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GB2136203B - Through-wafer integrated circuit connections - Google Patents

Through-wafer integrated circuit connections

Info

Publication number
GB2136203B
GB2136203B GB08305761A GB8305761A GB2136203B GB 2136203 B GB2136203 B GB 2136203B GB 08305761 A GB08305761 A GB 08305761A GB 8305761 A GB8305761 A GB 8305761A GB 2136203 B GB2136203 B GB 2136203B
Authority
GB
United Kingdom
Prior art keywords
wafer
device components
integrated circuit
circuit connections
connections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB08305761A
Other versions
GB2136203A (en
GB8305761D0 (en
Inventor
Thomas Meirion Jackson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STC PLC
Original Assignee
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephone and Cables PLC filed Critical Standard Telephone and Cables PLC
Priority to GB08305761A priority Critical patent/GB2136203B/en
Publication of GB8305761D0 publication Critical patent/GB8305761D0/en
Publication of GB2136203A publication Critical patent/GB2136203A/en
Application granted granted Critical
Publication of GB2136203B publication Critical patent/GB2136203B/en
Expired legal-status Critical Current

Links

Classifications

    • H10W15/00—
    • H10W15/01—
    • H10W40/47—
    • H10W70/611—
    • H10W70/635—
    • H10W72/075—
    • H10W72/5363—
    • H10W72/952—
    • H10W90/754—

Landscapes

  • Wire Bonding (AREA)

Abstract

Integrated circuit device components are provided at a first surface of a semiconductor wafer either by formation directly within the wafer (1 - Fig. 2) or bonding a separate chip (15) to the wafer (12 - Fig. 3). The wafer is provided with discrete electrical connections (13 - Fig. 3) extending therethrough from the first to the opposite surface either by diffusion and etching (Figs. 2 and 3), or forming dielectrically insulated conductive islands. The device components are electrically connected to the discrete connections at the first surface and external metallisation, forming contact pads (8), is provided at the second surface so that the overall package can be directly mounted to a substrate. The device components are encapsulated by a passivating layer (11) on the first surface (Fig. 2), or a cover (16) bonded to the first surface (Fig. 3). The packaging technique is particularly applicable to very high power integrated circuits of large areas and high pin count. <IMAGE>
GB08305761A 1983-03-02 1983-03-02 Through-wafer integrated circuit connections Expired GB2136203B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB08305761A GB2136203B (en) 1983-03-02 1983-03-02 Through-wafer integrated circuit connections

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB08305761A GB2136203B (en) 1983-03-02 1983-03-02 Through-wafer integrated circuit connections

Publications (3)

Publication Number Publication Date
GB8305761D0 GB8305761D0 (en) 1983-04-07
GB2136203A GB2136203A (en) 1984-09-12
GB2136203B true GB2136203B (en) 1986-10-15

Family

ID=10538872

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08305761A Expired GB2136203B (en) 1983-03-02 1983-03-02 Through-wafer integrated circuit connections

Country Status (1)

Country Link
GB (1) GB2136203B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8703603B2 (en) 2003-09-15 2014-04-22 Nuvotronics, Llc Device package and methods for the fabrication and testing thereof

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3516954A1 (en) * 1984-05-14 1985-11-14 Gigabit Logic, Inc., Newbury Park, Calif. MOUNTED INTEGRATED CIRCUIT
US4617730A (en) * 1984-08-13 1986-10-21 International Business Machines Corporation Method of fabricating a chip interposer
US5051811A (en) * 1987-08-31 1991-09-24 Texas Instruments Incorporated Solder or brazing barrier
FR2629665B1 (en) * 1988-03-30 1991-01-11 Bendix Electronics Sa ELECTRONIC CIRCUIT BOX
JPH0215652A (en) * 1988-07-01 1990-01-19 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
DE4318339A1 (en) * 1993-06-02 1994-12-08 Philips Patentverwaltung Sealed via for a ceramic substrate of a thick-film circuit and a method for producing the same
DE10229711B4 (en) * 2002-07-02 2009-09-03 Curamik Electronics Gmbh Semiconductor module with microcooler
US6825559B2 (en) 2003-01-02 2004-11-30 Cree, Inc. Group III nitride based flip-chip intergrated circuit and method for fabricating
EP1962344B1 (en) * 2007-02-25 2012-03-28 Samsung Electronics Co., Ltd Electronic device packages and methods of formation
US10319654B1 (en) 2017-12-01 2019-06-11 Cubic Corporation Integrated chip scale packages
CN111599743B (en) * 2020-07-06 2024-05-28 绍兴同芯成集成电路有限公司 Method for producing wafers using composite adhesive film combined with through-hole glass carrier structure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3343256A (en) * 1964-12-28 1967-09-26 Ibm Methods of making thru-connections in semiconductor wafers
USB428447I5 (en) * 1965-01-27
FR2013735A1 (en) * 1968-07-05 1970-04-10 Gen Electric Inf Ita
US3577037A (en) * 1968-07-05 1971-05-04 Ibm Diffused electrical connector apparatus and method of making same
DE2450902A1 (en) * 1973-10-30 1975-05-07 Gen Electric ELECTRICAL LADDER IN SEMI-CONDUCTOR DEVICES

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8703603B2 (en) 2003-09-15 2014-04-22 Nuvotronics, Llc Device package and methods for the fabrication and testing thereof

Also Published As

Publication number Publication date
GB2136203A (en) 1984-09-12
GB8305761D0 (en) 1983-04-07

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee