GB2133164A - Audio signal information display device - Google Patents

Abstract

An analog audio signal is converted into a digital signal by an A/D converter (ADC), and then the digital signal is processed by a computer having a central processing unit (CPU) and memories (ROM, RAM) for detecting the VU level, peak level etc. in the case that the audio signal is a stereophonic signal of two channels, the above-processing is effected in connection with both channels L and R. The computer outputs data indicative of patterns which are predetermined for respective items to be displayed including the VU level, peak level etc. A video display processor (VDP) responsive to the output data from the computer produces a video signal with which various patterns e.g. as in Fig. 4, are displayed on a screen of a display unit, such as a cathode-ray tube (CRT). <IMAGE>

Description

SPECIFICATION Audio signal information display device This invention relates to a display device which is capable of displaying various sorts of information, which are necessary during transmission, recording/reproducing and signal processing of an audio signal, on a display surface.

When transmitting, recording/reproducing, signal-processing an audio signal, the level, recording time or the like of the audio signal should be set taking into account the dynamic range, recording capacity of the transmission line, recording medium, used devices or the like, and therefore, meters for indicating the peak level or VU level of the audio signal, or a display device for indicating a maximum value of the peak level, as well as a timer have hitherto been used.

As meters or display devices for indicating a peak level or VU level, or as display devices for indicating the maximum level of the peak level, have generally been used a meter of the type having a needle, or a display device having lightemitting elements arranged. Furthermore, as a time has been used a mechanical clock or electronic digital clock or the like as is well known.

In order to effect transmission, recording/reproducing, and signal-processing of other sorts in satisfactory conditions, it is desirable that not only the VU level and the peak level are known respectively but also the relationship between these levels are directly visually seen. However, in the case that the VU level and phe peak level or the like are respectively indicated by way of separate meters, it is difficult to directly and visually know the relationship between the VU level and the peak level.

Moreover, it is desired recently that a display device which is capable of watching both image information (video information) and audio signal related thereto simultaneously, appears on the market.

The present invention has been developed in order to remove the above-described drawbacks inherent to the conventional display or indicator devices used for indicating audio signal information.

It is, therefore, an object of the present invention to provide a new and useful audio signal information display device which is capable of displaying various pieces of information simultaneously on a display surface or screen such as a cathode ray tube screen.

According to a feature of the present invention an analog audio signal is first A-D converted into a digital signal, and the digital signal is processed by a computer including a central processing unit and memories so that data indicative of predetermined patterns for indicating VU level, peak level etc. of the audio signal by way of corresponding patterns. The output data from the computer is fed to a video display processor which produces a video signal with which various patterns indicating the VU level, peak level etc.

are displayed on a display unit.

In accordance with the present invention there is provided an audio signal information display device comprising: an analog-to-digital converter for converting an audio signal into a digital signal; a central processing unit for computing a VU leval and a peak level on the basis of digital data which is within a predetermined time width, which digital data is obtained by said analog-to-digital converter, and for outputting predetermined pattern information corresponding to the magnitude and sort of the level by using the result of computing; and a video display processor responsive to output data from said central processing unit, so that one or both of the VU level and peak level of said audio signal is displayed on a display unit screen at real time.

In accordance with the present invention there is also provided an audio signal information display device comprising: an analog-to-digital converter for converting an audio signal into a digital signal; a central processing unit for computing a VU level, a peak level and a hold level of the peak level on the basis of digital data which is within a predetermined time width, which digital data is obtained by said analog-todigital converter, and for outputting predetermined pattern information corresponding to the magnitude and sort of the level by using the result of computing; and a video display processor responsive to output data from said central processing unit, so that the VU level and necessary data of peak level and the hold level of the peak level of said audio signal is displayed on a display unit screen at real time.

In accordance with the present invention there is further provided an audio signal information display device comprising: an analog-to-digital converter for converting an audio signal into a digital signal; a central processing unit for computing a VU level and a peak level on the basis of digital data which is within a predetermined time width, which digital data is obtained by said analog-to-digital converter, for computing maximum values of the VU level and the peak level, and for outputting predetermined pattern information corresponding to the magnitude and sort of the level by using the result of computing; and a video display processor responsive to output data from said central processing unit, so that the VU level, the peak level and necessary data of the maximum value of the VU level, and the maximum level of the peak level of said audio signal is displayed on a display unit screen at real time.

In accordance with the present invention there is still further provided an audio signal information display device comprising: an analoy-to-digital converter for converting an audio signal into a digital signal; a central processing unit for computing a VU level and a peak level on the basis of digital data which is within a predetermined time width, which digital data is obtained by said analog-to-digital converter, for outputting predetermined pattern information corresponding to the magnitude and sort of the level by using the result of computing, and for outputting given pattern information corresponding to timer information; and a video display processor responsive to output data from said central processing unit, so that one or both of the VU level and peak level of said audio signal is displayed on a display unit screen at real time, while said timer is also displayed on the display unit screen at real time.

In the case that the audio signal is a multichannel signal, such as a stereophonic signal of two channels, the above-processing is carried out in connection with each channel signal.

The object and features of the present invention will become more readily apparent from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings in which: Fig. 1 is a schematic block diagram of an embodiment of the display device according to the present invention; Fig. 2 is an example of a memory map of a video ram used in the embodiment of Fig. 1; Fig. 3 is an explanatory diagram of sections on a display unit screen of the display device of Fig.

1; Figs. 4 and 8 are diagrams showing examples of patterns on the display unit screen; Figs. 5 and 7 are flow charts showing the operation of the central processing unit used in the embodiment of Fig. 1; and Fig. 6 is an explanatory diagram of the storing state of sampled value data to storing regions.

The same or corresponding elements and parts are designated at like reference numerals throughout the drawings.

Fig. 1 is a block diagram of an embodiment of the display device according to the present invention. In Fig. 1, the references 1 and 2 are input terminals of respective channels of a 2channel signal, and in the following description, the input terminal 1 is for left channel (channel L) and the input terminal 2 is for right channel (channel R).

The references Bawl, BAr are buffer amplifiers; and the references BPFI and BPFr are band-pass filters, while the references FRI and FRr are fullwave rectifying circuits, where the subscripts I and r indicate the distinguishment between the left channel use and the right channel use. The above-mentioned band-pass filters have an identical passband so that necessary frequency range for measuring the peak level and the VU level of the audio signal is passed.

In the drawings, the reference TER is a timer, and the reference VR is a variable resistor for setting a time width which is set within the timer TER. The reference MPX is a multiplexer; CPU, a central processing unit; RAM a main memory; ROM, a read-only memory; VDP, a video signal generator (video display processor); V RAM, a video RAM (wherein RAM is a random-access memory); CRT, a display, and as the display is used a cathode-ray-tube in the following description.

The reference ADC in Fig. 1 is an analog-todigital converter, while the references 3, 4, 5a, and 5b are data busses. Furthermore, the reference RFC is an RF converter, and the reference TVS is a television receiver.

The video signal generator VDP functions as an interface between the video RAM V. RAM connected thereto via a data bus 4, and the central processing unit CPU, and is constructed such that it is capable of determining the contents of pictures by using various data stored in the abovementioned video RAM V.RAM, and of generating a composite video signal of a predetermined standard system.As this video signal generator VDP, for instance, may be used a video display processor VDP of Texas Instruments, Co., of the United States, introduced in ELECTRONICS November 1980 (pages 123--126) or an integral composite video generator disclosed in United States Patent No. 4,263,302 issued to Texas Instruments, and it is assumed that the above-mentioned video display processor is used as the video signal generator VDP in the following description.

In Fig. 1, although no address-decoder is shown, in actual structure an address-decoder responsive to address data from the central processing unit CPU is provided so as to respectively designate the addresses of the main memory RAM, read-only memory ROM AD converter ADC, multiplexer MPX, and the video display processor VDP. The central processing unit is preferably of high-speed and capable of commanding signed multiplication, which is a basic calculation of Fast Fourier Transform (FFT).

As the central processing unit CPU may be used an integrated circuit TMS9995 manufactured by Texas Instruments.

Fig. 2 is a drawing showing an example of a memory map of the video RAM V.RAM connected via the bus 4 to the video display processor VDP.

In the memory map of the video RAM of Fig. 2, 1024 bytes from address 0 to address 1023 are used as a sprite generator table (SPG); 768 bytes from address 1024 to address 1791 being used as a pattern name table (PNT); 128 bytes from address 1 792 to address 1919 being used as a sprite attribute table (SAT); 32 bytes from address 1920 to address 1951 being used as a color table (CT); and 96 bytes from address 1952 to address 2047 being unused yet; and 2048 bytes from address 2048 to address 4095 being used as a pattern generator table (PGT).

The pattern generator table PGT is capable of storing a specific pattern of 8 pixels by 8 pixels by using 8 bytes respectively for instance, and therefore 256 patterns of 8 by 8 pixels can be stored. The pattern information stored in the pattern generator table PGT is transmitted from the read-only memory ROM at an initial state of the device by the operation of the central processing unit~CPU. However, the pattern generator table PGT may of course be a read-only memory.

In the storing region including 8-byte portions of the pattern generator table PGT are stored specific patterns of 8 by 8 pixels are respectively stored, and respective specific patterns can be designated by pattern names assigned to respective storing regions in which the specific patterns are respectively stored. In the case of the pattern generator table PGT of Fig. 2, 256 patterns can be designated by way of 256 pattern names from pattern name &num;1 through pattern name 256.

Nextly, the pattern name table PNT comprises a storing capacity corresponding to a total number of displaying sections imagined on the screen of the display unit CRT so as to store information indicating which section is of which pattern name of the pattern generator table PGT.

In an example of Fig. 3, the total number of sections set in the display unit screen is [32 columnsx24 rows]=768, and since 1 byte is used as the amount of information for indicating 1 section, the pattern name table PNT has a storing capacity of 768 bytes as mentioned in the above.

In the case that a necessary number of patterns are stored in the pattern generator table PGT of the video RAM V.RAM, and that necessary pattern names assigned in correspondence with respective patterns are stored in the respective sections of the display unit screen of the pattern name table PNT, the video display processor VDP produces a composite video signal complying with a specific standard system where the contents of the picture is determined by information stored in the pattern name table PNT of the video RAM TRAM, information stored in the pattern generator table PGT, and information stored in the color table CT when necessary, and the produced composite video signal being fed to the display unit CRT for displaying a specific pattern on the screen of the displav unit CRT.

The above description is related to a case of displaying under a display mode in which a specific one of patterns stored in the pattern generator table PGT is displayed at a specific section among 768 sections, namely, so called graphic mode. When displaying a pattern with such a graphic mode, the position of the pattern is designated by the pattern name table PNT, and therefore, when it is intended to move a pattern on the display unit screen, the pitch of pattern movement on the display unit screen is 1 section (distance of 8 pixels).

In order to cause the pattern to move smoothly with the pitch of pattern movement on the display unit screen being made small, the pattern stored in the sprite generator table SGT is moved on the display unit screen at a pitch 1 pixel with a change in co-ordinates.

The pattern to be stored in the sprite generator table SGT is sprite data which may be of either 8 pixels by 8 pixels or 1 6 pixels by 1 6 pixels.

Respective patterns stored in the sprite generator table SGT are given sprite names separately as &num;0, #1 ...#N, a sprite surface corresponding to a pattern with respective sprite names are arranged so that smaller numerical values indicated by the sprite names have higher priority.

In the memory map of the video RAM V.RAM shown in Fig. 2, since 1024 bytes from address 0 to address 1023 are used as the sprite generator table SGT as described in the above, 128 patterns (sprite name &num;0 through &num;127) can be stored in the case of 8 pixels by 8 pixels in this case, and also 32 patterns (sprite name &num;0 through &num;31) can be stored in the case of 1 6 pixels by 1 6 pixels.

In the case that 2048 bytes are assigned to the sprite generator table SGT of the video RAM V RAM, it is a matter of course that the number of patterns which can be stored in the sprite generator table SGT is twice as much as the above example.

Since the sprite position (1 byte for designating each of vertical position and horizontal position), name of display sprite (1 byte), color code and display sprite termination code (1 byte) and the like are set in the sprite attribute table SAT by using 4 bytes for each one sprite, in the case that 128 bytes are used as the sprite attribute table SAT, information of 32 sprites is stored in the sprite attribute table SAT.

The position of a sprite is determined with a vertical position (a numerical value indicating the vertical order of picture point) and a horizontal position (a numerical value indicating the horizontal order of picture point) being written in the sprite attribute table SAT, where a coordinate of 49,152 picture points determined by 256 picture points (8 pixels by 32 sections) of horizontal direction (X direction) and 1 92 picture points (8 pixels by 24 sections) of vertical direction (Y direction) is provided wherein an origin of the sprite is set to the ' soft top end, and the movement of the sprite is effected with a pitch of 1 pixel.

According to the display device of the present invention a plurality of sorts of patterns are prestored in the pattern generator table PGT, sprite generator table SGT or the like, and the selection of patterns to be displayed on the display unit screen, the selection of pattern movement mode, or the like is effected by the data rewritten into the sprite attribute table SAT in correspondence with the VU level and the peak level of the audio signal as well as the maximum value of the VU level and maximum level of the peak level, and therefore a specific pattern is displayed on the display unit screen in a freely movable manner, while pattern selection and designation of pattern movement mode are effected by data written into the pattern name table PNT in correspondence with information of the peak level of the audio signal and the lapse of time within the timer or the like, so that it is possible to display a specific pattern on the display unit screen.

Fig. 4 shows an example of a displaying state of various sorts of information on the display unit screen of the display device according to the present invention. The characters L and R in Fig. 4 are display patterns used for indicting the distinguishment between channel L and channel R on the display unit screen, while symbols and numerals -oo, --30, --20, --1 5,... 4, 6, 8 and 10 are display patterns for indicating the signal level value in decibels (dB) on the display unit screen.

Furthermore, vertical lines shown above and below the above-mentioned numerals are a display pattern for indicating a scale on the display unit screen. Furthermore, a circle and numerals at the left top portion on the display unit screen show a display pattern for indicating a timer on the display unit screen.

Furthermore, white triangles pointing upward and downward are display patterns for indicating the maximum values of the VU levels on the display unit screen, while black triangles pointing upward and downward are display patterns for indicating the maximum value of the peak level on the display unit screen. Furthermore, a sentence formed by alphabets shown at the lower portion of the display unit screen is a display pattern for indicating brief contents to be displayed on the display unit screen.

The various display patterns of Fig. 4, which are to be displayed on the display unit screen, are prestored in the read only memory ROM to be prepared, and when starting the operation of the display device, the various display patterns stored in the above-mentioned read only memory ROM are transmitted via the central processing unit CPU and the video display processor VDP to the pattern generator table PGT and the sprite generator table SGT of the video ram V.RAM to be stored therein so as to be used for display operation on the display unit screen, and it will be described hereinafter in detail in this respect.

When the audio signal applied to the input terminals 1 and 2 is applied via respective bandpass filters BPFI and BFPr to the full-wave rectifying circuits FRI and FRr, a full-wave rectified output of the left channel audio signal is fed from the above-mentioned full-wave rectifying circuit to the multiplexer MPX as its input signal, while a full-wave rectified output of the right channel audio signal is fed from the above-mentioned fuilwave rectifying circuit to the multiplexer MPX as its input signal.

In the structural example of Fig. 1, in addition to the output from the above-mentioned full-wave rectifying circuits FRI and FRr, an output from the timerTER is also applied to the above-mentioned multiplexer MPX as its input signal, where the multiplexer MPX performs switching operation in accordance with a switching control signal applied from the central processing unit CPU so as to supply the above-mentioned three signals applied thereto to the AD converter ADC in a sequence.

As the timer TER of Fig. 1 may be used a sawtooth wave generator for example, and the period of the sawtooth wave to be outputted is arranged to be freely variably set by the adjustment of the variable resistor VR. As the sawtooth wave generator may be used as well known circuit arranged to generate a sawtooth wave by superposing pulses in a stepwise manner.

In place of the structure illustrated in Fig. 1 in which as the timer TER, may be used a circuit which generate an analog signal whose magnitude linearly increases along a time base, and the analog signal is fed via the multiplexer MPX to the AD converter ADC to be converted into a digital signal so as to be used as time information by the central processing unit CPU, a timer built in the central processing unit CPU may be used, and in the case that the timer built in the central processing unit CPU is used, the timer is set by manipulating timer input buttons (input buttons provided in correspondence with time values such as 30 minutes, 45 minutes, and 120 minutes) shown by imaginary line frame TERsw in Fig. 1.

The central processing unit CPU is arranged to operate in accordance with a flowchart of Fig. 5 so as to produce data necessary for displaying various levels of the audio signal and the timer, and to apply them to the video display processor VDP and the video ram V.RAM to cause the display unit screen to display as shown in Fig. 4.

In the flowchart of Fig. 5, in a step (21) power is applied to start the display device, and subsequently in step (22) initialization (system initialization) is effected to clear the AD converter ADC, the main memory RAM, the video ram V.RAM and the like, while register of the video display processor VDP is set and using region setting, in which it is determined which storing region of the video ram VRAM is used for which table, as well as operating mode setting is performed, and predetermined pattern information (for example, the pattern information of characters and numerals shown in Fig. 4, the pattern information of the timer, the pattern information of the vertical lines) is transmitted from the read-only memory ROM via the video display processor VDP to the pattern generator table PGT, and predetermined pattern information (for example, the pattern information of upward and downward white and black triangles shown in Fig. 4, the pattern information of the vertical lines and vertical bars) is transmitted from the read-only memory ROM to the sprite generator table SGT, and furthermore, sprite names, Y-ordinate, color data and the like are transmitted from the read-only memory ROM to the sprite attribute table SAT.

The central processing unit CPU repeatedly executes respective steps from step (23) to step (30), while the control of the multiplexer MPX and the AD converter ADC and storing of various input data to the main memory RAM are effected by an interrupt operation having step (31) through step (36) which interrupt operation is executed at a predetermined interval defined by an internal counter of the central processing unit CPU.

The interrupt operation having step (31) through step (36) will be described first.

Interruption occurs at a predetermined interval by the internal counter of the central processing unit CPU to effect switching control of the multiplexer MPX, conversion-starting operation of the AD converter ADC and data storage. Namely, in the step (31) a sampled value of the left channel signal is AD converted to be stored in the main memory RAM in the step (32), and in the step (33) a sampled value of the right channel signal is AD converted to be stored in the main memory RAM in the step (34), and further in the step (35) a sampled value of the timer value is AD converted to store the same into the main memory RAM in the step (36), terminating the interruption. The central processing unit CPU returns to control operation of the instant just before the interruption has occurred.

In the step (23), calculation of the VU level is made, and when calculating the VU level, signal level data of the audio signal of a predetermined time width T (for example, 300 ms) is required.

Namely, this is because that the VU level of the audio signal is obtained under a condition in which the audio signal is caused to rise with a time constant of 300 ms and to fall with a time constant of 300 ms.

When the time length of an audio signal used for the calculation of the VU level is expressed in terms of T, if N sampling values (sampling values of signal level of the audio signal) exist within the time length T, the calculation of the VU level is started with an arithmetical mean value of the N sampling values existing within the time length T being obtained.

For instance, assuming that T is 300 ms, and sampling period is 10 ms, the number of samples equals 30, and therefore, an arithmetical mean value of 30 sampling values is obtained.

The above-mentioned calculation effected by using N sampling values existing within the given period of time length T is effected respectively and in a sequence in connection with the left channel audio signal and the right channel audio signal stored in the main memory RAM in the above-described step (32) and the step (34), and it is advantageous for the purpose of easy calculation when the storing state of successive sampled data or respective channels with respect to the main memory RAM is selected as shown in Fig. 6.

Namely, in Fig. 6, the references M1, M2. . . Mn are n storing regions capable of storing N sampled data, where respective storing regions M1 through Mn are arranged to store different sampled values for each section of the total of n portion indicated at &num;1, #2, #3 .. #n bordered by vertical lines in the drawing. In Fig. 6, only the storing region used for storing the audio signal of one channel is shown, and therefore it is necessary to provide two sets of storing regions M1 through Mn such as shown in Fig. 6 for storing two-channei audio signal of L and R.

Since the calculation of the VU level, the calculation of the peak level, and other calculations, which will be described hereinafter, are identical for both the L-channel signal and the R-channel signal, the following description is common to both channels L and R.

The following description of the calculation of the VU level is made under an assumption that successive sampling value data of an audio signal are stored in the main memory RAM from the state that the main memory has been cleared for simplicity.

A sampled value of the audio signal at time tl is AD converted and it is assumed that sampled value data outputted from the AD converter ADC is expressed in terms of S1. Similarly, sampled value data respectively obtained at times t2, t3 tn are expressed by S2,S3... Sn, and it is arranged such that sampled value data S1, S2... Sn successively obtained along the time base are stored in the above-mentioned n storing regions M1 through Mn of the main memory RAM in the following manner.

Namely, sampled value data S1 is stored in the section &num;1 of the storing region M1 of the main memory RAM, while sampled value data S2 is stored in the section &num;2 of the storing region M1 and in the section &num;1 of the storing region M2, sampled value data s3 being stored in the section &num;3 of the storing region M1, in the section &num;1 of the storing region M2, and in the section &num;1 of the storing region M3, and in this way successive sampled value data are stored in the main memory RAM so that the storing state is as shown in Fig. 6.

Under the condition that N sampled value data of the audio signal are sent to the main memory RAM in sequence, which has been cleared, when the sampled value data S1 through Sn are stored in all the sections &num;1 through &num;n of the storing region Ml, and subsequently (N+ 1)th stored value data of the audio signal is sent to the main memory RAM, the state of the storing region M2 is such that sampled value data are stored in all the sections &num;1 through &num;n of the storing region M2. After this, successive sampled value data are sent to the main memory RAM in the same manner as the above, so that the state of the storing regions M3, M4... Mn are such that sampled value data are stored in all the sections &num;1 through &num;n in sequence.

Accordingly, an arithmetical mean value of the signal level for a predetermined time length T can be obtained at every sampling period on time base of the audio signal if all the sampled value data stored in the storing region M1 are read out to obtain an arithmetical mean value when the storing region M1 has come to a state that sampled value data has been stored in all the section &num;1 through &num;n with N sampled value data of the audio signal being sent to the main memory RAM which has been cleared, and subsequently all the sampled value data stored in the storing region M2 are read out to obtain an arithmetical mean value when the storing region M2 has come to a state that sampled value data has been stored in all the sections &num;1 through &num;;n with N sampled value data of the audio signal being sent to the main memory RAM, and after this all the sampled value data are read out from the storing regions M3, M4... Mn respectively to obtain an arithmetical mean value when the storing regions M3, M4... Mn have come to a state that sampled value data have been stored in all the sections &num;1 through &num;n thereof.

It is apparent that the above-mentioned respective storing regions M1 through Mn are cyclically used for successive calculations since the way of storing is such that the abovementioned successive sampled value data are stored in sequence into the sections #1, ...

when the successive sampled value data are sent to the main memory RAM after sampled value data have been stored into all the regions &num;1 through &num;n of a given storing region, and after the compietion of storing of sampled value data into all the sections of all the storing regions M1 through Mn, the stored data of respective storing regions M1, M2. . . Mn, M1, M2. . . change at 1 sampling period Ts(Ts=T/n), while respective storing regions M1 through Mn assume a state that N sampled value data of time length Tare respectively stored.

When the sampled value data outputted from the AD converter ADC in sequence is stored into respective storing regions M1 through Mn of the main memory RAM in sequence to the main memory RAM which has been cleared, and the sampled value data S1 through Sn have been stored in all the sections &num;1 through &num;n of the storing region Ml, the central processing unit CPU derives the sampled value data stored in all the sections &num;1 through &num;n of the abovementioned storing region M1 so as to execute calculation for obtained an arithmetical mean value as described in the above, and then compares the result of the calculation with a result of calculation of VU level of a former cycle, which latter result has been stored in the main memory RAM.

Assuming that an arithmetical means value (S1+S2+ ... +Sn)/n of sampled value data S1 through Sn stored in all the sections &num;1 through &num;n of the storing regions M1 is expressed by Sb1, and the result of calculation of VU level of the former cycle is expressed by SvuO, the result of comparison between Sbl and SvuO equals generally one of the following three: SvuO < Sbl (1) SuvO=Sbl (2) SuvO > Sb1 (3) In the case that the result of comparison is either (1) or (2), the VU level stored in the main memory RAM is rewritten regarding the value of Sb1 as a new VU level Svu 1.In the case that the result of comparison is (3), the VU level of the former cycle is multipled by a factor K, which is determined in correspondence with the falling time constant (for exa mple, 300ms) of the VU meter, to obtain KSvuO, and then KSvuO is compared with Sb1.

KSvuO < Sbl (4) KSvuO=Sb1 (5) KSvuO > Sbl (6) The result of the above-mentioned comparison may be one of the three cases shown by (4) through (6), and if the result of comparison is either (4) or (5), the VU level stored in the main memory RAM is rewritten regarding Sb1 as a new VU level value (SVu 1 (present VU level value). In the case that the result of comparison is (6), the VU level stored in the main memory RAM is rewritten regarding the new value of KSvuO as a new VU level.

In the above example, since the calculation executed in connection with sampled value data S1 through Sn stored in the storing region M1 is a first calculation (a first calculation executed after the main memory RAM has been cleared), in the above example, it is a matter of course that the arithmetical mean value is stored into the main memory RAM as the VU level Svu1 by rewriting.

Nextly, when the storing region M2 assumes a state that sampled value data have been stored into all the sections &num;1 through &num;n thereof, the central processing unit CPU calculates a new VU level by obtaining an arithmetical mean value Sb2 in connection with sampled value data S2 through Sn+1 stored in the storing region M2, and by comparing this Sb2 with the VU level Svu 1 obtained in the former cycle. After this, calculations of new VU levels are effected in sequence in the same manner as the above each time one sampling period elapses, and thus the new VU levels obtained in this way are stored in predetermined storing regions of the main memory RAM by rewriting.

The above-described calculations of the VU level are executed in the step (23) of the fiowchart of Fig. 5, and the calculations of the VU level in the step (23) are executed successively and respectively in connection with channel L and channel R, and therefore it is a matter of course that the VU level of channel L and the VU level of channel R are respectively stored into predetermined storing regions of the main memory RAM.

Nextly, calculations of the peak level in the step (24) of Fig. 5 will be described. The calculations of the peak level are executed by deriving the newest two sampled value data among the sampled value data used for the above-mentioned calculation of the VU level, and the peak level of the former cycle.Namely, taking the sampled value data S1 through Sn stored in the abovementioned storing region M1 as an example, the peak level is determined by executing a predetermined calculation with two sampled value data Sn-1 and Sn being compared with each other, and the result of the comparison may assume one of the following three cases (7) through (9):: Sn-1 > Sn (7) Sn-1=Sn (8) Sn-i < Sn (9) When the two sampled value data Sn-i and Sn have the relationship of (8), a provisional peak level value Snp is determined regarding that the present peak level value is lower than Sn by 1 dB, and subsequently the above-mentioned provisional peak level value Snp is compared with a peak level Spl of a former cycle, which has been stored in the main memory RAM: Spl < Snp (10) Spl=Snp (11) Spl > Snp (12) In the case that the two values have the relationship of (10) or (11), the provisionaily determined peak level Snp is determined as the present peak level which is stored into the main memory RAM as the present peak level value by rewriting.

In the case that the peak level value Spl and the provisional peak level value Snp have the relationship of (12), a calculation in which the former cycle peak level Sp is multiplied by a factor Kp determined in correspondence with the falling time constant (for instance, 1.5 sec) of the peak level meter, to obtain KpSpl, and thereafter this KpSpl is compared with the above-mentioned provisional peak level Snp.

KpSpl < Snp (13) KpSpl=Snp (14) KpSpl > Snp (15) The result of the above-mentioned comparison will result in one of the three cases of (13) through (15), and when the result of comparison is the case of either (13) or (14), Snp is determined as a new peak level value Snpl,and is then stored in the main memory RAM. as the present peak level value.

In the case that the result of comparison is (15), KpSpl, which is obtained by multiplying a former cycle peak value Spl by a factor Kp, is determined as a new peak level value and is stored in the main memory as the present peak level value.

Nextly, when two sampled value data Sn-i and Sn have a relationship of (7) or (9), and when one of the two sampled value data used for comparison shows a value close to 0, a level which is lower than a peak level indicated by a larger sampled value data by 1 5 dB is determined as a present provisional peak level Snp, which is then compared with a former cycle peak level data Spl stored in the main memory RAM. Then a present peak level Snp1 is determined by checking which case of (10) through (12) corresponds to the result of comparison in the same manner as the above case described with reference to the relationships of (10) through (15), and is stored in the main memory RAM by rewriting.

When two sampled value data Sn-1 and Sn have a relationship of either (7) or (9), and when the two sampled value used for comparison are in the already described two cases, namely, when in an intermediate state between a case in which two sampled value data used for comparison are equal to each other, and a case in which one of the two samples value data used for comparison is close to 0, a predetermined level value, such as --10 dB, -5 dB and -3 dB, is determined as a provisional peak level value Snp when the difference between two sampled value data corresponds to a step of a predetermined magnitude.Then the provisional peak level value Snp is compared with a former cycle peak level value Spl, and a new peak level Snpl is determined by using the result of comparison in accordance with the peak level determining method described with reference to (10) through (15) so as to be stored in the main memory RAM by rewriting as a present peak level value.

The above-described calculation executed as the calculation of peak level shown in the flowchart of Fig. 5 is also effected in sequence in connection with the storing regions M1, M2 ... Mn, and also effected in sequence and respectively in connection with channel L and channel R in the same manner as the calculation of VU level which has been described.

Nextly, calculation of peak level holding executed in the step (25) of the flow chart of Fig.

5 is effected in accordance with steps shown in Fig. 7 in detail. Namely, in a step (25A) a former peak level hold value stored in the main memory RAM and a present peak level value determined in the step (24) and stored in the main memory are both read out to be compared with each other to see whether the present peak level is greater or not, and if the present peak level is greater (the case of YES), the timer for peak holding is set in a step (25by, and then the present peak level is stored in the main memory RAM as a new peak level hold value to terminate execution; and if the result of the comparison in the above-mentioned step (25A) is NO, namely, the former peak level hold value is greater than the present peak value, counting down of the timer for peak holding is continued in a step (25C), and in a step (25D) it is checked whether the time (for instance, 3 sec) set in the timer for peak holding has elapsed or not, and if NO, execution is terminated; if YES, a step (25E) is'executed so that the former peak hold value is stored again in the main memory RAM as a hold value of a new peak level.

Nextly, in a step (26), the greatest VU level and peak level since the display device has started operation with its power being turned on in the step (21), and the obtained values are stored in the main memory RAM respectively.

Nextly, in a step (27), the proportion of time value since the display device has started operation with its power being turned on in the step (21), with respect to a scheduled operating time of the device (in the case that the device is a tape recorder, a time value determined by the used magnetic tape) is calculated by using the output of the timer TER, and the result thereof is stored in the main memory RAM.

Nextly, in a step (28), it is determined how the indication of the VU level value calculated in the step (23), the peak level value calculated in the step (24), the peak level hold value calculated in the step (25), the maximum value of the VU level value and the peak level value calculated in the step (26) correspond to the position on the display marked with degrees by decibel values, while it is also determined how the time proportion obtained by the step (27) occupies the positions on the display unit screen, and in a step (29), data to be written into the pattern name table PNT and the sprite attribute table SAT are generated in correspondence with data values determined in the step (28), and then in a step (30), the above-mentioned data is transmitted via the video display processor VDP to the video ram V.RAM so that the the video display processor VDP generates a composite video signal by using data written into the video ram V.RAM, to send the same to the display unit CRT and RF converter RFC. As a result, various signal levels and time proportion are displayed by way of given patterns on the screen of the display unit CRT and the screen of the display unit of the monitor TV receiver TVS which receives the output signal from the above-mentioned RF converter.

An example of the state of display of the various levels and time proportion (timer display) displayed on the display unit screem as described in the above will be described hereinbelow.

Although power is supplied to enable the display device to operate, the display on the screen of the display unit CRT is as shown in Fig.

8 in the absence of inputs to input terminals 1 and 2. When Land R channel signals are applied to the input terminals 1 and 2, an instantaneous signal in connection with channel L is displayed as a pattern in which vertical bars are arranged betweenoo and the peak level of the signal at the left of the character L on the screen of the display unit CRT, and an instantaneous signal in connection with channel R is displayed as a pattern in which vertical bars are arranged between -oo and the peak level of the signal at the left of the character R on the screen of the display unit CRT, where the indication of the above-mentioned instantaneous signal signal is effected such that the length of the arrangement of the vertical bars expands and contracts in accordance with the variation of the peak level of the signal.

The indication form -oo to the peak level of the signal effected by the arrangement of the vertical bars is readily performed with a pattern of vertical bars being written in the pattern generator table PGN, and with a region where the abovementioned bar-like pattern is to be arranged in accordance with the data of the signal peak level being determined, and with pattern names being written into the pattern name table in correspondence with regions. In this case, it is easy to arrange such that the vertical bars to be displayed at the left of O dB is made light blue, while the vertical bars to be displayed at the right of O dB is made light red for instance.

Since the position of the peak of the L and R channel signals changes at each instance, it is significant to arrange such that a peak level of the past close to the present instance is continuously displayed for a given period of time (such as 3 sec), and this can be achieved by displaying a peak level hold value by way of a specific pattern such as vertical bars. Vertical bar patterns indicated at the reference PH in Fig. 4 are peak level hold values.

When a new peak level of the signal exceeds the peak level, the patterns PH of the peak level hold values are written by the same as described in the above. However, when a new peak level, which exceeds the prior peak level, does not appear for a predetermined period of time (for instance, 3 sec), display is continuously performed for the above-mentioned predetermined period of time (for instance, 3 sec).

Peak level hold values may be indicated by using either the pattern generator table PGT and the pattern name table PNT, or the sprite generator table SGT and the sprite attribute table SAT.

The VU level is indicated by white vertical lines as the references VU in Fig. 4 on the screen of the display unit CRT. The indication of the VU level may be readily performed by using the sprite generator table SGT and the sprite attribute table SAT.

The pattern VUm indicated by white triangles in Fig. 4 are patterns for showing the maximum values of the VU levels, while the pattern Pm indicated by black triangles in Fig. 4 are patterns for showing the maximum values of the peak levels, where these patterns VUm and Pm are readily displayed by using the sprite generator table SGT and the sprite attribute table SAT.

Furthermore, the time proportion pattern indicated at the reference Tm can also be displayed by using the pattern generator table PGT and the pattern name table PNT.

As is apparent from the above detailed description, since the peak level, peak level hold value, VU level, maximum value of the VU level, maximum value of the peak level of an audio signal and time proprtion etc can be displayed at real time such that all the information pieces are arranged on a single display unit screen so as to be visually seen simultaneously, signal level adjustment and watching the same are satisfactorily effected when transmitting and recording/reproducing the audio signal.

Furthermore, since it is easy to enlarge the display unit screen, it is readily achieved so that information is seen simultaneously by a number of persons. Moreover, monitoring of a video signal and monitoring of an audio signal can be effected in parallel. Furthermore, consumer use TV receivers can be utilized to readily display the level of signals of a stereophonic reproducing device for instance. In this way the device according to the present invention can be effectively used in various fields in various manners.

Claims (13)

Claims

1. An audio signal information display device comprising: (a) an analog-to-digital converter for converting an audio signal into a digital signal; (b) a central processing unit for computing a VU level and a peak level on the basis of digital data which is within a predetermined time width, which digital data is obtained by said analog-to-digital converter, and for outputting predetermined pattern information corresponding to the magnitude and sort of the level by using the result of computing; and (c) a video display processor responsive to output data from said central processing unit, so that one or both of the VU level and peak level of said audio signal is displayed on a display unit screen at real time.

2. An audio signal information display device comprising: (a) an analog-to-digital converter for converting an audio signal into a digital signal; (b) a central processing unit for computing a VU level, a peak level and a hold level of the peak level on the basis of digital data which is within a predetermined time width, which digital data is obtained by said analog-to digital converter, and for outputting predetermined pattern information corresponding to the magnitude and sort of the level by using the result of computing; and (c) a video display processor responsive to output data from said central processing unit, so that the VU level and necessary data of peak level and the hold level of the peak level of said audio signal is displayed on a display unit screen at real time.

3. An audio signal information display device comprising: (a) an analog-to-digital converter for converting an audio signal into a digital signal; (b) a central processing unit for computing a VU level and a peak level on the basis of digital data which is within a predetermined time width, which digital data is obtained by said analog-to-digital converter, for computing maximum values of the VU level and the peak level, and for outputting predetermined pattern information corresponding to the magnitude and sort of the level by using the result of computing; and (c) a video display processor responsive to output data from said central processing unit, so that the VU level, the peak level and necessary data of the maximum value of the VU level, and the maximum level of the peak level of said audio signal is displayed on a display unit screen at real time.

4. An audio signal information display device comprising: (a) an analog-to-digital converter for converting an audio signal into a digital signal; (b) a central processing unit for computing a VU" level and a peak level on the basis of digital data which is within a predetermined time width, which digital data is obtained by said analog-to-digital converter, for outputting predetermined pattern information corresponding to the magnitude and sort of the level by using the result of computing, and for outputting given pattern information corresponding to timer information; and (c) a video display processor responsive to output data from said central processing unit, so that one or both of the VU level and peak level of said audio signal is displayed on a display unit screen at real time, while said timer is also displayed on the display unit screen at real time.

5. An audio signal information display device as claimed in Claim 1, further comprising a plurality of input terminals for receiving a plurality of analog audio input signals, and a multiplexer for selectively transmitting one of said analog audio input signals as said audio signal fed to said analog-to-digital converter.

6. An audio signal information display device as claimed in Claim 2, further comprising a plurality of input terminals for receiving a plurality of analog audio input signals, and a multiplexer for selectively transmitting one of said analog audio input signals as said audio signal fed to said analog-to-digital converter.

7. An audio signal information display device as claimed in Claim 3, further comprising a plurality of input terminals for receiving a plurality of analog audio input signals, and a multiplexer for selectively transmitting one of said analog audio input signals as said audio signal fed to said analog-to-digital converter.

8. An audio signal information display device as claimed in Claim 4, further comprising a plurality of input terminals for receiving a plurality of analog audio input signals, a timer for producing an analog signal indicative of lapse of time, and a multiplexer for selectively transmitting one of said analog signals, which are fed from said input terminals and said timer, as said audio signal fed to said analog-to-digital converter.

9. An audio signal information display device as claimed in Claim 5, wherein said central processing unit is programmed to control said multiplexer so as to select one of said plurality of analog signals in sequence, thereby causing said video display processor to produce a video signal with which various pieces of information fed to said multiplexer are simultaneously displayed on said display unit screen.

10. An audio signal information display device as claimed in Claim 6, wherein said central processing unit is programmed to control said multiplexer so as to select one of said plurality of analog signals in sequence, thereby causing said video display processor to produce a video signal with which various pieces of information fed to said multiplexer are simultaneously displayed on said display unit screen.

ii. An audio signal information display device as claimed in Claim 7, wherein said central processing unit is programmed to control said multiplexer so as to select one of said plurality of analog signals in sequence, thereby causing said video display processor to produce a video signal with which various pieces of information fed to said multiplexer are simultaneously displayed on said display unit screen.

12. An audio signal information display device as claimed in Claim 8, wherein said central processing unit is programmed to control said multiplexer so as to select one of said plurality of analog signals in sequence, thereby causing said video display processor to produce a video signal with which various pieces of information fed to said multiplexer are simultaneously displayed on said display unit screen.

13. An audio signal information display device constructed and arranged to operate substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.