GB2132030A - Electronic chip components - Google Patents
Electronic chip components Download PDFInfo
- Publication number
- GB2132030A GB2132030A GB08126944A GB8126944A GB2132030A GB 2132030 A GB2132030 A GB 2132030A GB 08126944 A GB08126944 A GB 08126944A GB 8126944 A GB8126944 A GB 8126944A GB 2132030 A GB2132030 A GB 2132030A
- Authority
- GB
- United Kingdom
- Prior art keywords
- termination
- chip
- components
- pattern
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 11
- 239000011159 matrix material Substances 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 3
- 239000010409 thin film Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000012360 testing method Methods 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 239000000654 additive Substances 0.000 claims description 2
- 230000000996 additive effect Effects 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 claims description 2
- 230000001939 inductive effect Effects 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 238000010998 test method Methods 0.000 claims description 2
- 238000000427 thin-film deposition Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
- H01G2/02—Mountings
- H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
- H01G2/065—Mountings specially adapted for mounting on a printed-circuit support for surface mounting, e.g. chip capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C13/00—Resistors not provided for elsewhere
- H01C13/02—Structural combinations of resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/006—Apparatus or processes specially adapted for manufacturing resistors adapted for manufacturing resistor chips
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
A specially designed substrate, with holes linking the front and back faces, enables processing by thick film, thin film or other deposition method to be carried out while chips are still in a matrix array. The processed chip is then provided with end terminations often arranged so that conductors can be bridged on the main assembly element, to economise on space, and be tested and adjusted while in the matrix. The invention may be applied to chip resistors, inductors or other components. <IMAGE>
Description
SPECIFICATION
Electronic chip components
A novel manufacturing method
Currently chip electronic components especially chip resistors that require manufacture involving a base material such as ceramic and also a full wrap around end termination, start through processing as a matrix array. To produce full termination, however, separation has to take place and the individual chips are then difficult to handle through the following stages of end termination, adjustment and test.
The basis of this application is a specially designed substrate where all processing may be carried out while the chips are still in the array, the second part of the claim being the process method for producing the end termination.
Description ofthe basic design. (See Figure 1).
The base material is divided into the usual matrix of individual chip areas but instead of a means being designed in for snapping or otherwise separating prior to application of the end termination, holes are made linking the front and back face of the base material along the lines between each chip.
These holes may be circular or rectangular in shape but have the following advantages for a particular application.
If a rectangular hole is placed alongside the component element, for example with a chip resistor, the resistive material, microcracking will not occur in the base material adjacent to it and thus stability will be improved.
A similar rectangular hole may be placed along the termination or conductor edge which will be ideal for chip components to be mounted on rigid thermally compatible material, however, with the main application of chip components likely to be on non rigid thermally incompatible material the provision of one or several round holes along the termination edge linked by a snap line had the advantage of increasing the resitance to mechanical stress of the solder or alternative joint between the chip and the main carrier thus improving stability.
Processing of the base
To describe this the particular example of chip resistor is chosen but it would equally apply to the manufacture of inductors, transformers, capacitors and similar components or for any application where it is desirable to produce many identical components as an array. Note that in the case of inductive elements a central hole may be placed in the chip to allow passage for core. Coils may be manufactured by any process such as thick film printing, thin film deposition pr simple enamelled copper wire turns attached to the upper face of the base material.
Processing by thick film technology
The following steps may be interchanged or even omitted as desired.
1) Print back face termination pattern including conductive material through termination hole. Dry and fire.
2) Invert base.
3) Print front face termination pattern including conductive material through termination hole. Dry and fire.
4) Print resistor material. Dry and fire.
5) Adjust to required value.
6) Test.
7) Separate.
Proces by thin film techniques
Again the steps are interchangable and may be omitted or added as desired.
1) Diffuse on back termination pattern and include diffusion into termination edge hole(s).
2) Diffuse on front termination pattern and include diffusion into termination hole(s).
3) Diffuse on resistor pattern.
4) Adjust value.
Other alternative process
Similar procedures may be adopted when other material application methods are used, additive or substrative in nature. Pattern generation being similarly by mask, screen or resist coating.
1. A method of manufacturing electronic chip components whereby the termination may be end, edge or face. Connection may be achieved between the top and bottom faces whilst the conductor material is deposited on those faces when producing an end or edge termination.
2. A method whereby adjustment and testing of the conduction patterns are enabled by the conduction pattern layouts whilst in the matrix form.
3. A method whereby bridging of conductors on a main circuit element, to which the chip may be attached, can be achieved by the chip component, and hence simplify the main element conduction pattern.
4. A method of ensuring high accuracy registration of a multiplicity of components during processing.
5. A process for the manufacture of electronic chip components embodying any, or all, of the foregoing claims.
6. A method of testing a multiplicity of chip components.
7. A method of processing a multiplicity of chip components.
8. A method of marking a multiplicity of chip components.
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (8)
1. A method of manufacturing electronic chip components whereby the termination may be end, edge or face. Connection may be achieved between the top and bottom faces whilst the conductor material is deposited on those faces when producing an end or edge termination.
2. A method whereby adjustment and testing of the conduction patterns are enabled by the conduction pattern layouts whilst in the matrix form.
3. A method whereby bridging of conductors on a main circuit element, to which the chip may be attached, can be achieved by the chip component, and hence simplify the main element conduction pattern.
4. A method of ensuring high accuracy registration of a multiplicity of components during processing.
5. A process for the manufacture of electronic chip components embodying any, or all, of the foregoing claims.
6. A method of testing a multiplicity of chip components.
7. A method of processing a multiplicity of chip components.
8. A method of marking a multiplicity of chip components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08126944A GB2132030B (en) | 1981-09-07 | 1981-09-07 | Electronic chip components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08126944A GB2132030B (en) | 1981-09-07 | 1981-09-07 | Electronic chip components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2132030A true GB2132030A (en) | 1984-06-27 |
| GB2132030B GB2132030B (en) | 1986-10-08 |
Family
ID=10524344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08126944A Expired GB2132030B (en) | 1981-09-07 | 1981-09-07 | Electronic chip components |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2132030B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4794367A (en) * | 1985-12-19 | 1988-12-27 | Marconi Electronic Devices Limited | Circuit arrangement |
| FR2627007A1 (en) * | 1988-02-05 | 1989-08-11 | Eurofarad | Decoupling capacitor for integrated circuit |
| GB2269057A (en) * | 1992-05-27 | 1994-01-26 | Fuji Electric Co Ltd | Thin film transformer |
| WO1998045856A1 (en) * | 1997-04-07 | 1998-10-15 | Ford Global Technologies, Inc. | Meniscus-shaped terminations for leadless electronic components |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1089923A (en) * | 1964-09-12 | 1967-11-08 | Siegfried Richard Waller Kaule | Method and apparatus for testing using ultrasonic pulse signals |
-
1981
- 1981-09-07 GB GB08126944A patent/GB2132030B/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1089923A (en) * | 1964-09-12 | 1967-11-08 | Siegfried Richard Waller Kaule | Method and apparatus for testing using ultrasonic pulse signals |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4794367A (en) * | 1985-12-19 | 1988-12-27 | Marconi Electronic Devices Limited | Circuit arrangement |
| FR2627007A1 (en) * | 1988-02-05 | 1989-08-11 | Eurofarad | Decoupling capacitor for integrated circuit |
| GB2269057A (en) * | 1992-05-27 | 1994-01-26 | Fuji Electric Co Ltd | Thin film transformer |
| US5420558A (en) * | 1992-05-27 | 1995-05-30 | Fuji Electric Co., Ltd. | Thin film transformer |
| GB2269057B (en) * | 1992-05-27 | 1996-05-01 | Fuji Electric Co Ltd | Thin film transformer |
| US5572179A (en) * | 1992-05-27 | 1996-11-05 | Fuji Electric Co., Ltd. | Thin film transformer |
| WO1998045856A1 (en) * | 1997-04-07 | 1998-10-15 | Ford Global Technologies, Inc. | Meniscus-shaped terminations for leadless electronic components |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2132030B (en) | 1986-10-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |