GB2121630A - Improved inverter circuit - Google Patents

Abstract

An inverter comprises a transistor oscillator including a transistor (20) connected to a coupling transformer (10) which is arranged to provide oscillation maintaining feedback from a winding (11) connected to the collector of the transistor (20) to a winding (13) connected in the base circuit of the transistor (20). A voltage limiting circuit (41', 70) is connected to a further winding (12b) of the transformer and acts to limit the overswing voltage appearing at the collector of the transistor (20) by providing a voltage sink effect which controls the mark-space ratio of the transistor (20) by maintaining the non-conduction period until the transformer (10) has reset. An inhibiting circuit (150) acts to clamp the voltage of the node where 71' 74 and 154 meet for a short preset period after the end of the conduction period of the transistor (20) to prevent spurious turn-on of the transistor during that period due to voltages in the winding (13), and thereby to allow a greater range of (i.e. lower) mark-space ratio to be utilised <IMAGE>

Description

SPECIFICATION Improved inverter circuit The present invention relates to improvements in inverter circuits of the kind in which switching of a D.C. power supply at a high frequency through one winding of a transformer produces an output at another winding of the transformer which may be rectified to produce a controllable D.C. output.

Our European Patent Application Publication No. 0,018,186 discloses a number of such circuit arrangements derived from the socalled blocking oscillator forward inverter.

The object of the present invention is to provide an improved inverter circuit of the above type in which the control range is increased.

The present invention provides an inverter comprising a semiconductor switch oscillator including a semiconductor switch having a switched current path from a direct current power source, the state of conduction of the semiconductor switch being responsive to a switching signal at a control terminal thereof, a coupling transformer arranged to provide oscillation maintaining feedback from a first winding thereof disposed in the switched current path of the semiconductor switch to a second winding thereof arranged to provide said switching signal wherein at the end of each conductive period of the semiconductor switch an overswing voltage higher than that of the power source appears at the first winding of the coupling transformer, a voltage limiting circuit arranged effectively to limit the overswing voltage appearing at the first winding of the coupling transformer to a determined value in such a manner as to maintain the semiconductor switch non-conductive within each operating cycle of the oscillations until the coupling transformer has reset, and an inhibiting means responsive to the switching signal provided by the second winding to inhibit the semiconductor switch from being rendered conductive for a preset period after termination of conduction of the semiconductor switch, thereby to avoid spurious switching of the semiconductor switch during the preset period and thus allow an increased control range of mark-to-space ratio to be achieved.

The inhibiting of the semiconductor switch is preferably achieved by a clamping circuit arranged to clamp the second (control) winding during the preset period, that period being defined by the discharge of a capacitor previously charged from the second winding during the preceding conductive period.

Features and advantages of the present invention will become apparent from the following description of an embodiment thereof, given by way of example, when taken with the accompanying drawings, in which: Figure 1 is a circuit diagram of a previously proposed circuit, and Figure 2 is a circuit diagram similar to that of Fig. 1 but incorporating an improvement according to the invention.

Referring to Fig. 1, there is shown an inverter circuit as disclosed in the abovementioned patent application. Reference is directed to this application for a complete description of the operation of the circuit, but a brief description follows with particular emphasis on the feature of interest in the present invention. The disclosed inverter is based on a transistor oscillator which includes a transistor 20 connected to a coupling transformer 10 arranged to provide oscillation maintaining feedback from a winding 11 connected to the collector of transistor 20 to a winding 1 3 connected in the base circuit of transistor 20.

A voltage limiting circuit 41' controlling a transistor 70 connected to one part of the output winding 1 2b acts to limit the overswing voltage appearing at the collector of the transistor 20 after turn-off of the transistor by providing a voltage sink effect which controls the turn-off period of the transistor 20 within each operating cycle. This is achieved by delaying the time of turn-on of the transistor 20 until transformer reset has occurred and the volt-time products of the conductive and non-conductive periods of each cycle are equal.

A resetting transistor 80 is included to determine the end of each operating cycle.

Resistor 85 and capacitor 86 have values selected so that prior to saturation of transformer 10, transistor 80 is turned on to provide a definite and abrupt end to the working cycle. Consequently, the duration of each pulse can be accurately determined.

A diode 90 is connected in parallel with resistor 85 in such a way that the diode is conductive when the base of transistor 80 becomes positive with respect to the feedback winding potential at the other end of resistor 85. This has the effect of resetting the base voltage of transistor 80 to a negative potential varying in accordance with the voltage present on winding 1 2b in accordance with the voltage limiting control circuit 41'. The effect of this is that, during conduction of transistor 20, capacitor 86 is charged via resistor 85, transistor 80 turning on once capacitor 86 is sufficiently charged. This turns off transistor 20. Diode 90 connected across resistor 85 is rendered conductive when the base of transistor 80 becomes positive with respect to the potential at winding 13, i.e. when transistor 20 is turned off.The base voltage of transistor 80 is then reset to a negative voltage dependent on the overswing voltage limit on the collector of transistor 20 as set by the control circuit 41'. When transistor 20 turns on after transformer reset, capacitor 86 charges from this negative voltage via resistor 85 to a voltage approximately 0.6V positive with respect to the emitter of transistor 80, whereupon transistor 80b turns on bringing an end to each switching cycle of transistor 20. A decrease in the overswing voltage limit will thus result in a decrease in the "ON" time and an increase in the "OFF" time, so that the circuit will operate at substantially constant frequency, but with a variable markspace ratio dependent on the load presented to the inverter.

Whilst the circuit will theoretically operate as discussed, it is found in practice that at low levels of control voltage across winding 1 2b (corresponding to a short period of conduction of transistor 20), any overshoot in the waveform appearing at the collector of transistor 20 immediately following turn-off of the transistor, due to factors such as the transformer leakage inductance, can cause transistor 20 to retrigger by virtue of the overshoot providing a sufficient base drive via the winding 1 3 to turn on the transistor again. The circuit of Fig.

1 includes two diodes 73a, 73b connected in series and in a direction to desensitise the control circuit for transistor 20, thereby preventing spurious turn-on of transistor 20 under these conditions. However, the addition of the diodes 73a, 73b has the effect of desensitising the trigger level at the end of the transformer reset period, and this limits the maximum period of conduction of the transistor 20 (i.e. maximum mark-space ratio). This limit on the maximum mark-space ratio obtainable is undesirable as it prevents the transformer 10 from being utilised to its maximum extent.

The circuit shown in Fig. 2, in accordance with a preferred embodiment of the present invention, overcomes this disadvantage by preventing any overshoot in the switched voltage waveform from affecting the conductive state of transistor 20. This is preferably achieved by effectively disconnecting the feedback winding 1 3 from the base of transistor 20 for a period sufficient to allow for any overshoot. Since the winding then has no effect on the transistor 20 during the occurrence of overshoots, lower control voltages can be used across the winding 12b and this lowers the minimum mark-space ratio available.

Components common to both Figs. 1 and 2 (and these include all components on the "output" side of transformer 10) share the same reference numerals. The circuit of Fig. 2 dispenses with the series-connected diodes 73a, 73b, and instead of resistor 71 connected between the collector of transistor 80 and one junction of capacitor 72 and diode 74, it includes a resistor 71' connected between the winding 1 3 and the other junction of these two components. This other junction is also connected to a clamping circuit 1 50 for effectively disconnecting the feedback winding 1 3 from the base of transistor 20.

The clamping circuit 1 50 includes a transistor 152 connected between terminal 2 and the other junction via a diode 1 54. The base of transistor 1 52 is connected to the winding 1 3 via a timing circuit consisting of resistors 155, 156, 157, capacitor 158, and diodes 159, 160 connected as shown.

In operation, the improved circuit of Fig. 2 prevents the overshoot from affecting.turn-on of transistor 20 by clamping winding 1 3 to approximately zero volts (i.e. the voltage of terminal 2). During the conduction period of transistor 20, capacitor 1 58 charges from the feedback signal in winding 1 3 via resistor 1 55. As soon as transistor 20 turns off in response to transistor 80 being turned on, the charge on capacitor 1 58 turns transistor 1 52 on (the collector voltage having been reduced effectively to bias the transistor on) until the capacitor 1 58 is discharged.The effect of transistor 1 52 turning on is to clamp the winding 1 3 to approximately the potential of terminal 2 and thereby prevent any overshoot voltage being transmitted via this winding to the base of transistor 20. The period during which the winding 1 3 is clamped in this manner can be made sufficiently long to exceed the overshoot period by suitable choice of the capacitor 1 58 and resistors 156, 1 57.

As a result of this effect, the base drive circuit may be made more sensitive which enables the transistor 20 to be turned on earlier after reset of the transformer 10. A better mark-space ratio can therefore be achieved thus providing more efficient utilisation of the transformer. Since the operating range of mark-space ratios available affects not only the control range of the circuit, but also, as a result of suitable choice of transformer turns ratio, the input current in the switching transistor 20, losses in the circuit can readily be minimised by using this improved circuit. Furthermore, whereas in the circuit of Fig. 1, the values of the inductance of winding 11 and the capacitance of capacitor 26 determined a delay period between reset of transformer 10 and turn-on of transistor 20 (by defining a gradient to the switching waveform between the non-conductive and conductive portions), this delay is avoided in the circuit of Fig. 2, since base drive to transistor 20 is provided at the correct time (i.e. just after core reset) despite the switching waveform masking the actual instant when reset occurs. It is thus no longer necessary to monitor closely the variation in the values of inductance of winding 11 and capacitance of capacitor 26 in order to achieve consistent performance.

Claims (8)

1. An inverter comprising a semiconductor switch oscillator including a semiconductor switch having a switched current path from a direct current power source, the state of conduction of the semiconductor switch being responsive to a switching signal at a control terminal thereof, a coupling transformer arranged to provide oscillation maintaining feedback from a first winding thereof disposed in the switched current path of the semiconductor switch to a second winding thereof arranged to provide said switching signal wherein at the end of each conductive period of the semiconductor switch an overswing voltage higher than that of the power source appears at the first winding of the coupling transformer, a voltage limiting circuit arranged effectively to limit the overswing voltage appearing at the first winding of the coupling transformer to a determined value in such a manner as to maintain the semiconductor switch non-conductive within each operating cycle of the oscillations until the coupling transformer has reset, and an inhibiting means responsive to the switching signal provided by the second winding to inhibit the semiconductor switch from being rendered conductive for a preset period after termination of conduction of the semiconductor switch, thereby to avoid spurious switching of the semiconductor switch during the preset period and thus allow an increased control range of mark-to-space ratio to be achieved.

2. An inverter according to claim 1, wherein the inhibiting means comprises a clamping circuit connected to the control terminal of the semiconductor switch and arranged to clamp the control terminal for the preset period in response to the switching signal from the second winding.

3. An inverter according to claim 1 or 2, wherein the inhibiting means includes a capacitor arranged to be charged from one polarity of switching signal provided by the second winding during the conductive period of the semiconductor switch, and an inhibit switch responsive to charge on the capacitor to provide an inhibit signal for the preset period during the non-conductive period of the semiconductor switch, the preset period being terminated when the capacitor has discharged.

4. An inverter according to claim 1, 2 or 3, wherein a resetting circuit is provided to reset the semiconductor switch so as to end its conductive period prior to saturation of the coupling transformer.

5. An inverter according to claim 4, wherein the resetting circuit includes a capacitance, means for providing an initial state of charge on the capacitance within each operating cycle, the initial state of charge being dependent on the overswing voltage limit set by the voltage limiting circuit, and means for charging the capacitance from its initial state of charge from the second winding of the coupling transformer during the conductive period of the semiconductor switch, reset of the semiconductor switch being provided when the capacitance reaches a predetermined state of charge.

6. An inverter according to claim 5, wherein the means for providing an initial state of charge on the capacitance comprises a diode connected to charge the capacitance from the second winding during the nonconductive period of the semiconductor switch.

7. An inverter according to claim 4, 5 or 6 wherein the resetting circuit is connected to the second winding of the coupling transformer to clamp the second winding in one polarity and the inhibiting means is connected to the second winding for clamping in the other polarity.

8. An inverter substantially as herein described with reference to and as illustrated in Fig. 2 of the accompanying drawings.