GB2120429A - Computer system with bus cycle sharing - Google Patents

Abstract

An interactive computer terminal system includes a CPU 4A, a direct memory access (DMA) controller, a RAM 8A, terminal display units 16-1A to 16-32A and various other units all coupled to a system bus 2A. The CPU 4A includes bus arbitration logic which assigns time slots on the system bus 2A in accordance with predetermined priority rules. To achieve maximum bus usage, a unit having a short bus cycle can utilize the bus during a portion of a longer bus cycle, being utilized by another unit, when that other unit is not transferring information over the bus. For example, the processor bus cycle equals two memory cycles, and the processor always accesses the memory during the second half of the processor cycle. Hence another cycle, e.g. a chip refresh cycle, can be activated concurrently with the first half of the processor cycle. <IMAGE>

Description

SPECIFICATION Computer system with bus cycle sharing The invention relates generally to an interactive terminal computer system having a system bus for communicating between elements of the computer system, and more particularly to an apparatus for permitting the maximum number of substantially concurrent bus cycles without interference with each other.

Most computer systems include one or more terminal systems as an element of the computer system with each terminal system having a number of subsystems each coupled to a central processor unit (CPU) which includes a microprocessor, and to other peripheral devices, such as random access memory (RAM), read only memory (ROM), device controllers, etc. Each terminal system with its subsystems may at various times be required to perform various operations, such as screen refresh of the cathode ray tube (CRT) of the terminal system, access main memory directly, or perform chip refresh for main memory. To perform these operations communication must be established over the system bus with an element of the computer system. This is generally accomplished by allocating one or more time cycles to the system bus for communicating with one or more elements.Many times requests for access to the system bus come simultaneously and require arbitration to determine which element would receive a cycle on the bus.

Various prior art techniques for performing this are known. However, the prior art devices assign exclusive priority of the bus during a given time cycle. This excludes maximum utilization of the bus during a given time in arbitrating priorities.

What is needed is an improved priority resolver for access to a bus with improved utilization of the bus.

Accordingly the present invention provides an interactive computer terminal system having a plurality of subsystems communicating with each other by time-sharing of a common bus, each subsystem requesting and being allotted on a priority basis a predetermined amount of time to use the bus (bus cycle), the bus cycles being of different durations, and including apparatus for permitting concurrent execution of two different bus cycles by two different subsystems on said bus comprising: (a) means for allotting a bus cycle 1; (b) means for allotting a bus cycle 2 which is longer than bus cycle 1; and (c) means for initiating the bus cycle 1 after the commencement of the bus cycle 2 but prior to termination of the bus cycle 2.

A system embodying the invention will now be described, by way of example, with reference to the drawings, in which: Figures 1A--l C are block diagrams of the system; Figures 2 and 3 are detailed logic circuits of the bus arbitration logic; Figure 3A is a timing diagram which shows the concurrency of a CPU cycle and a chip refresh cycle on the system bus; and Figures 4 and 5 are truth tables for the bus decoder and refresh decoder.

Introductory summary The present system provides logic circuits for assigning more than one cycle for concurrent execution on a bus.

An interactive terminal includes a central processor unit (CPU), a direct memory access (DMA) controller, a random access memory (RAM), a terminal display unit, a keyboard and a number of other subsystems, such as screen refresh and keyboard controller. The CPU further includes bus arbitration logic which receives requests from the computer system elements and assigns time slots for use of the system bus in accordance with predetermined priorities.

To achieve concurrency of bus cycles one unit having a shorter bus cycle than another utilizes the bus during a portion of the longer cycle when no information is being transferred over the bus.

Hence the unit with the shorter bus cycle does not have to wait until the longer bus cycle terminates.

For example, one processor cycle in the system takes two memory cycles-memory cycle 1 and memory cycle 2. However the processor always accesses memory during memory cycle 2, this being the time slot when the processor utilizes the bus to transfer information. During memory cycle 1 the processor cycle still has access to the bus but does not utilize it. Accordingly still another cycle, chip refresh cycle, is activated concurrently with the processor cycle for accessing memory during memory cycle 1.

Detailed description Figure 1 A shows a typical multi-application interactive terminal system 1 A. Operators seated at work stations may input information into the system via keyboards and receive requested information from the system via cathode ray tube (CRT) displays. A work station includes a keyboard and a display, and a printer if required by the application. The system of Figure 1 A has 32 work stations 16-1 A to 1 6-32A. (Note that a printer 101 A is included in the work station 16--1A.) Four work stations are coupled to device controllers 14-1 A to 14~4A for a total of 16 work stations, and the 16 work stations are coupled to a high speed link controller (HSLC) 1 2A.The HSLC 1 2A eases the connection of work stations by "dropping" them from a cable 12-iA.

A floppy disk 18 stores data pertinent to the application for which system 1 is used. As an example, when system 1 is used in a financial application, the floppy disk 18 may store information about customer accounts and recent transactions prior to transmission to the host.

Floppy disk 18 is coupled to disk controller 145.

A host computer 20A may couple system 1 A to a communication network for enabling communication with other terminal systems or other host computers in the network. Host computer 20A is coupled to a device controller 146A.

Device controllers 14-1 A to 1 4-6A and HSLC 12A are coupled in common to a system bus 2A, as are a central processor (CPU) 4A, a random access memory (RAM) 8A, and a read only memory (ROM) 1 OA. RAM 8A may store the operating system software, as well as other information during program execution. ROM 1 0A may store diagnostic programs for debugging system 1 A, as well as programs for initializing system 1 A during the "power-on" sequence.

CPU 4A controls the operation by generating the system bus 2A timing cycles. The CPU 4A generates bus 2A cycle priorities. The RAM 8A chip refresh cycle has the highest priority. Next in priority is the bus 2A cycle, called a DMA cycle, for transferring information between RAM 8A, ROM 1 OA or between device controllers 14-1 A to 1 4-6A or HSLC 12A. Following in priority is a screen refresh cycle for the CRT's displays 1 D to 16D. The CPU 4A has the lowest bus 2A cycle priority. The CPU 4A is also responsive to instructions received from RAM 8A or ROM 1 OA for typically controlling the system 1 A operation, including branching to error routines, processing interrupts and performing diagnostic routines, as well as application programs.

Included in device controllers 14-1 A to 144A are screen refresh controllers 14~1 S to 144S; whereas included in device controllers 145A to 1 4-6A are DMA controllers 14--5D to 1 4-6D. Moreover, the system bus 2A is comprised of an address bus having address bits A0-A1 9 and a data bus having data bits DO D7.

Figure 1 B shows the more essential elements of the system. The address bus 2A and data bus 2D correspond to the system bus 2A of Figure 1A.

The CPU 4B corresponds to the CPU 4A of Figure 1 A, the DMA controller 14--5D corresponds to one of the DMA controllers 14-SD, 1 4-6D of Figure 1A; ROM and RAM memory 10B corresponds to ROM and RAM memories 1 OA, 8A of Figure 1 A; screen refresh and keyboard controller 14-1 S corresponds to one of the device controllers 14-1 A through 1 4-4A and 14-iS through 14--4S of Figure 1 A; while display 1 D and keyboard 1 K corresponds to one work station on Figure 1 A. The CPU 4B includes the bus arbitration logic 11 B, which is more fully described infra utilizing Figures 2 and 3.

The basic concept of the system is to permit the maximum number of substantially concurrent cycles without interference with each other. Prior art systems utilize exclusive cycles utilizing a priority scheme. Whereas the present system also utilizes a priority scheme to enable a cycle and allocate resources, the various cycles need not be exclusive but can be concurrent once initiated.

The bus cycle of the system are synchronous and require 500 nanoseconds. A clock is set to 250 nanoseconds cycle time. The priorities for allocating cycles are as follows: 1. Chip refresh has the highest priority if a refresh cycle has not occurred within the last 15 nanoseconds, otherwise it has the last priority.

Chip refresh is necessary for such devices as MOS memory which require the maintenance of an electric charge, otherwise they lose information stored therein, 2. The DMA channel is given the highest priority, except for case 1 above. As noted supra, the DMA cycle on the bus 2A is utilized for transferring information between RAM 8A, ROM 1 or, controllers 14-1 A to 1 4#A, and controllers 1 4-5A to 1 4-6A, and HSLC 12A.

3. Screen refresh has the next highest priority.

Screen refresh is necessary to maintain information on the cathode ray tube (CRT) screen, which in Figure 1A and Figure 2A are shown as the display 1 D to 320. There are two formats utilized which are character dependent. One format has 64 characters per line, while the other format has 80 characters per line. For a single format system, the refresh cycles are allocated, two for refresh and one free to the system. For a dual format system--one utilizing the 64 character format and the 80 character format~ three cycles are allocated. First the 64 character format is given 2 cycles and then the 80 character format is given a cycle. This process is repeated until one of the screens is satisfied.The contention for cycles occurs on a random basis since the frequency of the two formats is not a multiple of each other, with the exception of the basic 60 Hertz synchronization.

4. The processor (CPU) is given the lowest priority.

The system, however, is flexible and the priority can be varied. For example, the processor can be assigned a higher priority. The system comprises the logic for arbitrating the DMA (direct memory access) cycle, refresh system A (64 character refresh), refresh system B (80 character refresh), processor cycle, and finally chip refresh.

With respect to refresh A and B, refresh A has first priority over refresh B, but if refresh A has two consecutive cycles, then refresh B can have a cycle after that. As noted earlier, the purpose of the screen refresh is to extract line data out of RAM memory to eventually be utilized to generate a composite video output to the CRT. (The RAM memory, not shown, is in the device controllers 14-1 A to 1 4#A. Each RAM contains the data for its respective displays. For example, displays 1 6-lA to 16 4A receive their data from the RAM in device controller 14-1 A). This is also true for screen refresh controllers 14~1 S to 1 4-48. It should be noted that these controllers 14-1 A to 14--4A may be of the Type A or the Type B, which is merely a convenient designation to indicate that the controllers either controls an 80 character screen, a 64 character screen, or some similar device with different characteristics.

Accordingly the arbitration logic must additionally arbitrate at this level between the Type A and Type B controller. If, for example, screen refresh for Type A controller has had 2 cycles in a row, the next memory cycle is arbitrated among others according to the priority supra-the DMA controller has first priority, screen refresh B has second priority, and CPU had last priority. If none of these devices require a bus cycle, then screen refresh A would continue to utilize the bus cycle if it was necessary.

Referring now to Figure 1 C, the CPU 4A includes a microprocessor 30C which generates 20-bit address signals ADO to AD7 and AS to A19 during address cycle time. The signals ADO to AD7 are operative as bidirectional data signals during data cycle time. Address signals ADO to AD7 and AS to A19 are stored in an address latch unit 36C. This allows the signals ADO to AD7 to transfer data during data cycle time. The address signals AO--A19 from address latch 36C are transferred over address bus 76C to an address buffer 64C for transfer over system bus 2A.

Bidirectional data signals ADO to AD7 appear on data bus 78~1 C and/or data bus 78-2C at data cycle time.

A clock generator 84C generates the basic timing for the system by making clock signals ACK 1 to CK12 available on system bus 2A. A processor clock signal PROC CLK provides the basic timing for the microprocessor 30C and a bus control and arbitration logic 32C. The PROC CLK signal is high between CK3 and CK5 time and between CK9 and CK1 1 time. Clock generator 34C also provides the RAM 8A, refresh timing signal DRAM REF REQ. This results in the bus control and arbitration logic 32C generating the RAM REF signal onto system bus 2A to refresh RAM 8A. Also, a number of miscellaneous timing signals generated from clock signals CK1 to CK 12 are applied to bus control and arbitration logic 32C.

Bus control and arbitration logic 32C receives processor status signals SO, S1 and S2 to indicate the mode of operation such as I/Q read, I/O write, memory read, or memory write. The I/O operations refer to the microprocessor 30C communicating with one of the device controllers 14-iA to 14-6A, or the HSLC 12A, as well as all I/O operations within the CPU 4A. The memory read or memory write operation refers to the transfer of information between the microprocessor 30C and either RAM 8A, ROM 1 OA, RAM 40C or PROM 42C. Signal MR indicates a memory read out from RAM 40C or PROM 42C; and signal MW indicates a memory write; signal IW indicates an I/O write and signal IR indicates an I/O read operation.The processor ready signal PROC RDY indicates that the system bus 2A is busy and the microprocessor 30C should wait for the next non-busy system bus cycle. This will normally happen when the microprocessor 30C initiates a memory read, write or I/O cycle on system bus 2A, since the processor cycle has a two memory cycle duration.

The bus control and arbitration logic responds to a device controller request signal DMA REQ with a device controller acknowledgement signal DMA ACK indicating that the requesting device controllers 14--5A, 14--6A, or the HSLC 12A may communicate with RAM 8A or ROM 1 OA or device controllers 14-1 A to 1 4-4A during a DMA bus 2A cycle. Also, screen refresh signal SCR REF indicates a display 1 D to display 16D refresh cycle and RAM refresh signal RAM REF indicates a RAM 8A refresh cycle.

A device select address decoder 38C generates enable signals S1 to S12 in response to address signals A0 to A19 to enable one of twelve logic elements of CPU 4A. The device select address decoder 38C also generates signals to enable device controllers 14-1 A to 1 4-6A, HSLC 12A and ROM 1 QA. One of the enable signals and the write signal MB or IW applied to a logic element will result in enabling the logic element receiving a data byte via data bus 78-iC or 78-2C signals ADO to AD7. If the read signal RD is applied to the enabled logic element, then the data bus 78-iC or 78 3C signals ADO to AD7 are stored in the enabled logic element.

A timer 46C acts as a watchdog timer, a real time clock and a baud rate generator. A watchdog timer generates a signal WOT whenever an event that should have happened did not happen. A real time clock generates a signal RTC whenever the system desires an operation after a preset time.

Signal BRG is applied to a USART 50C to generate the baud rate. Signal WOT is applied to a non-maskabie interrupt register which generates an NMI signal. The microprocessor is responsive to the NMI signal and branches to a firmware or software routine to recover from the fault that result in the WOT signal. The real time clock signal RTC is applied to interrupt controllers 48C which generates the INT signal which interrupts microprocessor 30C. Microprocessor 30C enables interrupt controllers 48C via device select address decoder 38C and signal S2 to read the data byte onto a data bus 78-1 C to identify the interrupting device to branch to the subroutine that will process that interrupt.

Address signals AD and Al select the mode of operation of the timer, the baud rate generator, watchdog timer or real time clock. Data bus 781 C signals DO to D7 set or read the count in the timer 46C.

The interrupt controller 48C has 16 levels of interrupt-level 1 having the highest priority interrupt and level 16 having the lowest level of interrupt.

The universal synchronous/asynchronous receive transmit controller (USART) 50C is capable of controlling communication lines which are coupled directly to the USART 50C. Signal S3 enables the USART 50C, which transmits data received from data bus 78-i C signals ADO to AD7, and receives data which it transfers to data bus 78-iC, signals ADO to AD7. The baud rate is generated by timer 46C and applied to USART 50C by signal BRG.

A 1 kx9 RAM 40C stores the interrupt vectors.

Four 8 bit bytes are reserved for each of the sixteen interrupt levels to point to the program to process the interrupt. The program may be stored in RAM 40C or in RAM 8C. Address signals AO to A9 address the 1024 byte locations. A PROM 42C optional from 8K to 32K bytes may store the routines to initialize the CPU 4A during the "power-up" operation. This loads RAM 40C, interrupt controllers 48C and timer 46C.

An address buffer 64C buffers the address signals AO to Al 9 for transfer over system bus 2A. The address buffer 64C is deactivated during the DMA system bus 2A cycle when one of the device controllers 14 5A to 1 4-6A or the HSLC 12A is communicating with RAM 8A or ROM 1 OA or device controllers 14-iA to 11 4A since the device controllers 14--5A to 146A or the HSLC 12A is generating the RAM 8A or ROM 1 OA address or device controllers 14-1 A to 14 4A address.

Screen AD MUX 66C is the multiplexer which selects either the address signals AO to Al 0 and Al 2 or refresh address signals RAO to RAil from screen refresh memory (not shown) to generate refresh address signals ADMUX 0 to ADMUX 5 which are used to access and refresh the screen refresh memory. The screen refresh memory refreshes displays 1 D to 16D.

The non-maskable interrupt register generates the NMI signal to interrupt the microprocessor 30C during power-up, the sensing of a parity error signal PERR from parity check 56C in addition to the watchdog timer error described supra.

Switch port 54C contains switches for storing addresses or configuring data during particular applications.

Parity check generator 56C receives data bus signals DO through D7 and DP, and generates a parity or checks for a parity error, and indicates by data signals DO to D2 if the parity error is a CPU 4A error or a DMA error. The parity signals are stored in both RAM 40C and RAM 8a and device controllers 191 1 A to 191 4A.

A cyclic redundancy check 58C is operated with USART 50C to generate during the transmit operation or to verify during the receive operation the cyclic redundancy check character.

An identification ROM 60C stores an identification number to identify the interactive terminals system 1 A. This is particularly needed when system 1 A is part of a large communication system and assures the sending device that the address system 1 A has responded.

A self-test panel 74 contains a test switch, light emitting diodes (LEDS), communication LEDS for the data bus 78-2C via self-test panel logic.

A mini floppy disk 70C is coupled to the data bus 78-2C via a mini floppy disk control 68C to store additional programs or to store a record of all transactions processed by the CPU 4A.

Figure 2 shows the detail logic diagram of screen refresh control which arbitrates between different types of screen refresh system requesting a refresh cycle.

Referring again to Figure 2, a PROM 210 is utilized to decode the priority codes associated with a variety of priority conditions that have to be resolved between Type A screen refresh controller and Type B screen refresh controller, and provide an appropriate output signal REFACKA or REFACKB (depending upon the outcome of the resolution) on output terminals 218 or 218B, respectively. In order to arbitrate these priorities, the decoder receives various input signals indicative of different conditions requiring resolution. For example, refresh request A input in terminal 220 provides a refresh request signal REFREQA to input to terminal ADC of decoder 210 via a flip-flop 225.When the D terminal of flip-flop 225, which is coupled to the REFREQA input in terminal 220, is high, and the C terminal is high, then the Q output terminal, which is coupled to the ADC input terminal of decoder 210, is also high. Conversely when the D input terminal of flip-flop 225 is low, the Q output terminal is also low, accordingly when pin terminal 220 is high, which is indicative of a Type A screen refresh cycle from controller 14-1 S, the ADC input terminal of decoder 210 would be high. On the other hand, under these conditions the Q terminal of flip-flop 225 would be low and the output signal would be applied to one input terminal of AND gate 214. The other input terminal of AND gate 214 receives its signal from the refresh B (REFB) flip-flop 212.With one input terminal of AND gate 214 low it cannot be enabled and accordingly screen controller B cannot perform two successive refresh cycles.

When a Type B screen refresh controller from one of screen refresh controllers 14~1 S to 144S, requests a refresh cycle, then a high signal REFREQB is applied to input to pin terminal 221.

This high signal is then applied to a SN7404 inverter 223, where it is inverted and applied to one input terminal of positive NOR gate 224. (The truth table for this type gate is Y=A, where A and B are input signals and Y is an output signal).

Accordingly if both input signals on NOR gate 224 are low, the output will be high. Accordingly a high signal will be applied to the D input terminal of flip-flop 226. Since the truth table of flip-flop 226 is the same as flip-flop 225 discussed supra, the Q output terminal of flip-flop 226 will be high, and accordingly a high signal will be applied to the ADO input terminal of decoder 210.

In arbitrating between a refresh cycle between Type A and Type B screen controllers, the decoder 210 also takes into consideration the status of the mode of bus operation; i.e., for example, is there a read/write cycle from the processor to the memory, and is that a read/write cycle to the screen memory. This is done by applying the status signals SO, S1 and S2, from the microprocessor 4A to input terminals A, B, C of a decoder 201. These status signals are then decoded on terminals Y5 and Y6 of decoder 201 and applied to the input terminals of a positive AND gate 203. The output of AND gate 203 is then applied as one input terminal of an SN74LS02 type positive NOR gate 205. The output from positive NOR gate 205 is applied as one input of another positive NOR gate 206.

Finally the output of NOR gate 206 is applied to the ADB input terminal of decoder 210. The determination as to whether or not the address of the next memory cycle is actually a screen address or an address of any screen area, is accomplished via a triple-input NAND gate 208 and a 4-input type positive NAND gate 207, which together decode address bus bits 1 6-1 9.

The decoded signal from NAND gate 207 is then applied to the other input terminal of NOR gate 205. Terminals Y5 and Y6 when true signify that the processor wants to do a memory read or write cycle. When ANDed with the address pointing to screen memory (output of 207) indicates that the processor wants to read or write to screen memory. This is then inputted to the decoder 210 so it can determine if refresh (A or B) or the processor can have the next cycle.

A further arbitration by the arbitration logic is to determine whether the DMA controller wants a screen access. Accordingly a DMA signal is provided by the DMA controller and applied to one input terminal of positive NOR gate 209. The other input terminal of NOR gate 209 is the enable not En on terminal 219. The output signal from NOR gate 209 is then applied to the ADA input terminal of decoder 210.

The input signals on decoder 210 are decoded so that between two requests from a Type A screen refresh controller and Type B, Type A will win the bus cycle when there is no read/write cycle to-or-from main memory or to-or-from screen memory and additionally there is no processor or DMA controller cycle. When, for example, the Type A screen refresh controller wins the bus cycle, a high signal will result on the D01 output terminal of decoder 210, which in turn is applied to the D input terminal of a flip-flop 211. Since the enable not En signal on input line 260 is always high, the Q terminal of flip-flop 211 will latch high on the next clock cycle and will provide a refresh acknowledge RENACKA signal on terminal 218 via the SN74S241 type buffer gate 216.Additionally the inverter 231 will be true, since under these conditions the u terminal of flip-flop 211 will be low and the Q terminal of flip-flop 212 will be high providing a low output signal from positive NAND gate 230 by similar analysis, when the D02 output terminal of decoder 210 is high, the flip-flop 212 will be true indicating that refresh B cycle has the bus.

Referring now to Figure 3 the bus arbitration logic will be further described. On Figure 2 the logic which arbitrates between a Type A or Type B screen refresh control without interferring with the DMA processor cycle on a bus was described.

Figure 3 shows the total arbitration process between direct memory access controllers, processor and the winner of the chip refresh cycle.

Referring now to Figure 3, a DMA read request (DMARDREQ) and DMA write request (DMAWRREQ) is applied respectively to input terminals 350 and 351. These signals are ORed together at a positive AND gate 305 and then applied to the ADB input terminal of a bus decoder 307. A chip refresh request signal CHPREFREQF from the Q output terminal of a flipflop 301 is also applied to the ADA input terminal of bus decoder 307. Still another input to the input terminal ADC of decoder 307 is the chip refresh enable (CHPREFENB) signal from the Q output terminal of flip-flop 302. Yet another input to the ADB input terminal of decoder 307 is applied from the Q output terminal of a flip-flop 303. Final input signal on terminal ADE of decoder 307 is the DMA screen cycle (DMASCR) from line 352.Accordingly signals are applied to the input terminals of bus decoder 307 representing DMA read requests, a DMA write request, a chip refresh request, a chip refresh enable request and a DMA screen refresh. (The resolution of such requests are shown in the truth table of Figure 4 to be described infra). It should be noted that the function of the chip refresh request flip-flop 301 is to request a dynamic refresh cycle. The function of chip refresh enable flip-flop 302 is to permit the chip refresh cycle during their period that the Q terminal is high. The function of the chip refresh enable flip-flop 302 is to prevent another chip refresh cycle within a 15 during the period that the Q terminal is high. The function of chip refresh sync flip-flop 303 is to allow the chip refresh to have the first half of a processor cycle when the processor doesn't want the bus 2A.Therefore chip refresh does not interfere with the processor cycle. The function of the positive NOR gate 308 is to arbitrate the contention for a bus cycle between the processor and the DMA, or between the processor and the screen refresh cycle. When gate 308 is true, the flip-flop 311 is true, and the processor obtains one cycle. On the other hand, if the chip refresh cycle is true, then the output D02 of decoder 307 is true, and the chip refresh cycle flip-flop 312 is true, and a chip refresh cycle is performed. If, however, DMA is to have a cycle, decoder 307 decodes the input so that the D03 output terminal of decoder 307 is true; this signal is then applied as one input of a positive AND gate 310 which is arbitrated with the refresh decode (REFDEC) signal on line 353. When AND gate 310 is true, the flip-flop 313 is true, and permits the occurrence of a DMA cycle. During this cycle, synchronous 4-bit counters 317 and 319, respectively, count approximately to 15 microseconds, after which time chip refresh is eligible to be considered as top priority once again.

Referring now to Figure 4, there is shown the truth table for bus decoder 307. The chart is substantially self-explanatory. The first five columns represent the signals on the input terminals of refresh decoder 307; the last five columns represent the signals on the output terminals of bus decoder 307. It should be noted that the chip refresh request signal ADA is represented in the first column and is true when the terminal is high; the DMA request signal ADB is represented in the second column and is true when L is low, and so on with the remainder of input/output terminals of Figure 4.

Figure 5 is the truth table of the refresh decoder 210 which is read substantially in the same manner as Figure 4. In order to further illustrate the use of these tables, assume that chip refresh request controller requires a cycle whereas the other devices do not require a bus cycle. This is shown on row 25. Referring to row 25, it will be seen that the chip refresh request ADA terminal of bus decoder 307 is high; additionally the DMA request controller terminal ADB is high indicating that this is not true; the remainder of the input terminals ADC, ADD and ADE are all low indicating that they are not true.

This combination of signals is decoded at the output so that the D01 and D03 output terminals of bus decoder 307 are high. These signals then are further arbitrated through subsequent logic hardware.

Referring now to Figures 3 and 3A, chip refresh will be additionally described with the emphasis on the feature of performing dynamic memory refresh (i.e., chip refresh) during a chip refresh cycle which is concurrent with the CPU cycle. The CPU cycle N (B) (shown on Figure 3A) is comprised of two memory cycles (C) M1 and M2.

During the first half of the cycle M1, the CPU memory setsup new addresses in a CPU memory address register (not shown). During this half of the CPU cycle, which lasts for 500 nanoseconds, no information transfers take place and accordingly the bus is not utilized by the CPU cycle N which lasts for 1000 nanoseconds.

However, the latter part of the CPU cycle N which also lasts for 500 nanoseconds does utilize the bus for information transfers. Further the dynamic memory refresh cycle (D) is also a 500 nanosecond cycle, DM 1, in which time the bus would be utilized to refresh the RAM memory. In order to avoid interference between the CPU (B) and the dynamic memory refresh cycle (D), prior art systems require two different cycles CPU cycle of 1000 nanoseconds and a DIM 1 cycle of 500 nanoseconds. The present system assures that the dynamic memory chip refresh cycle DM 1 always occurs during the first half of the CPU cycle (B). Accordingly both the CPU cycle and the dynamic memory refresh cycle can be performed concurrently thus saving approximately 500 nanoseconds in performing these two operations.

Referring once again to Figure 3A, it will be seen that a CPU ALE (address latch enable) signal strobe occurs at clock times 5 to 9. The CPU ALE strobe (A) strobes the CPU address bus 76C and status signals SO, S1 and S2 into the address latch 36C of Figure 2. The system takes advantage of this by having the dynamic memory refresh cycle DM 1 also begin concurrently with the beginning of the CPU cycle N. The dynamic memory refresh cycle will terminate after 500 nanoseconds after utilizing the system bus.

However, during this part of the CPU cycle the CPU does not utilize the system bus, but merely provides address information to the CPU memory address register MAR (not shown). During the last half of the CPU cycle N the system bus is utilized by the CPU's memory cycle M2; however, by this time the dynamic memory refresh cycle has terminated and leaves the bus free.

Referring now to Figure 3, the logic for accomplishing the chip refresh operation during a CPU memory cycle will be described. An ALE signal is applied to one input terminal of AND gate 327, whereas the output from the 0 terminal of the processor cycle flip-flop 311 is applied to the other input terminal on positive NOR gate 327. Positive NOR gate 327 is true when both inputs are true, and will provide a chip refresh synch (CHPREFSYN) signal to the D input terminal of chip refresh synch CHPREFSYN flop 303. The Q output terminal of flip-flop 303 is applied to the ADD input terminal of bus decoder 307, which as seen previously, arbitrates between the various requests.

It can be seen, therefore, that if the ALE signal is true at the input of gate 327 and also the processor cycle is true at the other input of AND gate 327, flip-flop 303 will latch and become true at this time. This true signal will be arbitrated at bus decoder 307 and the chip refresh cycle will be awarded according to other inputs of the bus decoder. If a chip refresh cycle is awarded, it can be seen that chip refresh cycle flop 312 will be true and provide a RAM refresh signal on RAMRFH terminal 323. This will occur only on the first half of the processor's cycle because positive NOR gate 327 allows the chip refresh cycle to proceed only if there is an ALE signal present.

Since the processor cycle always occurs at the rising edge of the ALE signal, it is assured that the chip refresh cycle will occur in the first 500 nanoseconds of the total processor cycle which lasts for 1000 nanoseconds.

Claims (4)

Claims

1. An interactive computer terminal system having a plurality of subsystems communicating with each other by time-sharing of a common bus, each subsystem requesting and being allotted on a priority basis a predetermined amount of time to use the bus (bus cycle), the bus cycles being of different duration, and including apparatus for permitting concurrent execution of two different bus cycles by two different subsystems on said bus comprising: (a) means for allotting a bus cycle 1; (b) means for allotting a bus cycle 2 which is longer than bus cycle 1; and (c) means for initiating the bus cycle 1 after the commencement of the bus cycle 2 but prior to termination of the bus cycle 2.

2. A system according to Claim 1, wherein the bus cycle 2 is twice as long as the bus cycle 1 and wherein the bus cycle 1 is commenced during the last half of the bus cycle.

3. A system according to Claim 2, wherein the bus cycle 2 has access to the bus system during its entire duration but utilizes the bus only during the first half of the bus cycle 2.

4. A system according to Claim 3, wherein the subsystems include a CPU, a main memory, and a memory refresh controller and wherein the CPU has a bus cycle twice as long as the bus cycle of the memory refresh controller, the main memory also having a bus cycle equal to that of the memory refresh controller, and including means for permitting the memory refresh controller to access the main memory via the bus during the second half of the CPU cycle.