GB2199171A - Display - Google Patents

Abstract

In a method for the mains-synchronised, multiplex control of a display, the display should be as bright as possible. A counter is brought into circuit in each mains cycle at the end of the last display place starting signal (e4). When the counter runs through more than a specific number of counting steps up to the end of the mains cycle, the starting signals (e1'-e4') in the following cycle are lengthened. If it runs through less than the specific number, they are shortened. <IMAGE>

Description

Method for controlling a display and a display The invention relates to a method for controlling a display with several multiplexed display places, for which, in each cycle of the mains voltage, starting signals for the individual display places are produced one after tne other and the first starting signal is synchronised respectively with the beginning of each cycle of the mains voltage.

The invention also relates to a display for carrying out the method.

In mains-synchronised time switches for example1 their display is operated according to a method of this type.

Due to the synchronisation of the respective first starting signal with the zero passage of the ma@@@ alternating volt- age, i.e. the beginning of each cycle of the mains voltage, optical flickering cf the display can be eliminated.Indeed this produces an undesirably dark splay. This can be attributed to the fact that in each cycle of the mains voltage, after the end of the respective last starting signal and the end of this cycle, a comparatively long delay or break time must be provided. The break time cannot be minimised by corresponding fixing of the durations of the starting signals, since the durations cf the starting signals fluctuate on account of tolerances which cannct be avoided economically.

In the bbliography "Halbleiterschaltungstechnik" (semi-conductor circuit techniques), U. Tietze, CH, Schenk, fifty edition, 1980, page 629, a display with several multi- plexed display places is described. However, the said problem is not solved therein.

In a method of the afore-mentioned type, it is theobject of the invention to achieve the brightest possible display by compensating for tolerances of the duration of the starting signals caused by components. It is also the object of the invention to propose a corresponding display.

According to the invention the above-mentioned object is achieved in a method o; the afore-mentioned type due to the fact that a counter is put into circuit at the end of the last starting signal in each cycle of the mains voltage, that then, when the counter runs through more than a specific number of counting steps up to the end of this cycle, the starting signals in the following cycle are lengthenec ano that then, when the counter runs through less than tne specific number of counting steps up to ne end of this cycle, the starting signals in the following cycle are shortened.

It is thus ensured that in the cycles of the mains voltage the time during which no starting signal is available, is short. The display seems accordingly right. Existing tolerances of the starting signals at- ccrpensatec for so that the sum of the durations of the starting signals is the least possible amount smaller than the cycle duration of the mains voltage.

In a preferred embodiment of the invention, the counter is re-set to its initial counting state by the zero passage of the mains voltage following the last starting signal of a mains cycle.In the case of a mains failure, the counter then passes to its final counting state. When this is achieved, a mains failure signal is produced. Consequently, the counter at the same time provides a Dower failure fuse cut-out. Units wit a higher power consumption can be switched off by the power failure signal and a buffer fcr the electronics can be put into circuit.

In order to prevent that on the basis of delay time fluctuations, a display cycle, namely the sum of the durations of the starting signals plus the necessary break times, lasts longer than one mains cycle, due to which the regulation taking place due to the counter would be faulty, after a plurality of cycles of the alternating mains voltage, for example after each minute, the durations of the starting signals are periodically set to their minimum value.

A display according to the invention is described in Claim 5.

Further advantageous embodiments of the invention will become apparent from the following description of one embodiment. In the drawings: Figure 1 is a block circuit diagram of a display in mainssynchronised time switch and Figure 2 shows voltage diagrams.

! feed voltage with mains frequency reduc-- iti respect to the mains voltage is supplied on a supply line A mains-synchronised time switch 2 is connected te the supply line 1. This time switch 2 switches a unit which is not shown in detail, by way of an output 3.

By way of a multiplexor 4, the time switch 2 controls a display unit 5, which in this example comprises four display places 6, 7, 8, 9. The numerals "0 to t can be made to appear at each display place (6 to 9 by way of the multiplexor 4. The display unit 5 comprises a heating system 10, which is connected to the supply line On the one hand the multiplexor 4 produces starting signals (el, e2, e3, e4) (see Figure 2b) for the base electrodes (6' to 9') of the four display places (6 to 9) (see Figure 1). On the other hand it produces switching pulses (not shown in detail) for the digit electrodes of the four display places (6 to 9). A control circuit 11 is provided for adjusting the durations of the starting signals (el to e4).

Also connected to the supply line 1 is a counter 12, in the case of this example a down counter. A comparator 13 is connected between the counter 12 and the control circuit 11.

The counter 12 is also connected to the time switch 2 and the multiplexor 4.

A time-lag relay 14 is connected to the control circuit 11, which relay sets the control circuit 11 after a certain time, for example one minute, periodically so that starting signals (el to e4) with the minimum duration appear.

Figure 2a illustrates one cycle (T) of the mains alternating voltage. figure 2b shows the four starting signals (el to e4) and a delay time (W) after the last starting signal (e4) during the cycle (T). Figure 2c shows ccuntir.g pulses of the coulter 2 luring the delay time tow;.

In the example illustrated, the delay time (W) is long and it is shortened with the circuit described.

The method of operation is as follows: At the time of the zero passage of the mains voltage, the counter 12 is re-set to its initial counting state, for example "15" and the first starting signal (el) begins.

This is followed by the other starting signals (e2, e3, e4).

The counter 12 is actuated by the end of the last starting signal (e4). It now counts down beginning from "15" (see Figure 2c) until the next zero passage of the mains voltage.

The comparator 13 is adjusted so that when the counting state at the time of the zero passage is less than "14" (see Figure 2c), the control circuit 11 is activated so that in the following mains cycle (T), the starting signals (el' to e4') are extended in like manner so that accordingly the delay time (W) is shortened. With the zero passage of the mains cycle (T), the counter 12 is re-set to its initial counting state and the first starting signal (el') of the following mains cycle begins.

If the delay time (W) is so short that the counter 12 only counts up to the limit value set at the comparator 13, in this example "4", then the durations of the starting signals (e1 to e4) are not changed.

If, during the delay time (W), the counter 12 does not reach the said limit value "14" before it is re-set at the end of the mains cycle (T), then the durations of the starting signals (el to e4) are shortened by way of the control circuit 11.

Changes to the durations of the starting signals (el to e4) take place step-wise in successive mains cycies until the counter 12 is at the limit value, in this example "14".

Since It cannot be precluded that as a result of delay time fluctuations, a cycle of the starting signals may last longer than the mains cycle (T), the durations of the starting signals are set to their minimum value by the time-lag relay 14 for example each minute, in which case a maximum delay time results and then it is lengthened in the manner described so that a minimum delay time results.

If the power supply fails, then after the delay time (W', the counter 12 is no longer re-set to its initial counting state, but runs up to a final counting state. If this is reached, then a buffer circuit can be brought into operation by this mains failure signal and the display unit 5 as well as other consumers are switched off.

The afore-described display is not restricted to use in time switches. It can also be used in other cases.

Claims (8)

Claims

1. Method for controlling a display with several multiplexed display places, starting signals for the individual display places being produced in succession in each cycle of the mains voltage and the respective first starting signal being synchronised with the beginning of each cycle of the mains voltage, characterised in that at the end of the last starting signal (e4) in each cycle (T) of the mains voltage, a counter (12) is put into circuit, that then, when the counter (12) runs through more than a specific number of counting steps up to the end of this cycle (T), the starting signals (el to e4) in the following cycle are lengthened and tat then, when the counter (12) runs through less than the specific number of counting steps up to the end of this cycle (T), the starting signals (el to e4) in the following cycle are shortened.

2. Method according te Claim 1, characterised in that the counter (12) is reset to its initial counting state by the zero passage or the stains voltage following the last starter sicnal (e4! of a mains cycle (T).

3. Method according to Claim 2, characterised in that a mainC failure signal is initiated by the counter (12), when St reaches its final countIng state.

4. Method according to one of the preceding Claims, characterised in that after a plurality of cycles of the mains voltage, the durations of the starting signals (el te e4) are periodically set to their minimum value.

z. Display, in particular in a mains-synchronised time switch, with several display places, which are controlled by starti slg..âls in the multiplex method, characterised in that a counter (12) is provided, which is put into circuit by the end of the last starting signal (e4) of a cycle (T) of the mains voltage and which is reset by the following zero passage of the mains voltage and that the counter (12) is followed by a comparator (13), which controls the durations of the starting signals (e1 to e4) depending on the counting state reached up to the following zero passage.

6. Display according to Claim 5, characterised in that the comparator (13) is set to a limit counting state, from which it lengthens or shortens the durations of the starting signals (el to e4).

7. Method for controlling a display with several multiplexed display places, substantially as hereinbefore described with reference to the accompanying drawings.

8. A display substantially as hereinbefore described with reference to the accompanying drawings.