GB2192319A - Logic circuits - Google Patents

Abstract

An integrated logic circuit comprising bipolar transistors (16, 18) and junction field-effect transistors (12, 14). The junction field-effect transistors (12, 14) are arranged in the circuit to serve as switching elements, the gates being connected to the bases of the respective bipolar transistors (16, 18). The channels of the junction field-effect transistors are formed in the integrated structure design as ''pinch'' resistors defined by a P or N doped region of the same or similar type to that used to define the sub-emitter base resistance in the bipolar transistors (16, 18).

Description

SPECIFICATION Logic circuits The present invention relates to integrated logic eircEsíts.

integrated circuittechnology employs a variety of veIi'known processing techniques. The techniques afeu-6aaíly based on either bipolar or CMOS proces sing te cnologyand strive to provide an optimum balance between conflicting operational design re quiremenfsforthe chips. The conflicting requirements usually include maximising operational speed and packing density ofthe logic gates whilst also minimising the power required for chip operation.

An objective ofthe present invention is to provide an integrated logic circuit structure which lends itseif to bipolar processing technology and which provides chips having fast operational speed, high packing density of logic gates and low power operation.

According to the present invention there is provided an integrated logic circuit comprising bipolartransistors and junction field-effecttransistors; wherein the junction field-effecttransistors are arranged in the circuit to serve as switching elements, the gates of the junctionfield-effecttransistors being connected to the bases ofthe bipolar transistors.

In a preferred embodiment the junction field-effect transistors each have a P-channel and the bipolar transistors are each ofthe NPN type. In another embodimentthe junction field-effecttransistors each have an N-channel and the bipolartransistors are each ofthe PNPtype.

In one embodimentthere is provided an integrated logic array comprising a plurality of logic circuits each ofwhich comprises bipolartransistors an djunction field-effect transistors,wherein the junction fieldeffect trarlsistors are arranged in series relationship to one another and the bipolartransistors are arranged in parallel relationship to one another,the gate of each ju nction field-effecttransistorbeing connected to the base of a respective one ofthe bipolartransistors.

In afurtherembodimentthere is provided an integrated logic array comprising a plurality of logic circuits each of which comprises bipolartransistors and junction fielci-effecttransistors, wherein the junction field-effecttransistorsare arranged in parallel relationship to one another and the bipolartransistors are arranged.inseriesrelationshiptooneanother,the gate of each,jpnction field-effecttransistor being connectedito tlhe base of a respective one of the bipolartransistors.

In a preferred embodimentthe channnel of each of the junction field-effecttransistors is formed in the integnatedstructure design as a "pinch" resistor.

In one embodimentthe "pinch" resistor defining tSEchannei is in the form of a P or N doped region of tire sameorsimilartype to that used to define the sub-emitter base resistance in the integrated NPN or PNP bipolar transistors.

Advantageously the "emitter" region is extended to separatetwo "base" regions normally defined in a bipolartransistorwherebythe "base" regions be come the source and drain, and the "emitter" the gate ofthejunctionfield-effecttransistor.

In one embodiment the channel of each of the junction field-effect transistors in the integrated chip structure has a thickness substantially within the range of 0.5 microns to 0.05 microns.

In a preferred embodiment the thickness of the channel of the junction field-effecttransistor is 0.2 microns or less.

The present invention also provides a method of manufacturing an integrated logic device comprising the use of bipolar processing steps to form a bipolar transistor and a junction field-effect transistor within the integrated structure of the device, the channel of the junction field-effect transistor having a thickness less than 0.5 microns and being formed to function when in operation in a mannersimilartothatof a "pinch" resistor.

The present invention will be described further, by way of example, with reference to the accompanying drawings in which: Figure lisa circuit diagram of an integrated two input NOR gate according to an embodimentofthe present invention; Figure 2 is a circuit diagram of an integrated two input NAND gate according to an embodiment ofthe present invention; Figure 3 is a cross sectional view through an integrated NPNtransistor; Figure 4 is a cross sectional view through a P-channnel junction field-effect transistor according to an embodiment of the present invention; Figure 5 is a cross sectional view through part of an integrated gate device ofthe type illustrated in Figure 1;; Figure 6A is a layout, in plan view, of part ofan integrated gate device of Figure 5; Figure 6B is a circuit diagram illustrating the interconnections corresponding to the layout of Fi- gure 6A; Figure 7 is a circuit diagram of a static memory cell employing JFET-Bipolar logic configurations accord ing to an embodiment ofthe present invention; and Figure 8 is a diagram of CMOS-Like random access memory cell employing JFET-Bipolar logicconfigura- tions according to an embodimentofthe present invention.

Referring to the circuit diagram of Figure 1 there is illustrated a two input NOR gate comprising two NPN transistors 16 and 18, and two P-channel junction field-effect transistors (J-FET) 12 and 14. The gate of the J-FET 12 is connected to the base of the NPN transistor 16 and the gate of the J-FET 14 is connected to the base of the NPN transistor 18. The P-channels of the J-FET's 12 and 14 are connected between a power supply line 6 and the collectors ofthe NPN transistors 16 and 18. The emitter of the NPN transistors is grounded to a line 8, the collector being connected to an output line 20.

The gate oftheJ-FET 12 and the base ofthe NPN transistor 16 are arranged to receive simultaneously either high orlowinputsignals applied along an input line 10. Similarly, the gate of the J-FET 14 and the base of the NPN transistor 18 receive simultaneously either a high or low input signal applied along an input line 11. By appropriate choice of voltage (VBE+A) on the power supply line 6,the choice being dependent on the characteristics ofthetransistors 16 and 18 and 12 and 14 and on the desired speed of operation, the J-FETs 12 and 14 behave in operation as active switching elements ofthe gate circuit.

The circuit of Figure 1 has some similarities to CMOS devices in that both polarities of active device are available, and in each ofthe output logic states, there is no net currentthroughthe switch, i.e. as for CMOS the primary currentterm is in the charge and discharge of nodal capacitances.

As shown in the diagram,the power rail should be incrementally greaterthan oneVsE, and shouidarack VBE with temperature. This requirement is as for 12L.

Unlike 12L, active drive is available in both high and low states, while standby current is very small,thus, like CMOS, the ci rcuit will demand powerforswitching butsave power in the static state. Again as for CMOS, it is possible to produce faster versions of a gate by powering up; either by device scaling or, as for 12this might be conveniently carried out by increasing the power supply voltage.

The sink for static current is the base current ofthe NPN transistor and the gate current in the P-JFET when forward biased. Both of these currents will be controlled by the power supply voltage, although it is emphasised that this control is no more difficultthan for 12L, and will probably be carried out in the same way. Where operation from a single battery cell is required, a series resistor may be used. Alternatively, logic could be stacked across a high voltage supply to further improve efficiency, as is often the case with l2L.

In another embodiment (not shown) the integrated two input NOR gate may be designed by employing two n-channel junction field-effect transistors to replace the two P-channel junctionfield-effecttransis- tors 12 and 14, and by replacing the two NPN transistors 16 and 18 bytwo PNPtransistors.

Referring to the circuit diagram of Figure 2 there is illustrated an integrated two input NAND gate. The NAND gate includes two P-channel junction fieldeffect transistors 22,24 the gate of each ofwhich is connected to the base of a respective one of a pair of NPN transistors 26,28. The transistors 22,24 are arranged in parallel relationship havingtheirP- channels connected in parallel between the supply line 6 and the collector ofthe NPN transistor26. The NPN transistors 26,28 are arranged in series relationship between an output line 30, which is connected to the collector of the NPN transistor 26, and the ground line 8.

In another embodiment (not shown) the integrated two input NAND gate may be designed by employing two N-channel junction field-effecttransistorsto replace the two P-channel junction field-effecttransis- tors 22,24 and by replacing the two NPN transistors 26,28 by PNP transistors.

In orderto realize the NOR gate and NAND gate circuit designs described above within a chip having a high packing density of gates and a relatively low power of operation use is made of "pinch" resistors within the chip design in a novel manner.

Fundamentally, all conceivable bipolar processes contain, without additional process stages, a pinch type resistor, of sheet resistivity typically between Skohms and 30kohms per square. Although usually this is measuured, it is normally only used as a reference point for the estimation of base resistance.

Since the current gain, hfe, is a controlled process parameter in virtually all bipolar processes, and the pinch resistance and transistor hfe are very closely linked, it may be argued that pinch resistance is in principle fairlywell controlled. In addition, the temper- ature coefficient of pinch resistors is positive and usuallysimilarto conventional base resistors (although not normally close enough for inter-type tracking).

The above considerations led usto the development of pinch resistors in low power logic circuits and to the realization thatthe pinch resistorstructure, if the "emitter" region is used as a gate, is a P-channel JFET which is a device rarely used. However, we found that with small geometry processes, the characteristics are farsuperiorto previous versions and it is possible to usethejFETasanactiveswitching element.

This in turn led to the integrated circuit designs referred to in Figures 1 and 2 and to illustrate this novel technique further reference is made to Figures 3 to 6.

Figure 3 illustrates a sectional view through a doped silicon layer defining a stranded NPN transistor. By a3teringthe layoutslightlya P-channel junction field-effect transistor (Figure 4) may be produced in place of the NPN transistor. Compared to the standard NPN transistor, in the P-channel junction field-effect transistorthe emitter region is extended to separated the two base regions. The bases become, respectively, the source and the drain ofthe P-channel junction field effecttransistor, while the emitter becomes the gate.

The sub-emitter base resistance takes the form of a "pinch" resistor to form the P-channel.

Figure 5 illustrates the manner in which part ofthe circuit design of Figure 1 is realized using the structures of Figures 3 and 4. The drain contact is not essential and could be removed to save area. The use of double (N+ and P+) polysilicon as an interconnect technology is known, but is particularly advantageous in the configuration of the invention as it reduces the number of contact holes needed and hence reduces the chip area pergate.

The plan layout of the chip configuration is illustrated in Figure 6A. As can be seen by comparing with Figures3to 5the major difference between the layout of the NPN transistor and the P-channel field-effect transistor lies in the extended N+ doped "emitter" region which becomes the gate of the P-channel field-effecttransistor. The extended N+ doped "emitter" region effectively separates off into two separate reg ions the P+ doped area which would otherwise define base regions which thereby become respec tivelythe source and drain of the P-channel field-effect transistor.

It is our belief that the logic circuit described above in Figures 5, 6A and 6B has both self-powering advantages usuallyfound in CMOS technology and the very low voltage operation advantages usually found in ZLtechnology Furthermorethe logic circuit structure according to the present invention is we beiieve fulíy process compatible with standard bipolar processèsFand Zs potentially fasterthan 12L or CMOS gate structures. In addition the logic circuit structure according to the invention uses very few metal contacts and hence is of high yield.

Itwill be appreciated that whereas Figures 5, 6A and 6B illustrated the structure of an inverter comprising a P-channel junction field-effecttransistor and an NPN transistor, in other embodiments ofthe invention the inverter may comprise an N-channel junction field effecttransistorand a PNPtransistor.

Although the present invention has been described with respecttp particular embodiments, it should be understood that modifications may be effected within the scope ofthe invention. For example whereas Figure 1 isa 2-input NOR gatetheconceptcould be extended to at least th ree inputs; and the J FETs may need to be ratioed as for CMOS, but are unlikely to be critical in this respect. Figure 2 shows the 2-input NAND gate. Multiple input gates will probably be operated in simplified form as in the most recent CMOS, possibly using transmission gates or even "domino" logic.

Different layouts ofthe circuits are possible in minimising chip area per gate. The cross-section of the proposed structures illustrates one very significant layout advantage (Figure 5). In a "doublepolysilicon" process such as Plessey Process HE, polysilicon can be extensively used as the interconnect,with a large saving in the numbers of contacts from the metal layers. This is particularly true of JFET-bipolar logic, and will lead to very compact layouts.

Transistor parametersforthe P-JFET have been shown to be relatively unimportant; the same is largely true of the NPN transistor. Series emitter resistance, often a problem in high speed circuits, will actually help operation of this circuit by avoiding "current-hogging" and generally reducing power rail voltage dependence. Gain at low currents is desirably high, sincethe circuit is intended for low current operation. Here again though, the complementary nature ofthe switch will help in adverse conditions.

Speed of operation is good and is adjustable to some extent via the power rail voltage. Assumimg a standby of 1 Oua, and an estimated 160fF output node capacitance of a 2-input, 2-output gate, over 100 MHz should be possible without making allowanceforthe speed-up effect of the complementary gate. Satura tion of the NPN transistor could slowthe operation; if this becomes a problem, the addition of a "feedback emitter" clamp should help. Total power consumption (static) on the basis outlined above would be, for say 30,000 gates, 240mW. This is probably an upper limit, although more power will be used dynamically.

Radiatioo hardhess, an increasingly importantspe cification, should be good. The JFET is an inherently harddeviceewhilethe lowsupplyvoltagewill elirni rvatethe possi bil ity of latch-u p. Sincethecurrent will be limited ultimately by the JFET, the circuit should be particularly hard for most threats.

An embodiment ofthe present invention is illustrated in Figure 7 which showsthe circuit diagram of a static memory cell using the JFET-- Bipolar logic configuration. The memoryelement consists of two NPN type bipolartransistors T1 and T2 and two J FETs T3 and T4. The JFETs are advantageously of the 'normally-off' or'enhancement'type as described above.

ThetransistorT, and T2 are coupled together as a cross-coupled latch. The emitters of the trnnsistorsT1 and T2 are connected to a negative rail 40 kept at a fixed potential e.g. OVorwhich may be fed bya current source; the choice being dependent on the memory sensing circuitry.

On each ofthe transistors T1 and T2 a second emitter connection is provided, connected respectively to rails labelled 'bit line' 42 and 'bit line' 44. An upper power rail 46 to the circuit can be conveniently used as a 'word line'. The operational sequency is: 1. Writing a) The data to be written to the element is set on lines 'Bit line' 42 and 'Bit line' 44. One line is high and the other low relative to the negative rail 40.

b) Raise the word line potential.

c) If the bipolartransistor addressed by the low bit line is 'on', it will remain so.

d) Ifthe bipolartransistor addressed by the low bit line is'off', itwill conductcurrentthrough the emitter connected to the bit line. This pulls the collector potential down, turning 'off' the other half ofthe latch, and, by regenerative action, latching the side addressed 'on'.

2. Reading a) The bit lines are connected to a 'sense' amplifier which detects relative 'high' and 'low' levels.

b) Theword lineistaken high.

c) The sense amplifier reads the data in the cell in a non-destructive way, i.e. the current taken from the cell is not sufficient to disturb the sense ofthe cell.

In the above description ofthe operational sequ encetheterms 'high' and 'low' refer to relative logic levels. The exact values will be determined by the circuitry not shown and will depend on the precise characteristics ofthe devices used.

The random-access bipolar memory cell makes use of very low standby power, occupies very small chip area and is capable of high speed.

Afurther embodiment ofthe present invention is illustrated in Figure 8 which shows the circuit diagram of a CMOS-like random access memory cell in a bipolar process. The circuit elements are NPN transis torsT1 and T2 and P-channei JFETs.The circuit consists ofthe two bipolartransistors T and T2 and fourJFETtransistorsT3, T4,T5 and T6. The circuit is poweredthrough lines marked 'Ov' and 'Vcc'. The latter is maintained typically atVbe + A where Vbe is the forward base-emittervoltage ofthe bipolar transistors and A is a small voltage, of the order of 10-50mV, but could be as high as300mV.

In operation,thetransistorsT1 toT4form a cross-coupled latch circuit. Transistors T5 and T6, when addressed by taking the word line low, connect the latch to the lines 'Bit' and 'Bit'. During the write operation,the bitand bit lines aresetto appropriate 'high' or'low' levels. In this context, high is approximately equivalent to Vcc and 'low' is approximately Ov.

When the word line is addressed by taking it low, the cell acquires the high/low combination of levels as set bythe bit and bit lines, i.e. if bit is high and bit is low, T2 turns on,turningT1 off.Similarly,T4 turns off,turning T3 on i.e. the latch repeats the state ofthe bit lines. In general, it may be necessary to arrangeT5 andT6to be larger devicesthan T3 andT4to ensure this condition.

During read operations, the bit and bit lines connect to 'sense' amplifiers which buffer the outputs to the rest of the circuit. Enabling theword line, bytaking it low, transfers data from the latch tothe sense amplifier.

Advantages of this memory cell over conventional circuits are that much lower power is required than with bipolar memories anahigher speedthan CMOS memories. Addresssing is also simplerthan bipolar memories.

Claims (17)

1. An integrated logic circuit comprising bipolar transistors and junctio n fiel d-effect tra nsisto rs (J FETs); wherein the junction field-effecttransistors are arranged in the circuit to serve as switching elements, the gates ofthefieldeffecttransitors being connected to the bases ofthe bipolar transistors.

2. An integrated logic circuit as claimed in claim 1 wherein the channels oftheJ-FETsare connected between a supply voltage line and the collectors ofthe bipolartransistors.

3. An integrated logic circu it as claimed in claim t or claim 2 wherein each ofthe J-FETS hays a P-c-hannel and each of the bipolar transistors is ofthe NPN type

4. An integrated logic circuit as claimed in claim X orclaim 2 wherein each oftheJ-FETs has an N-channel and each ofthe bipolartransistors is ofthe PNPtype.

5. An integrated logiccircuitasclaimed in any one of claims 1 to 4wherein the channels ofthe J-FETs are formed in the integrated structure design as "pinch" resistors.

6. An integrated logic circuitas claimed in claimS wherein the "pinch" resistor defining the channel is in theform of a doped region of the same or similar type to that used to define a sub-emitfer base resistance in the integrated bipolartransistor.

7. An integrated logic circuit as claimed in any one of claims 1 to 6 wherein thethickness ofthe channel of the J-FET lies substantially within the range 0.5 micron to 0.05 micron.

8. An integrated logic circuit as claimed in any one of claims 1 to 6 wherein the thickness ofthe channel of the J-FET is 0.2 micron or less.

9. A logic array comprising a plurality of integrated logic circuits, each as claimed in any one of the preceding claims, wherein the junction field-effect transistors are arranged in series relationship to one another and the bipolartransitors are arranged in parallel relationship to one another, the gate of each field-effect transistor being connected to the base of a respective one ofthe bipolartransistors.

10. A logic array comprising a plurality of logic circuits, as claimed in any one of claims 1 to 6, wherein the junction field-effecttransitors are arranged in parallel relationship to one another and the bipolar transistors are arranged series relationshipto one another, the gated of each field-effecttransistor being connected to the base of a respective one ofthe bipolar transistors.

11. An integrated logic circuit constructed, adapted and arranged to operate substantially as herein before described with reference to one or more of Figures 1,2,5, GA and 6B of the accompanying drawings.

12. A logic arraycomprising a plurality of integrated logic circuits as claimed in claim 9.

13. A method of manufactu ring an integrated logic device comprising the use of bipolar processing steps to form a bipolartransistor and a junction--fietd-effect transistor within the integrated structu re-oth-edevice, the thickness ofthe channel ofthejunctiorì ffeidreTfiecb transistor being less than 0.5 micron anld tlie channel being formed in the integrated structure to function when in operation in a mannersimilarto a "pinch" resistor.

14. A static memory cell incorporating an integrated logic circuit as claimed in claim.

15. A static memory cell constructed, adapted and arranged to operate substantially as herein before described with reference to Figure 7 ofthe accompanying drawings.

16. A random access memory cell incorporating an integrated logic circuit as claimed in claim 1.

17. Arandom access cell constructed, adpated and arranged to operate substantialiy as hereinbefore described with reference to Figure 8 ofthe accompanying drawings.