GB2188217A - Baseband spread-spectrum modulators - Google Patents

Abstract

A spread-spectrum modulator includes a programmable read-only memory (PROM) 21 receiving data signals D0-D3, respective code sequences CODE 0 - CODE 3 and transmission enable signals TX0 - TX3. The PROM 21 is arranged to output a 4-bit word on lines Q0 - Q3 dependent on the states of the data, code and enable inputs A0-A11. A digital-to-analogue converter 22 converts the 4-bit word to an analogue output on line 23 for subsequent transmission, the output representing the enabled spread-spectrum signals added together. <IMAGE>

Description

SPECIFICATION saseband spread-spectrum modulators The present invention relates to baseband spread-spectrum modulators.

There has been significant recent interest in the development of spread spectrum transmission/reception systems. A direct sequence spread spectrum system may be viewed as an overlay to a conventional radio communication system. The original narrowband radio signal is multiplied (modulated) by a deterministic digital code sequence to produce a wideband radio signal.

The increase in bandwidth (spreading) results from the high code-bit rate of the spreading sequence. The wideband signal may be simply de-spread at the receiver by multiplication with an identical code sequence to restore the narrowband radio signal for subsequent demodulation.

An alternative approach is to spread the narrowband baseband data signal priorto modulation by the radio carrier to produce a wideband baseband signal which is subsequently modulated onto a radio carrier. This is a radio overlay to a baseband spread spectrum system.

Asignificantadvantage of spread spectrum systems is that multiple reception of a numberof signals can be achieved by the use in a receiver of sets of codes having low cross-correlation. Such sets of codes are termed orthogonal codes. Thus it is possible to achieve minimum interference between separate transmissions on the same carrier frequency and spread over the same frequency by selecting different codes from such an orthogonal set.

Further details of spread spectrum systems, their use and their implementation can be obtained from the appropriate literature, for example, "Spread Spectrum Systems", R.C. Dixon, John Wiley & Sons, 1976.

The function of a baseband spread-spectrum modulator is to modulate an information-carrying or data channel by an appropriate code sequence in order to provide a spread spectrum signal for transmission. In the situation where a plurality of digital data channels areto be modulated by respective code-sequences, it has been proposed to effectthe modulation in separate multipliers, and to pass the outputs of the multipliers through respective enabling transmission gates to a summing circuit, the output of the summing circuit representing the combined spread-spectrum signal for transmission.A problem with this approach is that the outputs of the transmission gates must each have precise analogue levels for subsequent linear summing. Moreover, the number of components is relatively high and the requirement for precise maintaining of analogue signai levels leads to an expensive circuit.

According to the invention there is provided a baseban d spread-spectru m modulator for modulating a plurality of data signals with respective spread-spectrum code sequences and providing the resulting spread-spectrum signals on an output line for transmission, the modulator comprising a memory arranged to receive the data signals and the code sequences, and responsive thereto to provide a digital output dependent thereon, and a digital-to-analogue converter operable to convert the digital outputofthe memory to an analogue outputfortransmission.

Preferably, at least one transmit enable channel is provided as a further input to the memory, the transmit enable channel or channels being operative on data signal channels. Onetransmitenable channel may control all the data signal channels.

Alternatively, each transmit enable channel may be arranged to control a corresponding subset of data signal channels. As a further alternative, each transmit enable channel may control a corresponding single data signal channel.

The invention will now be described, by way of illustrative and non-limiting example, with reference to the accompanying drawings, in which: Figure lisa circuit diagram of a previously-proposed modulator; Figure2 is a circuit diagram of a modulator according to one embodiment ofthe invention; and Figure 3 is a circuit diagram of a modulator according to another embodiment of the invention.

Referring to Figure 1, the previously-proposed spread-spectrum modulator as described above is shown in greaterdetail. Data channels DOto D3and corresponding code sequence carriers CODE 0 to CODE 3 are shown as being connected to inputs of respective exclusive-OR gates 10 to 13. The exclusive-OR gates 10 to 13 effectively multiply digital signals on the data channels DOto D3 by the respective code sequences CODE 0 to CODE 3 to produce output signals each of which has states of + 1 or - 1.The code sequences, as described above, each comprise a sequence of bits or chips, the bit rate of the code being considerably higherthan the maximum signal of the basebandfrequency. Itwill be apparent that, if the code sequence is considered to have states of +1 and and the modulation is effectively multiplication of the data signal bythat code sequence, then demodulation of the received signal can be effected by afurther multiplication by an identical code (with states of + 1 and - 1) precisely synchronised with the modulation code, since multiplication twice by either +1 or -1 yields +1, and therefore the original signal will be recovered.

The outputs from the gates 10 to 13 are connected via respective transmission gates 14to 17to corresponding inputsofa summing circuit 18.The transmission gates 14to 17 are responsiveto respective enabling signals TXO to TX3 to ailow transmission of the spread signals as required. Thus the transmission gates 14 to 17 act to select a subset of channelsfortransmission. It will be seen from Figure 1 that teach input to the summing circuit 18 can vary between states +1,0 or - 1. The states + 1 and -1 are those atthe output of the respective multiplier gate, and the state 0 occurs when the respective transmission gate is blocking passage of the signal.Since each input to the summing circuit 18 can vary between + 1, 0 and -1, and since any of these states can be present at a particular instant on any of the inputs to the summing circuit 18, the output 19 ofthe summing circuit l8will vary in unit steps between 14 and +4. Thus the summing circuit 18 must exhibit good linearity and moreoverthe outputs of the transmission gates 14to 17 must have precisely-matched analogue levels for accurate linear summing. The circuit istherefore relatively complex and expensive to manufacture.

Figure 2 shows a circuit according to one embodiment of the invention. Data channels DO to D3, code sequence channels CODE Oto CODE 3 and transmission enabling lines TX0 to TX3 respectively carry data, code sequences and enabling signals as in Figure 1. However, all the channels are applied to respective address inputs of a memory, preferably a programmable read-only memory (PROM) 21 with address inputs A0 to All, and outputs QO to 03. The outputs Q0 to 03 are connected to a digital-to-analogue converter 22 which provides an analogue outputfortransmission on a line 23.

The PROM 21 is programmed in such a manner that depending on the particular combination of signals on the various data, code and enable inputs, a particular digital output is provided at the outputs Q0toQ3.Asshown in Figure 2,fourdata channels DOto D3 are provided andthereforethe PROM 21 has twelve inputs A0 to All. In this case,the PROM 21 is a 4096 x 4-bit PROM. The data, code and enable inputs (twelve bits) address 4096 PROM locations each of which has been programmed with a 4-bit word, which when applied to the converter 22 produces the required analogue output (between -4 and +4) on the line 23to model the circuit of Figure 1 exactly.The PROM 21 includes four outputs Q0 to Q3 since nine levels are required from the output 23 of the converter 22, and therefore 4-bit control is required to achieve these nine levels.

The advantage ofthe circuit shown in Figure 2 is thatthe digital circuitry is confined to the PROM 21 and the precision analogue circuitry is confined to the digital-to-analogue converter 22. Any digital-to-analogue conversion law may therefore be accommodated. Thus the arrangement is simpler and cheaperthanthat of Figure 1.

Figure 3 shows a variation ofthe circuit of Figure 2 in which the data channels are enabled in pairs, rather than separately. Thus only two transmit enable channels TX0l and TX23 are provided, for enabling data channels DO and D1 together, and data channels D2 and D3 together, respectively. The data, code and enable inputs are applied to a PROM 31 which is connected to a digital-to-analogue converter 32 providing the required output for transmission on a line 33, as in Figure 2. However, since only two transmit enable channels TX0l , TX23 are provided, each channel pair can only produce3 levels, namely +2,0, -2 and therefore the sum ofthe two channel pairs can only have 5 levels, namely4, 2, 0, -2, -4. Hence only 3-bits are requiredforthe digital-to-analogue converter 32 and the PROM 31 requirement is reduced to 1024 x 3-bit.

The advantages ofthe Figure 3 circuitare similarto those of Figure2, and the additional factors that the capacity of the PROM is significantly reduced and so is the bit-number of the digital-to-analogue converter.

If separate transmission control is not required, it is possible to reduce the transmit enable channels to a single channel controlling all the data channels together. Alternatively, the transmit enable channels may be omitted altogether, and each of these further implementations will result in a reduction in the required storage capacity of the memory.

Claims (10)

1. A baseband spread-spectrum modulatorfor modulating a plurality of data signals with respective spread-spectrum code sequences and providing the resulting spread-spectrum signals on an output line for transmission, the modulator comprising a memory arranged to receive the data signals and the code sequences, and responsive thereto to provide a digital output dependent thereon, and a digital-to-analogue converter operable to convert the digital output ofthe memoryto an analogue outputfortransmission.

2. A modulator according to claim 1, wherein the memory is a read only memory.

3. A modulator according to claim 2, wherein the memory is a programmable read only memory.

4. A modulator according to claim 1,claim 2, or claim 3, wherein the memory is arranged to receive at least onetransmission enable signal which is operative on at leastone data signal channel.

5. A modulator according to claim 4, wherein a single said transmission enable signal is operative on all data signal channels.

6. A modulator according to claim 4, wherein the memory is arranged to receive a plurality of transmission enable signals each of which is operative on a corresponding subset of data signal channels.

7. A modulator according to claim 4, wherein the memory is arranged to receive a plurality of transmission enable signals each ofwhich is operative on a corresponding one ofthe data signal channels.

8. A modulator according to claim 7,wherein the memory is arranged to receive four data signal channels and fourtransmission enable signals, and the memory has 4096 x 4 - bit locations.

9. A modulator according to claim 6, wherein the memory is arranged to receive four data signal channels and two transmission enable signals each of which is operative on a respective two of the data signal channels, and the memory has 1024 x 3 - bit locations.

10. Abaseband spread-spectrum modulator substantially as herein before described with referenceto Figure 2 or Figure 3 of the accompanying drawings.