GB2185666A - A data bus coupler - Google Patents
A data bus coupler Download PDFInfo
- Publication number
- GB2185666A GB2185666A GB08630748A GB8630748A GB2185666A GB 2185666 A GB2185666 A GB 2185666A GB 08630748 A GB08630748 A GB 08630748A GB 8630748 A GB8630748 A GB 8630748A GB 2185666 A GB2185666 A GB 2185666A
- Authority
- GB
- United Kingdom
- Prior art keywords
- bus
- signal
- bus part
- receiver
- coupler
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims abstract description 3
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 238000009434 installation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40032—Details regarding a bus interface enhancer
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40019—Details regarding a bus master
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/403—Bus networks with centralised control, e.g. polling
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
Abstract
Three or more data buses in accordance with Mil-Std 1553 are connected together by a connecting device. The latter comprises, for each bus, a logic circuit 12 which passes, to its associated bus, a signal from any one of the other buses and a signal detector 14 which upon detection of a signal from its bus part disables the receiver or enables the transmitter of every other bus part. Each bus preferably terminates at the connecting device with a hybrid junction matched to the characteristic impedance of the bus and allowing disconnection thereof without affecting either its own operation or the operation of the other buses. <IMAGE>
Description
SPECIFICATION
A data bus coupler
This invention relates to a data bus coupler. It arose in an endeavour to overcome limitations in an existing type of data bus called Mil-Std 1553 (known in U.K. as Defence Standard 0018) which is for use on military vehicles such as aircraft, tanks and ships.
The purpose of this type of data bus is to achieve internal high speed, high integrity communication between technical facilities within the vehicle. Such facilities could include mechanical things such as aircraft flaps and undercarriages; navigational instruments such as altimeters, air speed indicators and gyro-compasses; radio equipment; and an air data computer. Mil-Std 1553 (Defence Standard 0018) operates at 1 megabit per second and is a serial data bus using word lengths of twenty bits.
The data bus consists of a length of 77 + 7 ohm screened twisted pair balanced cable which is terminated by a resistor equal to its characteristic impedance at both ends. The signalling system uses a special code known as Manchester II which is a self clocking asynchronous code. The essential parts of such a bus are the cable, the termination resistors, a controller and up to thirty-one data terminals. The length of the cable does not usually exceed one hundred meters because of losses occasioned by resistance within the cable; dielectric losses in the insulating material; and bridging losses caused by power lost in the input resistance of the data terminals. The number of terminals cannot exceed thirty-one because the input resistance of more than that many terminals, connected effectively in parallel across one twisted pair would be unacceptable.
There is now a requirement to increase the number of terminals and to extend the data bus in certain vehicles. Using current practices this would entail replacing the existing data bus installations with new installations designed to a different specification. This would be expensive and would involve a departure from Mil-Std 1553 which would mean that equipment designed for use with Mil-Std 1553 would not correctly interface with the new system and the whole value of having a wellunderstood and standard system would be lost.
Existing Mil-Std 1553 (Defence Standard 0018) data buses sometimes have what is called a "stub connection". In such a stub connection one coil of a stub coupling transformer is connected across the lines of the main data bus via customary protection resistors and the other coil is connected to a length of bus cable (the "stub") which leads to the primary of a second remoteterminal unit (RTU) transformer similar to the first. Such a stub connection can only serve one RTU and incurs a bridging loss which limits the number of stubs which can be used on a given main data bus.
The present invention provides a coupler for coupling together three or more data bus parts which interconnect terminals controlled in such a way that only one of them can transmit signals onto the bus at a given time, the coupler comprising: associated with each bus part a receiver which reshapes pulses from that bus part, associated with each bus part a transmitter for amplifying the output from any receiver associated with a different bus part and transmitting it along the associated bus part; and, also associated with each bus part, a signal detector for detecting a signal from that bus part and arranged so that, in response to a detection, it either disables any receiver associated with another bus part or enables any transmitter associated with another bus part.
By employing the invention it is possible to build a stub connection which can serve more than one remote terminal unit, which loads the line only to the extent of a single RTU and which can furthermore be disconnected without inhibiting normal operation of the main data bus. A coupler constructed in accordance with the invention can also be used to join together three or more data buses end to end.
Whilst it is possible for each signal detectorto be arranged to enable all the transmitters other than that with which it is associated; the preferred arrangement is for it to disable the receivers other than that with which it is associated. This is because it is a relatively simple matter to complete the disabling function before the signal causing it has been processed by the appropriate transmitter and has reached the input to the various receivers.
The signal detector can be at the input or the output of the associated receiver. Each receiver may be of the type which has two outputs on one of which it produces a re-shaped version of the received signal and on the other of which it produces an inverted version thereof; and in which each receiver includes a threshold detector which causes the outputs to adopt the same state when the input signal is below a certain amplitude. In this arrangement the signal detectors need do no more than to sense when the outputs adopt the same state.
One way in which the invention may be performed will now be described by way of example with reference to the accompanying drawings in which: Fig. 1 is a schematic block diagram showing a data bus system constructed in acordance with the invention;
Fig. 2 shows at A, B and C signals shown at respective points A, B and Con Fig. 1. Referring to figure 1, the illustrated arrangements comprises four data buses lA, IB, 1C and 1D all of which are similar and only two of which, IA and 1 B, are shown and will be described in detail.
The data bus 1A comprises a twisted pair of cables 2 and 3 constructed in accordance with Mil
Std 1553. Attached to the cables 2 and 3 are thirtyone data terminals 4 and a central controller 5 which communicate with each other in a way well known to those familiar with Mil-Std 1553. At one end of the twisted pair 2,3 is a termination 6 in the form of a resistor which has the same impedance as the characteristic impedance of the cable 2,3. The other end of the cable 2,3 is terminated by a resistor 7, which is the same value as resistor 6, an isolation transformer 7A and isolation resistors 7B as required by Mil-Std 1553.
The data buses 1A, 1B, 1C and 1D are all connected together by a connecting device 8 to which they are releasably attached by plug and socket connections shown schematically at 9A, 9B, 9C and 9D.
The voltage A across the wires 2 and 3 of bus 1A is applied in the connecting device 8 to the input of a receiving amplifier 1 or. The signal at the input of this receiving amplifier 1 OA varies between a positive and a negative value. Because of the attenuation of the high frequency components of this signal by the data bus 1Athis signal has lost its sharp edges as can be seen from Figure 2A.
The purpose of the receiving amplifier 10A is to convert the signals shown at 2A into a corresponding logic signal varying between a positive value and zero as shown on figure 2B and to provide another logic signal, as shown on figure 2C, which is the logical opposite of 2B. These two logic signals B and C are applied on separate lines as shown on figure 1. Each receiving amplifier includes a threshold detector which, when the differential input signal is less than a particular value close to zero, causes the two outputs to go positive.
An input to the data bus 1A is applied via a transmitting amplifier 11Athe purpose of which is to convert incoming logic signals like those shown at B and C on figure 2, to a signal like that shown at 2A but of course with relatively sharp leading and trailing edges whose precise form meets the requirement of Mil-Std 1553. When the two inputs to the transmitting amplifier 9 are the same the transmitter output goes to zero.
The connecting device 8 comprises logic circuits 12A, 12B, 12C and 12D, one associated with each data bus. Each logic circuit, 12A, 12B, and 12D is connected to pass, to the transmitting amplifier 11 of its associated data bus, signals on the output line
B from the receiving amplifiers of all the other buses but not from the receiving amplifier of its own associated bus. The connection device 8 also includes logic circuits 13A, 13B, 13C and 13D each of which is connected to pass, to the transmitting amplifier of its associated bus, signals on the line C from the receiving amplifiers of all the other buses but not from the receiving amplifier of its own associated bus.The signals applied at the output of a receiving amplifier are passed via the logic circuits to the inputs of the transmitting amplifiers unchanged. This assumes that the input, not being used, to the logic circuits (which are AND gates) are at a high level. This assumption can correctly be made because, in this system, only one terminal 4 is allowed by the controller 5, to transmit at any given time: and in the absence of a signal A at the input of the receiving amplifier its two outputs go high. In an alternative system where the receiving amplifier outputs go low in the absence of an input signal, the
AND gates would be replaced by OR gates.
In the arrangement as described so far the signal
Afrom bus would be received at 10A, amplified at 11B, 11C and 1 1D and then be fed back via receivers 108, 10C and 1 OD and transmitter 1 to the bus 1A. This would corrupt the original signal on 1A. To prevent this detectors 14Ato 14D are included. Each of these receives the two outputs from an associated receiver and provides an output signal A, B, C or D which, when at a high level, indicates when the two lines are different, thus indicating the presence of a signal on the input to the receiver. The output signal from a detector 14 is appplied to an input of each of the gates 15 except that with which it is associated.Each gate 15 is a
NOR gate and the application of a logic high signal to any one of its inputs causes its output to go low, thus blocking the operation of the associated receiver 10.
The time taken for a detector 14 to react to the presence of a signal and for the circuits 14 and 10 to respond is typically 10 nS which is less than the time, typically 500nS for the signal to reach the inhibited receiver.
It will be observed that the bus 1 B is attached to the connector 8 at its mid point, avoiding the need for a terminating resistor 7. In an alternative configuration two or more (up to 4 in the illustrated example) can be connected at their mid points.
It will be appreciated that the arrangement shown in figure 1 immensely increases the potential use of data buses constructed in accordance with Mil-Std 1553 in that it allows a principal bus to be extended by the addition of branches or enables stub connections to be made to it with each stub connection itself providing the same capability as the unexpected bus. Furthermore the various extensions can be plugged in or unplugged providing great adaptability or, in situations where this may be required, allowing one of the branches to be disconnected and thereafter to continue functioning under the control of its own controller similar to that shown at 5.
Claims (6)
1. A coupler for coupling together three or more data bus parts which interconnect terminals controlled in such a way that only one of them can transmit signals onto the bus at a given time, the coupler comprising: associated with each bus part a receiver which re-shapes pulses from that bus part; associated with each bus part a transmitter for amplifying the output from any receiver associated with a different bus part and transmitting it along the associated bus part; and also associated with each bus part, a signal detector for detecting a signal from that bus part and arranged so that, in response to a detection, it either disables any receiver associated with another bus part or enables any transmitter associated with another bus part.
2. A coupler according to claim 1 in which each detector is operative to disable all receivers other than that with which it is associated sufficiently fast to ensure that the output from any transmitter is not received and transmitted back to the bus part with which that detector is associated.
3. A coupler according to any preceding claim in which each receiver has two outputs on one of which it produces a re-shaped version of the received signal and on the other of which it produces an inverted version thereof and in which each receiver includes a threshold detector which causes the outputs to adopt the same state when the input signal is below a certain amplitude, and in which the signal detectors are designed to sense when the outputs adopt the same state.
4. A coupler according to any preceding claim in which the signal detectors are arranged to render disoperative the aforementioned receivers.
5. A coupler substantially as described with reference to Fig. 1 and substantially as illustrated therein.
6. A data bus system incorporating data buses and a coupler substantially as described with reference to Fig. 1 of the accompanying drawings and substantially as illustrated therein.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8600983 | 1986-01-16 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8630748D0 GB8630748D0 (en) | 1987-02-04 |
| GB2185666A true GB2185666A (en) | 1987-07-22 |
| GB2185666B GB2185666B (en) | 1989-10-25 |
Family
ID=10591461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8630748A Expired GB2185666B (en) | 1986-01-16 | 1986-12-23 | A data bus coupler |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2185666B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0410873A1 (en) * | 1989-07-25 | 1991-01-30 | Regie Nationale Des Usines Renault | Device for interconnecting and extending busses in an information transmission network |
| EP0419711A1 (en) * | 1989-09-28 | 1991-04-03 | Siemens Aktiengesellschaft | Interface module for coupling modulated signals thereto |
| EP0419712A1 (en) * | 1989-09-28 | 1991-04-03 | Siemens Aktiengesellschaft | Decoupling device for a bus communication system |
| EP0419713A1 (en) * | 1989-09-28 | 1991-04-03 | Siemens Aktiengesellschaft | Interface module for a bus interface |
| DE4213569A1 (en) * | 1992-04-24 | 1993-10-28 | Siemens Ag | Interface module for connecting two bus segments |
| WO2010128263A1 (en) | 2009-05-07 | 2010-11-11 | Heikki Rastas | System for electrically connecting an electric vehicle to a stationary charging station |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2074426A (en) * | 1980-04-18 | 1981-10-28 | Hewlett Packard Ltd | Logic circuitry for intercommunication between distant bus systems |
| GB2118004A (en) * | 1982-03-05 | 1983-10-19 | Western Electric Co | Data communication system |
| GB2127652A (en) * | 1982-07-31 | 1984-04-11 | Sharp Kk | Bidirectional in-line signal compensation circuit |
| GB2131254A (en) * | 1982-12-02 | 1984-06-13 | Western Electric Co | Collision avoidance circuit for packet switched communication system |
-
1986
- 1986-12-23 GB GB8630748A patent/GB2185666B/en not_active Expired
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2074426A (en) * | 1980-04-18 | 1981-10-28 | Hewlett Packard Ltd | Logic circuitry for intercommunication between distant bus systems |
| GB2118004A (en) * | 1982-03-05 | 1983-10-19 | Western Electric Co | Data communication system |
| GB2127652A (en) * | 1982-07-31 | 1984-04-11 | Sharp Kk | Bidirectional in-line signal compensation circuit |
| GB2131254A (en) * | 1982-12-02 | 1984-06-13 | Western Electric Co | Collision avoidance circuit for packet switched communication system |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0410873A1 (en) * | 1989-07-25 | 1991-01-30 | Regie Nationale Des Usines Renault | Device for interconnecting and extending busses in an information transmission network |
| FR2650459A1 (en) * | 1989-07-25 | 1991-02-01 | Renault | BUS INTERCONNECTION AND EXTENSION DEVICE IN AN INFORMATION TRANSMISSION NETWORK |
| US5166957A (en) * | 1989-07-25 | 1992-11-24 | Regie Nationale Des Usines Renault | Bus interconnection and extension device in a data transmission network |
| EP0419711A1 (en) * | 1989-09-28 | 1991-04-03 | Siemens Aktiengesellschaft | Interface module for coupling modulated signals thereto |
| EP0419712A1 (en) * | 1989-09-28 | 1991-04-03 | Siemens Aktiengesellschaft | Decoupling device for a bus communication system |
| EP0419713A1 (en) * | 1989-09-28 | 1991-04-03 | Siemens Aktiengesellschaft | Interface module for a bus interface |
| US5305465A (en) * | 1989-09-28 | 1994-04-19 | Siemens Aktiengesellschaft | Interface chip for coupling modulated signals |
| JP2523457B2 (en) | 1989-09-28 | 1996-08-07 | シーメンス、アクチエンゲゼルシヤフト | Interface Module |
| DE4213569A1 (en) * | 1992-04-24 | 1993-10-28 | Siemens Ag | Interface module for connecting two bus segments |
| EP0566935A3 (en) * | 1992-04-24 | 1995-10-18 | Siemens Ag | Interface module for connecting two bus segments |
| WO2010128263A1 (en) | 2009-05-07 | 2010-11-11 | Heikki Rastas | System for electrically connecting an electric vehicle to a stationary charging station |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8630748D0 (en) | 1987-02-04 |
| GB2185666B (en) | 1989-10-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |