GB2181025A

GB2181025A - Clock signal multiplexers

Info

Publication number: GB2181025A
Application number: GB08523526A
Authority: GB
Inventors: Richard Joseph Andrew Avis
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 1985-09-24
Filing date: 1985-09-24
Publication date: 1987-04-08
Also published as: GB2181025B; GB8523526D0

Abstract

A clock signal multiplexer for combining first and second input clock signals ckx, cky serially into a single channel, by selectively passing either of the input clock signals ckx, cky to an output of the multiplexer to the exclusion of the other, comprising a selector circuit 16 having a first input Z3 to which the first input clock signal ckx is supplied, a second input Z0 to which the second input clock signal cky is supplied and a third input Z1/Z2 which is maintained at a fixed reference level, a control signal generator 14, 15 for selectively controlling the selector circuit 16 such that one only of the inputs Z0, Z1/Z2, Z3 is connected to the output of the multiplexer and so that when the first input Z3 or the second input Z0 is connected to the output of the multiplexer, the third input Z1/ Z2 is next connected to the output of the multiplexer, and a control arrangement 9, 10, 11 to control the control signal generator 14, 15 such that when the first input Z3 or the second input Z0 is connected to the output of the multiplexer, the selector circuit 16 can only be changed over to connect the third input Z1/Z2 to the output of the multiplexer when the first or the second input clock signal ckx, cky currently supplied via the first or second input Z3, Z0 to the output of the multiplexer is at the fixed reference level. <IMAGE>

Description

SPECIFICATION Clock Signal Multiplexers This invention relates to clock signal multiplexers.

The need to multiplex two clock signals together, that is to say to combine the two clock signals serially into a single channel, by selectively passing either of the clock signals to the exclusion of the other, arises in various circuits. Consider, for example, a digital video tape recorder which is deriving two binary data signals via respective reproducing heads, where both data signals are to be stored in a single memory, such as a random access memory forming a field store. In this case, a respective clock signal will be derived from each reproduced data signal for use in controlling the memory when that data signal is to be stored.

Ideally, the two clock signals will remain in a constant phase relationship, but in practice, due to jitter, this may not be so, and as a consequence there may be a clash of control at the memory.

Particularly in the case of a random access memory, such a clash can result in total loss of the stored data.

In these and other circuits there is, therefore, a requirement for a clock signal multiplexer capable of multiplexing two independent clock signals together to form a single output clock signal, with the assurance that the output clock signal will always contain complete clock cycles and be glitchfree. Previously proposed clock signal multiplexers, such as simple switching devices, do not provide these assurances.

According to the present invention there is provided a clock signal multiplexer for combining a plurality n of input clock signals serially into a single channel, by selectively passing one of said n input clock signals to an output of said multiplexer to the exclusion of the other n-l input clock signals, the multiplexer comprising:: a first selector circuit having n clock signal inputs, a reference input, and an output which forms said output of the multiplexer, said n input clock signals being supplied to said n clock signal inputs, respectively, and said reference input being maintained at a fixed reference level; a control signal generator for selectively controlling said first selector circuit such that one only of said clock signal inputs is connected to said output of the multiplexer and so that when any one of said clock signal inputs is connected to said output of the multiplexer, said reference input is next connected to said output of the multiplexer; and means to control said control signal generator such that when any one of said clock signal inputs is connected to said output of the multiplexer said first selector circuit can only be changed over to connect said reference input to said output of the multiplexer when said input clock signal currently supplied via said one of said clock signal inputs to said output of the multiplexer is at said fixed reference level.

According to the present invention there is also provided a clock signal multiplexer for combining first and second input clock signals serially into a single channel, by selectively passing either of said input clock signals to an output of said multiplexer to the exclusion of the other, the multiplexer comprising:: a selector circuit having first, second and third inputs and an output which forms said output of the multiplexer, said first input clock signal being supplied to said first input, said second input clock signal being supplied to said second input, and said third input being maintained at a fixed reference level; a control signal generator for selectively controlling said selector such that one only of said inputs is connected to said output of the multiplexer and so that when said first input or said second input is connected to said output of the multiplexer, said third input is next connected to said output of the multiplexer; and means to control said control signal generator such that when said first input or said second input is connected to said output of the multiplexer said selector can only be changed overto connect said third input to said output of the multiplexer when said first or said second input clock signal currently supplied via said first or said second input to said output of the multiplexer is at said fixed reference level.

The invention will now be described byway of example with reference to the accompanying drawings, in which: Figure 1 shows in block form an embodiment of clock signal multiplexer according to the present invention; Figure 2 shows waveforms referred to in describing the operation of the embodiment of Figure 1 in the case of multiplexing two clock signals comprising pulses of equal duration; and Figure 3 shows waveforms referred to in describing the operation of the embodiment of Figure 1 in the case of multiplexing two clock signals comprising pulses of unequal duration.

Referring to Figure 1, the embodiment of clock signal multiplexer to be described comprises two Dtype flip-flops 1 and 2 to the inputs 3 and 4 respectively of which are supplied the two clock signals which are to be multiplexed, hereinafter referred to as the clock X and the clock Y (in the drawings ckx and cky). Selection of the clock X or the clock Y as the output of the clock signal multiplexer is under control of control signals enable X and enable Y which are supplied by way of inputs 5 and 6 respectively to the D-inputs of the flipflops 1 and 2 respectively. The enable X and the enable Y are independent signals and each goes low, the other than being high, when the corresponding clock signal is to be the output of the clock signal multiplexer.

The Q output of the flip-flop 1 and the Q output of the flip-flop 2 are respectively connected to the two inputs of a NAND gate 7, and the Q output of the flipflop 1 and the Q output of the flip-flop 2 are respectively connected to the two inputs of a NAND gate 8. The outputs of the NAND gates 7 and 8 are connected to the set and reset inputs respectively of a latch 9. The NAND gates 7 and 8 correct any non mutual exclusivity in the enable X and the enable Y.

The clock signal multiplexer also comprises two shift registers 10 and 11 having input terminals 12 and 13 connected to their respective clock inputs. To the~input terminal 12 is supplied an inverted clock X (cks) and to the input terminal 13 is supplied an inverted clockY (cky). Inverted clockX is in synchronism with clock X, and inverted clock Y with clock Y; that is, there is no delay. From the Q output of the latch 9 a signal XPI is supplied to the data inputs of each of the shift registers 10 and 11.

Outputs from the first two stages of the shift register 10 are supplied to the two inputs A0 and Al of a 2:1 selector 14, while outputs from the first two stages of the shift register 11 are supplied to the two inputs BO and Bi of a 2:1 selector 15. The outputs of the selectors 14 and 15 are supplied as a pair of control signals A and B to a 4:1 selector 16. An output from the third stage of the shift register 10 is supplied to one input of an AND gate 17, and an output from the third stage of the shift register 11 is supplied to the other input of the AND gate 17. The output of the AND gate 17 forms a control signal for both of the selectors 14 and 15.

To two of the four inputs ZO and Z3 of the selector 16 are supplied the clock X and the clock Y by way of input terminals 18 and 19, respectively, while the other two inputs Z1 and Z2 of the selector 16 are connected to earth. The output of the selector 16 is supplied to an output terminal 20, and forms the output of the clock signal multiplexer.

The operation will now be described with reference also to Figure 2.

Figure 2 shows the multiplexing of the clock X and the clock Ywhere these two signals differ in phase but comprise pulses of the same duration and frequency. The lefthand side of Figure 2 shows a transition from the clock X to the clock Y, and the righthand side of Figure 2 shows a transition from the clock Y to the clock X. The enable X and the enable Y are latched by their respective clocks, the clock X and the clock Y, in theflip4lops 1 and 2, and their inverses are generated. They are then combined into the single signal XN, by the NAND gates 7 and 8, and the latch 9. The NAND gates 7 and 8 ensure that only one of the enable X and the enable Y controls the latch 9 at any given moment.

For example, if the clock X is currently being supplied as the output of the clock signal multiplexer, then the enable X must relinquish control by going high before the enable Y can reset the latch 9 and cause the clock Y to be the output of the clock signal multiplexer. The converse is also true.

The signal XN is then latched through the shift registers 10 and 11, one of which is clocked by the inverted clock X (ckx) and the other of which is clocked by the inverted clockY(cky). The first three outputs of the shift registers 10 and 11 are designated Qix, Q2x, and Q3x, and Q1y, Q2y and Q3y, respectively. The first two outputs Qix and Q2x of the shift register 10 form the two inputs of the 2:1 selector 14, and the first two outputs Q1y and Q2y of the shift register 11 form the two inputs of the 2:1 selector 15.The waveforms of all these signals are shown in Figure 2, the time differences in the transitions of the outputs Qlx, Q2x, Q3x, Q1y, Q2y and Q3y being equal to the periods of the clock X and the clock Y. The third outputs Q3x and Q3y of the shift registers 10 and 11 are combined by the AND gate 17 to form a control signal Q3x.Q3y for the selectors 14 and 15. The outputs of the selectors 14 and 15 respectively form the two control signals A and B for the selector 16, and depending on whether the control signals A and B are high or low, a particular one of the inputs ZO, Z1, Z2 and Z3 of the selector 16 is selected to form the output Z.The relationship is as follows: A B Z 0 0 1 0 Z1 0 1 Z2 1 1 Z3 The transition from the clock X to the clock Y will first be explained (lefthand side of Figure 2). The clock X is being supplied to the output terminal 20 and it is assumed that the enable X has relinquished control of the latch 9 by going high. Then, when the enable Y goes low, the latch 9 will be reset and the signal XPlwill go low.The signal X/Ywill then propagate through the shift registers 10 and 11 to generate Qix, Q2x, Q3x, Q1y, Q2y and Q3y, Q3x.Q3ywill currently be high so the control signal A from the selector 14 will be input A1, that is Qix, and the control signal B from the selector 14 will be input By, that is Q2y. At this time, both Qix and Q2y are high, and hence the input Z3 of the selector 16 forms the output so that the clock X continues to be supplied to the output terminal 20. As the signal XP/ propagates through the shift registers 10 and 11, 01x will go low first.The control signal Afrom the selector 14 will then go low, the control signal B from the selector 15 still being high, and this will cause the clock X to be de-selected by the selector 16, the 0 volts of the inputs Z1 and Z2 then being connected to the output terminal 20. Thus, as shown in the bottom waveform on the lefthand side of Figure 2, the clock X will cease subsequent to a complete pulse and the output clock signal will then remain low for a time.

Q2y will then follow by going low, causing the control signal B to go low, and hence the input Z0, that is the clock Y, will be selected by the selector 16, so that the clock Y is then supplied to the output terminal 20. Finally, when either Q3x or Q3y goes low, the selectors 14 and 15 will cause the control signal A to become input A0, that is Q2x, and the control signal B to become input BO, that is Q1y, in preparation for a further change from the clock Y backto clock X.

Turning now to the righthand side of Figure 2, the transition from clock Y to clock X is the converse of the above. Assuming that the enable Y has relinquished control by going high, then when the enable X goes low, this will cause the latch 9 to be reset so causing the signal X/Y to go high.

At this time the selectors 14 and 15 are selecting Q2x as the control signal A and Q1y as the control signal B. Hence, as the control signal WY propagates through the shift registers 10 and 11, Qly will go high so causing the selector 16 to deselect the clock Y. 02x then follows by going high so causing the clock X to be selected by the selector 16 and supplied to the output terminal 20. Finally, when both 03x and Q3y go high, the selectors 14 and 15 will cause the control signals A and B to become equal to Qix and Q2y, ready for the next change from the clock X to the clock Y.

Thus, in essence, the selectors 14 and 15 are used to select the appropriate control signals for the selector 16, to ensure that the current clock signal is de-selected, in dependence on the current clock signal, before the new clock signal is selected. By doing this, no output clock pulses are cut short, and no clock glitching occurs at the output terminal 20.

The above operation has been described in relation to the waveforms of Figure 2 where the clock X and the clock Y comprise pulses of equal duration and frequency, but differ in phase. It will be understood by following the above description in relation to Figure 3 that the effect is the same where the clock X and the clock Y comprise pulses of different durations and frequencies, again differing in phase. As with Figure 2, the lefthand side of Figure 3 shows a transition from the clock X to the clock Y, and the righthand side shows a transition from the clock Y to the clock X.

Embodiments of clock signal multiplexer as described can be used wherever two clock signals have to be combined to form a predictable and reliable single clock signal which will always contain complete clock cycles and be glitch4ree. The two input clock signals can be totally independent of each other in terms of both frequency and phase.

Embodiments of the invention are suitable for use, for example, where two inputs are to be combined prior to supply to a memory device, as memory devices are particularly susceptible to clock glitching, and for use with single port storage devices such as charge-coupled devices for data compression and expansion.

Various modifications can of course be made. For example, using the same principles, the invention can be extended to provide embodiments capable of multiplexing more than two input clock signals.

For example, a clock signal multiplexer for combining four input clock signals may be required for use with a 4-channel digital video tape recorder.

Claims

1. A clock signal multiplexer for combining a plurality n of input clock signals serially into a single channel, by selectively passing one of said n input clock signals to an output of said multiplexer to the exclusion of the other n-l input clock signals, the multiplexer comprising; a first selector circuit having n clock signal inputs, a reference input, and an output which forms said output of the multiplexer, said n input clock signals being supplied to said n clock signal inputs, respectively, and said reference input being maintained at a fixed reference level;; a control signal generator for selectively controlling said first selector circuit such that one only of said clock signal inputs is connected to said output of the multiplexer and so that when any one of said clock signal inputs is connected to said output of the multiplexer, said reference input is next connected to said output of the multiplexer; and means to control said control signal generator such that when any one of said clock signal inputs is connected to said output of the multiplexer said first selector circuit can only be changed over to connect said reference input to said output of the multiplexer when said input clock signal currently supplied via said one of said clock signal inputs to said output of the multiplexer is at said fixed reference level.

2. A clock signal multiplexer for combining first and second input clock signals serially into a single channel, by selectively passing either of said input clock signals to an output of said multiplexer to the exclusion of the other, the multiplexer comprising: a first selector circuit having first, second and third inputs and an output which forms said output of the multiplexer, said first input clock signal being supplied to said first input, said second input clock signal being supplied to said second input, and said third input being maintained at a fixed reference level;; a control signal generator for selectively controlling said first selector circuit such that one only of said inputs is connected to said output of the multiplexer and so that when said first input or said second input is connected to said output of the multiplexer, said third input is next connected to said output of the multiplexer; and means to control said control signal generator such that when said first input or said second input is connected to said output of the multiplexer said first selector circuit can only be changed over to connect said third input to said output of the multiplexer when said first or said second input clock signal currently supplied via said first or said second input to said output of the multiplexer is at said fixed reference level.

3. A clock signal multiplexer according to claim 2 wherein said clock signal generator comprises second and third selector circuits which supply respective binary control signals to said first selector circuit, said first input of said first selector circuit being connected to said output of the multiplexer when both said binary control signals are at one binary level, said second input of said first selector circuit being connected to said output of the multiplexer when both said binary control signals are of the other binary level, and said third input of said first selector circuit being connected to said output of the multiplexer when said binary control signals are of different binary levels, and wherein said means to control said control signal generator is operative such that both said binary control signals cannot change their binary level simultaneously.

4. A clock signal multiplexer according to claim 2 or claim 3 wherein a requirement to change the input clock signal supplied to said output of the multiplexer from one input clock signal to the other is signalled by the supply of a pulse edge, and wherein said means to control said control signal generator comprises first and second shift registers to each of which said pulse edge is supplied and each of which is operative under control of said first and second input clock signals respectively to step said pulse edge through the shift register, outputs of first and second stages of said first shift register being supplied as inputs to said second selector circuit and outputs of first and second stages of said second shift register being supplied as inputs to said third selector circuit.

5. A clock signal multiplexer according to claim 4 wherein outputs of third stages of said first and said second shift registers are combined to form a control signal for each of said second and said third selector circuits.

6. A control signal multiplexer according to claim 4 or claim 5 wherein said pulse edge is negativegoing when the input clock signal supplied to said output of the multiplexer is to change from said first input clock signal to said second input clock signal, and is positive-going when the input clock signal supplied to said output of the multiplexer is to change from said second to said first input clock signal.

7. Aclocksignal multiplexer substantially as hereinbefore described with reference to the accompanying drawings.