GB2181013A - Method for locking a clock signal to a video signal - Google Patents

Abstract

In a method for locking a clock signal C to a video signal 1 having time base errors, a ramp signal R is inserted into the horizontal frequency blanking interval, the time position of the ramp signal being determined by a horizontal sync pulse 2. With the inserted ramp signal, the video signal B is sampled in an analog/digital converter 6 with the clock signal C. A digital value, which is obtained by sampling the inserted ramp signal in the vicinity of a predetermined point thereof is used for adjusting the phase position of the clock signal generator 17. <IMAGE>

Description

SPECIFICATION Method for locking a clock signal to a video signal The invention relates to a method for locking a clock signal to a video signal.

In the analog/digital conversion of video signals, particularly colour television signals, it can be advantageous for a number of reasons to lock the clock signal with the video signal. For the correction of timebase errors, which occur on playing back video signals from a record support such as a magnetic tape, methods are known in which the video signals are written into a memory following analog/digital conversion. In such methods, both for the anaiog/digital conversion and for writing into the memory, use is made of a clock or timing signal suffering from the same timebase errors as the video signal.

According to the present invention there is provided a method for locking a clock signal to a video signal suffering from timebase errors, wherein a signal is inserted into the horizontal frequency blanking interval of the video signal, the inserted signal passing from a first value to a second value according to a predetermined function and having a time position determined by a horizontal frequency pulse, wherein the thus modified video signal is supplied to an analog/digital converter clocked by a clock signal, and wherein the time difference between a digital value obtained by sampling the inserted signal and a predetermined point of the function is used for adjusting the phase position of the clock signal.

The method according to the invention has the advantage that by using simple circuit means, particularly conventional components of digital circuit technology, it is possible to obtain a precise phase-based locking of the clock signal with the video signal and in particular the already analog/ digital conversion video signal.

The inventive method is not limited to the use of television signals and can also be used for other video signals.

An embodiment of the invention will now be described with reference to the accompanying drawings, wherein: FIG. 1 is a block circuit diagram of an arrangement for performing the inventive method, FIG. 2 are voltage-time diagrams of signals occurring in the arrangement of FIG. 1, and FIG. 3 are further voltage -- time diagrams with a modified time scale compared with FIG. 2.

At an input 1 an analog television signal (CCVS) is supplied from a record support such as a magnetic tape to the arrangement of FIG. 1. The horizontal frequency sync pulses are separated from the television signal in a sync pulse clipper 2 and supplied to the inputs of two pulse shapers 3 and 4.

The invention is not restricted to the use of sync pulses separated from the video signal. In many television installations there are horizontal frequency pulses which correlate with those in the video signals. Also there is described in our copending patent application (P/1155) a magnetic tape recorder in which the sync pulses are obtained with the aid of a second head switch and a second demodulator because the head switch provided for the video signal itself switches during horizontal frequency blanking intervals and therefore disturbs the sync pulses.

In response to each sync pulse from 2, a pulse shaper 3, which can advantageously be implemented by a phase-linear low-pass filter, shapes a signal R shown in the second line of FIG. 2.

The essential part of signal R is a gradually rising edge (ramp), which starts at the lower operating limit of an analog/digital converter 6 and rises symmetrically up to 50% of the operating limit and whose rise time is between one and two periods of the clock signal C which clocks the converter 6. The ramp is followed by a constant amplitude portion corresponding to the 50% level.

The ramp signal R is inserted into the horizontal frequency blanking intervals of the television signal CCVS by means of a switch 5. The square-wave pulse D in line 4 of FIG. 2 is derived by the pulse shaper 4 from the output signal of the sync pulse clipper 2 for controling the changeover switch 5. In known manner the pulse shaper 4 contains a monostable switching stage. Thus, when D is low the signal R is passed to the A/D converter 6, whereas when it is high the FBAS signal shown at the top of FIG. 2 is passed to the converter 6. The resulting signal B is shown in line 3 of FIG. 2 and is supplied to the analog/digital converter 6. The reason for the oscillations in B will be described later.

The analog/digital converter 6 is supplied with the clock signal C, whose frequency is at least twice as higH as the highest frequency occurring in the television signal supplied. In the present embodiment, the clock signal C has a frequency of 13.5 MHz. From the output of the analog/digital converter 6, the digital television signal is passed with an accuracy of 9 binary digits to point 7 for further processing.

The modified digital television signal B is also supplied with an accuracy of 9 binary digits (bit width of 9) to a register 8, which is also clocked with the clock signal C and is also controlled by the pulse D produced by pulse shaper 4.

On a larger scale than in FIG. 2, FIG. 3 shows in line E the ramp portion of R occurring in the digital television signal at the output of the converter 6, but for reasons of clarity it is represented as an analog signal. There are several pulses of the clock signal C during the pulse D. During the pulse D the sampled values from converter 6 are fed via the register 8 to a further register 10 and to a window comparator 11, whose output controls register 10. At its output, the known window comparator supplies a signal if the value of the input signal supplied to register 8 is between two values fed in at 12 and 13, e.g. 10% and 90% of the total amplitude of signal R.

Prior to the start of the ramp (i.e. prior to the pulse D), the sampled values in register 8 are very small, so that register 10 is not released by window comparator 11. The first value exceeding 10% of the total amplitude of signal R is written into the register 10. If subsequently there is a sampled value below 90%, the latter replaces the value previously written into the register 10. Since, as described hereinafter, the sampled value is used for regulating the phase position of the clock C during normal operation, i.e.

without any action of special disturbance variables, a phase position will be obtained such that signal R is sampled in the vicinity of point M.

With the aid of a programmable read-only memory (PROM) 15, in which is stored the shape of the ramp of signal R, the time difference between the sample point on the ramp R and the mid-point M of the ramp R is determined by using the contents of register 10 as an address to the PROM 15. The time difference is read out from PROM 15 as a digital signal and used for adjusting the phase position of clock signal C. This is diagrammatically shown in FIG. 1, wherein the clock signal C is the output voltage of an oscillator 16 which is passed across a controllable phase shifter 17, the value read out of PROM 15 being supplied across a digital/analog converter 18 to the control input of the phase shifter 17. However, other means are also possible for producing a phase-variable clock signal.

Thus, e.g. a start - stop oscillator can be started at a phase position which can be fixed by the output signal of PROM 15. Such a digital clock generator is described in our copending patent application (P/1 157).

In the correction of time and velocity errors, an evaluation of the colour sync signal takes place in the case of colour television signals. This can be provided for by superimposing a colour sync signal on the aforementioned constant amplitude portion ofthe inserted signal R following the ramp, as indicated in the third line of FIG. 2.

Claims (8)

1. A method for locking a clock signal to a video signal suffering from timebase errors, wherein a signal is inserted into the horizontal frequency blanking interval of the video signal, the inserted signal passing from a first value to a second value according to a predetermined function and having a time position determined by a horizontal frequency pulse, wherein the thus modified video signal is supplied to an analog/digital converter clocked by the clock signal, and wherein the time difference between a digital value obtained by sampling the inserted signal and a predetermined point of the function is used for adjusting the phase position of the clock signal.

2. A method according to claim 1, wherein the function is symmetrical and the predetermined point is the reversing point of the function.

3. A method according to claim 2, wherein the function is a cos2 function.

4. A method according to claim 1,2 or 3, wherein the function is stored in a programmable read-only memory (PROM), to which is supplied the said digital value as an address and from whose output is taken a digital signal which corresponds to the time difference between the clock signal and the predetermined point.

5. A method according to claim 4, wherein the inserted signal is produced by a circuit containing a phase-linear low-pass filter, and wherein an oscillator is provided whose phase is controllable, and wherein a control input of the oscillator is connected, optionally via a digital/analog converter, to the output of the programmable read-only memory.

6. A method according to any preceding claim, wherein the signal inserted in the video signal has a constant amplitude portion, preferably 50% of the video signal amplitude range, following the predetermined function.

7. A method according to claim 6, wherein a colour sync signal is superimposed on the constant amplitude portion.

8. A method for locking a clock signal to a video signal, substantially as described herein with reference to the accompanying drawings.