GB2173035A - Semiconductor devices - Google Patents

Abstract

A semiconductor device includes a heterojunction which is formed between a base region 4 of crystalline silicon, and an emitter region 1, 5 of semi-insulating polycrystalline silicon. In the case of a thyristor this gives improved operating characteristics, particularly in the case of a gate turn-off thyristor in which the dV/dt withstand characteristic is improved. Its use also improves current sharing between a number of separate emitter regions during turn-off. Emitter regions may include high resistivity fingers 5. In the case of a transistor, variation of the resistivity in a transverse direction of the emitter region by incorporation of high resistivity regions in the semi- insulating polycrystalline silicon gives improved performance. <IMAGE>

Description

SPECIFICATION Semiconductor devices This invention relates to semiconductor devices and seek to provide such devices having an emitter action with improved characteristics. The invention is particularly applicable to gate turn-off thyristors, although the invention is also beneficially applied to high frequency transistors and the like.

According to a first aspect of this invention, a thyristor includes a base region of crystalline silicon of a first conductivity type which forms a heterojunction with an emitter region which consists of semi-insulating polycrystalline silicon of a second conductivity type. Usually, but not essentially, the first conductivity type is p-type, and the second conductivity type is n-type.

According to a second aspect of this invention, a semiconductor device includes a base region of crystalline silicon which forms a heterojunction with emitter region which includes semi-insulating polycrystalline silicon and which has a resistivity which is greatest in a central region and which is lower at an outer region.

Preferably the semiconductor device is a gate turn-off thyristor in which the base region is p-type semiconductor and the emitter region is n-type semiconductor arranged as a plurality of elongate finger-like structures.

When a region of semi-insulating polycrystalline silicon doped with p-type or n-type impurities is contiguous with a region of conventional crystalline silicon, a heterojunction is formed, the electrical properties of which are dependent on the conductivity types of the materials and their electricity resistivities. In particular, the heterojunction results in a p-n junction having a greater band gap than would be the case for a junction betwen two contiguous regions of crystalline silicon, and this gives rise to properties which are very advantageous in a gate turn-off thyristor. Heterojunctions can be formed between two areas of crystalline silicon of different band gap but the interface recombination velocity is high, giving low gain to the npn or pnp transistor layers; with semi-insulating polycrystalline silicon the recombination is low.As is known, such a thyristor can, in contrast to the more traditional kind of thyristor, be rendered nonconductive by the application of a suitable gate signal, even though a substantial potential may exist between the cathode and the anode of the thyristor and whilst a substantial anode current is flowing.

To achieve good turn-on the emitter efficiency of a thyristor should be high: this is achieved by the use of a heterojunction with a wide energy gap in the emitter material and low interface recombination velocity. These conditions are met by the use of semi-insulating polycrystalline silicon as the emitter.

Another characteristic of a gate turn-off thyristor is what is usually termed the dV/dt withstand characteristic; this characteristic is a measure of the tendency of a thyristor to turn on again when the voltage across it begins to rise rapidly shortly after it has been turned off. It has been found that this particular characteristic is dependent on the resistance of the buried p-base layer, but the resistance of this p-base layer cannot be reduced to any significant extent in conventional gate turn-off thyristors as this would reduce the gain of the emitter junction and impair the turn-on performance of the device.The provision of a heterojunction by the use of a semi-insulating polycrystalline silicon emitter considerably increases the efficiency of the n-emitter carrier injection and this permits the resistance of the buried p-base to be somewhat less than would otherwise be the case, thereby enabling the reapplied dV/dt characteristic and the turn-off gain to the enhanced. A further and very important characteristic which stems from the use of the polycrystalline silicon is that the resistance of the n-type emitter can be varied in the tranverse dimensions of the structure so as to give a high resistance in the centre of the emitter, with a lower resistance material to either side of it, possibly surrounding it completely.

This provision very greatly improves the turn-off characteristic, as the higher resistivity of the SIPOS towards the centre of the emitter, which stems in pratice from a reduced impurity doping level, gives a much reduced gain in this region. Therefore, as the conducting plasma is squeezed towards this area during the turn-off phase of thyristor operation, the effective current gain will drop and the device will thereby turn off.

At turn-off the reduced gain in the centre of the emitter will increase the anode to cathode potential on each emitter region; in a typical gate turn-off thyristor the emitter is configured as a plurality of radiating fingers. If the current concentrated in any one finger, there is an additional increase in voltage, but this has the effect of reducing the current flow to that finger, thereby forcing current sharing between all fingers.

The invention is further described by way of example with reference to the accompanying drawings, in which: Figure 1 is a sectional view through a portion of a gate-turn-off thyristor, Figure 2 is an explanatory diagram, Figures 3 and 4 are sectional views of transistors, and Figures 5 and 6 are explanatory diagrams relating thereto.

Referring to Fig. 1, it shows a sectional view through part of one radial emitter finger of a gate turn-off thyristor. Only a small portion of such a thyristor is shown, but overall it is of circular plan having a plurality of radially disposed narrow fingers, each of which constitutes an elongate emitter and which is surrounded by gate electrode regions. Thus, in Fig. 1, the emitter region 1 is shown in transverse section across what is a long thin finger extending into the paper. The gate turnof thyristor itself is a four-layer device having a central n-type region 2 composed of doped crystalline silicon and which is bounded by a crystalline p-type anode region 3- and a crystalline p-base region 4. These three regions extend over the whole surface of the circular thyristor or constitute, in this example, a disc shaped body of silicon.On top of the p-base region are a plurality of the elongate finger emitters 1 as previously mentioned, and in this instance the emitter 1 is composed of ndoped semi-insulating polysilicon (n-SIPOS). In this instance the n-SIPOS is formed by doping the polycrystalline silicon with phosphorous.

The emitter 1 does not have a uniform resistivity across its transverse section but instead is provided with a small high resistivity finger 5 which is buried within the bulk of the n SIPOS regions and extends along the axis of the elongate finger so that it is in contact with the p-base region 4. This finger 5 is surrounded by n-SIPOS having# a somewhat lower resistivity. Although the ends of the fingers 5 are not visible in the drawing, these too are preferably bounded by regions of lower resistivity n-SIPOS.

To enable electrical connections to be made to the thyristor, the lower p-region 3 is provided with an anode contact 6, the p-base region 4 is provided with gate contacts 7 and the emitter 1 is provided with a cathode contact 8i these contacts being a conventional thin metalisation such as aluminium.

Fig. 2 is a diagramatic representation of the way in which the phosphoros dopant concentration of the n-SIPOS varies across the transverse dimension of the emitter finger 1.

The bulk of the emitter region has a concentraction corresponding to the level-C1 whereas the central region 5 has a very much lower concentration C2 which gives rise to a correspondingly higher resistivity. During normal operation, the gate turn-off thyristor conducts a very high current between the anode and cathode electrodes 7 and 8. Upon application of a suitable gate signal to the electrodes 8 this current is extiguished and the current turn-off is by a mechanism in which the conducting plasma is pinched towards the centre of the emitter finger 1 by reverse biasing the gate. As the n-SIPOS has reduced doping level of phosphorous towards the centre region there is therefore a much reduced gain in this region. Therefore, as the conducting plasma is squeezed or pinched towards this area the current gain will drop-and the thyristor will thereby turn-off and become non-conducting.If the current concentrates in any one finger, there is an additional increase in voltage, but this has the effect of reducing the current flow to that finger, thereby forcing current sharing between all fingers.

The n-SIPOS emitter region 1 can be formed by deposition from a vapour onto the body of the thyristor, the body consisting of layers 2, 3 and 4 which themselves are formed in the conventional manner. Thus, a uniform deposition of high resistivity n-SIPOS is initially formed on the upper surface of the p-base layer 4, the resistivity being adjusted by the concentration of the phosphorus in the SIPOS which is deposited. Alternatively, phosphorous may be ion implanted after deposition. This uniform layer is then partially removed by a selectively etch to (using a suitable etch resistance mask) leave the array of radially extending fingers having the required shape and size, one only of which is illustrated in section view as finger 5- in Fig. 1.Subsequently, a deposition of lower resistivity n-SIPOS is formed over the whole of the upper surface of the thyristor, and this is followed by a similar etching process to leave the fingers 1. In this case, the thickness of the second deposition is greater than that of the first so as to completely cover the low resistivity fingers.

The provision of the lateral variation of resistivity of the SIPOS is usefully applicable also to transistors, it being useful to reduce the incidence of what is termed, second breakdown.

Fig. 3 shows a sectional view of part of a transistor to which the invention is applied.

The transistor consists of a p-base 10, an ncollector 11, and an n-SIPOS emitter 12. Also shown in Fig. 3 are base and emitter electrodes 13 and 14 respectively. The emitter does not have a uniform rsistance, but instead it varies across the transverse dimension of the emitter. It includes a central region 15 of higher resistivity n-SIPOS which is flanked by regions 16 of lower resistivity. The outer-ends of the emitter also include regions 17 having higher restivity. This variation in resistivity is achieved- by varying the n-dopant concentration, and this variation is illustrated in -Fig. 4, which is analogous to the variation of phosphorous concentration shown in Fig. 2, and similar fabrication techniques can be used to achieve it. In Fig. 3, the central region 15 of higher resistivity prevents current crowding during turn-off while the additional edge regions 17 help to prevent current crowding during the turn-on and during on-state operation. Forward bias safe operating area is improved and turn-on efficiency is improved due to reduction in emitter current crowding around emitter periphery.

A modification is shown in Fig. 4 in which a transistor is provided in which the shape of the edge region 18 is rather different to Fig.

3, other parts being similar and carrying corresponding reference numerals. This tapering re sistance variation, which corresponds with the variation in dopant concentration shown in Fig.

6, results in a structure with a more efficient operation, but at the expense of more complex processing. The same general benefits are obtained as for the structure shown in Figs. 3 and 5, but the graded doping extends the range of current densities over which these benefits apply.

Claims (10)

1. A thyristor including a base region of crystalline silicon which forms a heterojunction with an emitter region which consists of semiinsulating polycrystalline silicon.

2. A semi-conductor device including a base region of crystalline silicon which forms a heterojunction with an emitter region which includes semi-insulating polycrystalline silicon and which has a resistivity which is greatest in a central region and which is lower at an outer region.

3. A device as claimed in claim 1 and wherein the semiconductor device is a gate turn-off thyristor in which the base region is p-type semiconductor, and the emitter region is n-type semiconductor arranged as a plurality of elongate finger-like structures.

4. A device as claimed in claim 3 and wherein the thyristor is a substantially circular body of silicon having the finger-like structures disposed radially at one surface thereof, with gate electrodes being positioned between the fingers.

5. A device as claimed in claim 3 or 4 and wherein each finger-like structure consists of an internal finger of n-SIPOS having a relatively high resistivity, and which is in contact with the said base region, the finger having a region of n-SIPOS of lower resistivity on both sides of it and in contact with said base region.

6. A device as claimed in claim 5 and wherein each finger is surrounded by regions of n-SIPOS of lower resistivity.

7. A device as claimed in claim 2 and wherein the semiconductor device is a transistor, and wherein further high resistivity regions are provided outside of said outer region so as to be located at the outer edge of the emitter region.

8. A device as claimed in claim 7 and wherein the further high resistivity regions have a tapered resistivity variation in whih the resistivity decreases towards said central region.

9. A gate turn-off thyristor substantially as illustrated in and described with reference to Figs. 1 and 2 of the accompanying drawings.

10. A transistor substantially as illustrated in and described with reference to Figs. 3 and 5 or Figs. 4 and 6 of the accompanying drawings.