GB2169133A - Integrated photoreceiver circuit - Google Patents

Abstract

A photoreceiver, e.g. for an optical communications system, comprises a photodetector (11), amplifier (12) and buffer (13) formed by selective Si implantation into a semi-insulating GaAs substrate. <IMAGE>

Description

SPECIFICATION Photoreceiver circuit This invention relates to photoreceiver circuits for use e.g. in optical communication systems.

At present photoreceivers used in optical communication systems are hybrid devices, constructed with discrete detectors and amplifiers. An integrated device can overcome the problems of limited frequency and noise performance due to parasitic elements, large size, and lack of reproducibility, which are inherent in these hybrid receivers. The proven speed performance of GaAs ICs and the efficient optical absorption property of the material at short wavelengths render GaAs well suited for the fabrication of high speed, sensitive integrated photoreceivers for operation in the 0.85 micron wavelength region. Several examples of such circuits have recently been reported. However, these reported designs have required epitaxial growth of multiple-layers on the SI substrate to form the photodetector.The need for this extra device technology and the non-planar nature of the detector itself, inevitably complicate the processing method and reduce device yield.

The object of the present invention is to minimise or to overcome this disadvantage.

According to the invention there is provided an integrated photoreceiver device, including a photodetector, and an amplifier coupled to the photodetector, wherein said detector and amplifier are provided by selective silicon ion implants into the substrate.

Embodiments of the invention will now be described with reference to the accompanying drawings in which: Figure 1 is a schematic diagram of the photoreceiver; Figure 2 shows typical bandwidth characteristics for the receiver of Fig. 1; Figure 3 shows one form of transimpedance amplifier circuit, Figure 4 shows an alternative cascade amplifier circuit, and Figures 5 to 12 illustrate a fabrication sequence of the photoreceiver of Fig. 1.

Referring to Fig. 1, the integrated photoreceiver comprises a planar photodetector 11 and a wideband amplifier 12 which amplifier converts the detector current into voltage across a buffered stage 13 capable of driving a wide range of load impedance e.g. a direct 50 ohm load or a common source stage with 50 ohm drain load. The structure is formed on a common compound semiconductor chip, e.g. gallium arsenide. The detector structure comprises two interdigitated electrodes 21, 22 formed directly on the semi-insulating substrate, to which external bias is applied. Typical detector size is 100 micron with 1.8 micron electrode width and 3 micron electrode separation.

Fig. 2 shows both the computer predicted and measured dependence of bandwidth on feedback resistance value. With 2.5 kilohms feedback resistance, receiver bandwidths of 2.3 and 1.1 GHz are predicted for the cascode and simple transimpedance type circuits respectively.

Fig. 3 shows the circuit diagram of a transimpedance amplifier and its associated output buffer. Signals from the photodetector are fed to the gate of transistor TR31, the load of which comprises a gate-source shorted transistor TR32. TR33 and TR36 form a source-follower stage to provide negative feedback to the gate of TR31 via resistor R31, and to drive the output buffer. Diodes D1 to D4 shift the dc voltage at the drain of TR31 down to near zero at the buffer output. The output from TR31 is further amplified by transistor TR33 and fed via level shifting diodes D1 to D4 to the output buffer comprising transistors TR34 and TR35. Feedback to the amplifier signal is provided via resistor R31. Transistor TR36 biases the output buffer.

Typically the feedback resistor is 2 to 3 kn.

An alternative cascode amplifier circuit is shown in Fig. 4. in this arrangement the photodetector input is first amplified by transistor TR41 and the amplified signal is fed to a low input impedance grounded gate transistor TR42. The use of this low input impedance second stage reduces the Miller effect capacitance appearing at the amplifier input.

The receiver bandwidth may be approximated by the relationship:

where A#=amplifier voltage gain RF =feedback resistance Cd detector capacitance, and Q =amplifier input capacitance For the amplifier circuits of Figs. 3 and 4, the dependence of bandwidth on the feedback resistance value is shown in Fig. 2. With 2.5 kn feedback resistance, receiver bandwidths of 2.3 and 1.1 GHz are predicted for the cascade and simple transimpedance type devices respec tively.

The photoreceiver is fabricated by selective implantation of (Si29)+ ions into LEC grown undoped SI substrates to form the circuit components. Advantageously the metallization material for the interdigitated detector is identical to that of the MESFET gate and first level metallization, i.e. Cr-Au (3000 A), so that these can be fabricated in a single lift-off step. This permits the fabrication of the photoreceiver devices without any modification to existing Gatts IC process using selective ion implantation. Typically the MESFETs are standard 1 micron gate length depletion-mode devices with implanted n+ drain and source contacts to minimize series resistance. A pinch-off voltage of -1 volt was chosen. Very low series resistance level-shifting diodes may be realized using an interdigitated design and a deep n+ implant to form the cathode.

A typical fabrication sequence for the photodetector of Fig. 1 is illustrated in Figs. 5 to 12.

For clarity only one transistor and one diode are shown whereas in practice all the components of the circuit of Fig. 3 or Fig. 4 would be fabricated simultaneously. A semi-insulating gallium arsenide substrate 51 (Fig. 5) is provided with a titanium layer 52 which in turn is coated with a photoresist mask 53 having an opening 54. The titanium layer 52 and the underlying gallium arsenide 51 are etched through this opening to provide a recess 55 (Fig. 6) in the gallium arsenide surface. The recess 55 provides a registration mark for subsequent processing. The mask 53 is removed and a second mask 56 (Fig. 7) is applied, said mask having an opening 57 in register with the channel region of an FET that is to be formed. The structure is implanted with silicon ions through the mask opening 57 to define the channel region 58.The gate region of the FET is next masked with photoresist 59 (Fig. 8) and n' contact regions 60, e.g. of phosphorus, are implanted. These contacts extend below the channel region. The mask 56, 59 is removed and a further mask 61 (Fig. 9) is applied. This mask has an opening 62 adjacent the FET and through which a deep n' implant 63 is applied. This implant is used to form level shifting diodes. The mask 61 and the titanium layer 52 are removed and the structure is annealed to repair the implant damage.

Ohmic contacts 64, 65 (Fig. 10) are applied respectively to the contact regions 60 and to the deep implant 63. A further (Shottky) metallisation is then applied (Fig. 11) to form a gate electrode 66, the interdigitated detector structure 67 and a diode anode electrode 68. The structure is covered with a first dielectric layer 69 having openings 70, 71 to expose the detector 67 and the FET contacts respectively. A metal interconnect pattern 72 (Fig. 12) is applied to provide electrical connection to the ohmic contacts and an interconnect (not shown) between one photodiode electrode and the transistor gate. The assembly is coated with a further dielectric passivation layer 73 to form the finished device.

The photoreceiver devices described herein may be employed in optical communications systems.

Claims (10)

1. An integrated photoreceiver device, including a photodetector, and an amplifier coupled to the photodetector, wherein said detector and amplifier are provided by selective silicon ion implants into a common semi-insulating gallium arsenide substrate.

2. A photoreceiver device as claimed in claim 1, wherein the photodetector comprises two interdigitated electrodes disposed on the substrate and each forming a Schottky barrier therewith.

3. A photoreceiver device as claimed in claim 2, wherein said electrodes comprise a chromium/gold alloy.

4. A photoreceiver device as claimed in claim 1, 2 or 3, wherein said amplifier is a transipe dence amplifier.

5. A photoreceiver device as claimed in claim 1, 2 or 3, wherein said amplifier is a cascode amplifier.

6. A photoreceiver device substantially as described herein with reference to Figs. 1, 2 and 3 or to Figs. 1, 2 and 4 of the accompanying drawings.

7. A method of fabricating an integrated photoreceiver device on a semi-insulating gallium arsenide substrate, the method including implanting said substrate with an n-type implanting to define a field effect transistor and an adjacent diode, forming a first metallisation providing an ohmic contact to the substrate to define the drain and source electrodes of the transistor and the diode cathode, and providing a second metallisation to define a pair of interdigitated electrodes forming a photodetector and todefine the transistor drain and diode anode electrodes, said second metallisation forming a Schottky barrier with the substrate.

8. A method of fabricating a photoreceiver device substantially as described herein with reference to and as shownin Figs. 5 to 12 of the accompanying drawings.

9. A photoreceiver device made by the method of claim 7 or 8.

10. A communications system provided with one or more photoreceivers as claimed in any one of claims 1 to 6 or as claimed in claim 9.