GB2166571A - Data processing system - Google Patents

Abstract

A system 8 for data storage and retrieval comprises memory means 9c having a first storage means containing instructions for use in an instruction means to direct operation of the data processing system and a second storage means provided with, in use, instructions for use in a common instruction means, the command instruction means controlling the data processing system under direction of the instruction means, the instruction means generating and assigning four pointers for each of the instructions in the command instructions means, wherein the pointers (16, 18, 20, 22, Fig. 3) respectively represent the locations of a succeeding instruction which is nested in the current instruction, a succeeding instruction which is at a level of nesting the same as and within a nest of instructions the same as the current instruction, a preceding instruction which nests the current instruction, and a preceding instruction which is at a level of nesting the same as and within a nest of instruction the same as the current instruction, the system being manually controllable by a manual control means and/or automatically controllable by an automatic control means. <IMAGE>

Description

SPECIFICATION Data processing systems The present invention relates to a data processing system particularly envisaged for use in storage and retrieval of data from a store of data such as a data base.

Consequent to the development of computers with large memory capability and fast operation more and more information is stored in data bases in data processing systems.

However, the effectiveness of the data bases is limited by the ability of a user, either skilled or unskilled, to store and/or retrieve data from the data base.

In general, data processing systems and the like may be made to operate, under a suitable control means, in two modes.

In a first mode of operation the data processing system is made to operate automatically. Under automatic operation the control means may direct the data processing system to operate forwardly in accordance with a set of command instructions and at least partially backwardly.

In a second mode of operation the data processing system is made to operate manually. Under manual operation a user may, with the control means, direct the data processing system to operate forwardly or backwardly in accordance with a set of command instructions. However, under manual control the user may not easily direct the data processing system out of a recursive command instruction.

Under such circumstances the user must step through every term of the recursive control instructions or direct the data processing system out of the command of the control means. For, example, where a recursive command instruction specifies, say, 1000 recursions the user, under the manual control mode, would have to traverse all 1000 recursions in passing through the command instruction. That is, to pass through a recursive command instruction the user must direct control into the command, through all of its recursions and out of the command at the completion of a last one of the recursions.

The present invention provides a data processing system which is controllable forwardly and backwardly in accordance with a command instruction means, under direction of an instruction means, and into and out of recursive command instructions of the command instruction means.

In accordance with one aspect of the present invention there is provided a data processing system for data storage and data retrieval comprising a central processing unit, a memory means, an input/output means and an operating system linked by a system bus under control of a bus controller, the memory means having a first storage means containing a plurality of instructions for use in an instruction means to direct operation of the data processing system and a second storage means provided with, in use, a plurality of instructions for use in a command instruction means, the operating system providing interface for the instruction means and the command instruction means to the remainder of the data processing system, the command instruction means controlling the data processing system under direction of the instruction means, the instruction means generating and assigning pointers for each of the instructions in command instruction means, the pointers representative of the location of preceding and succeeding instructions relative to a current instruction, wherein the pointers comprise a first pointer representative of the location of a succeeding instruction which is nested in the current instruction, a second pointer representative of the location of a succeeding instruction which is at a level of nesting the same as and within a nest of instructions the same as the current instruction, a third pointer representative of the location of a preceding instruction which nests the current instruction and a fourth pointer representative of the location of a preceding instruction which is at a level of nesting the same as and within a nest of instruction the same as the current instruction, the system being manually controllable by a manual control means and/or automatically controllable by an automatic control means.

In accordance with a further aspect of the present invention there is provided a process for the control of a data processing system in relation to data storage and data retrieval, comprising accepting a plurality of command instructions for a command instruction means from an input/output device and storing them in a second storage means under direction of an instruction means having a plurality of instructions stored in a first storage means via a system bus under control of a bus controller and interfaced by an operating system, generating and assigning pointers to each instruction of the command instruction means, the pointers representative of the location of preceding and succeeding instructions relative to a current instruction, wherein the pointers comprise a first pointer representative of the location of a succeeding instruction which is nested in the command instruction, a second pointer representative of the location of a succeeding instruction which is at a level of nesting the same as and within a nest of instructions the same as the current instruction, a third pointer representative of the location of a preceding instruction which nests the current instruction and a fourth pointer representative of the location of a preceding instruction which is at a level of nesting the same as and within a nest of instructions the same as the current instruction, and storing the pointers in an array, the process being manually controllable by a manual control means and/or auto matically controllable by an automatic control means to follow a desired direction of execution.

The present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a schematic representation of apparatus which incorporates the data processing system of the present invention; Figure 2 is a table to textual command instructions; Figure 3 is a table of pointers corresponding to the table of Figure 2; Figure 4 is a flow chart of manual control for the data processing system of the present invention; and Figure 5 is a flow chart of automatic control for the data processing system of the present invention.

In Figure 1 there is shown an apparatus 8 comprising the data processing system of the present invention and suitable to incorporate the process of the present invention.

The apparatus 8 comprises a central processor unit (CPU) 9a in electrical communication with a system bus 9b. The bus 9b provides further electrical communication between a memory means 9c, an input/output (I/O) means 9d, a bus controller 9e and an operating system 9f.

The memory means 9c comprises a first storage means and a second storage means, each having a plurality of instructions temporarily or permanently stored therein.

The instructions in the first storage means and the second storage means are respectively for use in an instruction means and a command instruction means of the data processing system of the present invention. The command instruction means is provided to control the data processing system under direction of the instruction means.

The nature of the command instruction means and its control over the data processing system may be altered by a user of the data processing system by altering the instructions in the second storage means.

The instructions in the first storage means are instructions corresponding to commands used to effect a manual process of control (shown in Figure 4) and an automatic process of control (shown in Figure 5) for the data processing system under direction of the instruction means.

The second storage means comprises a plurality of instructions for use in the command instruction means which relate to process commands that are independent of and directed by the apparatus and process of the present invention.

The memory means 9c also comprises a third storage means comprising data to be ac cessed and processed. The data relate to data upon which the process of the present invention may operate, as described hereinafter. For example, the stores of data may relate to data in a data base.

The plurality of command instructions in the second storage means relate to a method of implementation of the apparatus and process of the present invention desired by the user to access and/or process data contained in the memory means 9c, such as data in the third storage means. The instruction means and the command instruction means is interfaced by the operating system 9f to the remainder of the apparatus 8.

The I/O means 9d comprises devices to allow input and output instructions and data into and out of the apparatus 8. More specifically, the I/O means 9d may comprise video display units, printers, automatic mailing systems, disk drive assemblies etc. (not shown).

Data and command instructions are entered by a user into the I/O means 9d and directed to the remainder of the apparatus 8.

The passage of data and instruction commands is directed and controlled about the apparatus 8 along the bus 9b by the bus controller 9e.

The bus controller 9e may, for example, give exlusive use of the bus 9b to the I/O means 9d. Such exclusive use may be granted to a disk drive assembly of the I/O means 9d to allow it to store and/or read data in the memory means 9c under action of a direct memory access (DMA) controller (not shown).

The operating system 9f of the apparatus 8 is also required to interface the process of the present invention with the remainder of the apparatus 8. The operating system 9f further provides instruction and data format alterations suitable to allow the instructions of the memory means 9c to be applicable to a variety of CPU's 9a, I/O means 9d and bus controllers 9e.

The apparatus and process of the present invention is particularly intended for use with the AT and T Bell Laboratories developed UNIX operating system although it may be adapted to use other operating systems.

In Figure 2 there is shown, as an example, a table of textual instructions 10 comprising a plurality of lines of text 12. The lines of text 12 are used to allow a user of the apparatus 8 to tailor the control of the command instruction means to suit his/her desired application.

The lines of text 12 are conveniently referred to as verb lines 12.

The lines of text 12 are, in use, text instructions for use in the command instruction means and may include nested instructions which are to be executed in a recursive manner. A nested instruction is an instruction whose execution is dependent upon a preceding instruction which nests it. The nesting instruction is executed once the nested instruction is executed through all of its recursions.

The nested recursive instruction is so exe cuted between each execution of the nesting recursive instructions until the nesting recursive instruction is also completely executed.

For the purpose of the present example a nested verb line 12 is a verb line 12 which appears one or more spaces further from the margin than a preceding verb line 12. Thus, a verb line 12 may be converted from a nested to an un-nested verb line 12, by a user of the apparatus 8, by adding or removing one or more spaces at the beginning of the verb line 12.

The table of textual instructions 10 is created by a user of the data processing system of the present invention. The lines of text 12 are entered into the apparatus via a video display unit of the I/O means 9d, for example. In Figure 2 the verb lines 12 are shown on a screen 13a of a video display unit and each verb line 12 has a verb line number 13b. Each verb line number 13b is a pointer to each corresponding verb line 12.

The verb lines 12 are transferred from the I/O means 9d to the memory means 9c along the bus 9b under control of the bus controller 9e and may be subject to demands of the remainder of the apparatus 8.

For the table of instructions 10 in Figure 2 nested verb lines 12 are executed to completion before non-nested verb lines 12. For example, the verblines Nos. 3, 4 and 5 are nested in the verbline 2 and each is executed to completion every time the verbline No. 2 is executed.

Execution of nested verblines 12 in the data processing system of the present invention may be compared to nested DO loops in the FORTRAN IV programming language. In such a comparison each verbline 12 may be considered as a DO loop. Also each verbline 12 may be considered as a micro instruction comprising definitions as to its recursion. Preferably, the verblines 12 are formed of components as described and claimed in our cofiled Patent Application described hereinafter.

In Figure 3 there is shown a table of pointers conveniently referred to as a token table 14. The token table 14 comprises a plurality of pointers which indicate the relative location of a current textual instruction or verbline 12 with preceding and succeeding textual instructions or verblines t2.

The pointers are defined for each command instruction line which is written by the user and stored in the memory means 9c. The pointers are created by the instruction means and correspond to command components, connection components and parameter components of the command instructions as described and claimed in our co-filed Patent Application. The pointers also provide a representation of the characteristics of the connection components and the parameter components of the command instruction.

The pointers comprise a first pointer 16 conveniently referred to as an IN pointer 16.

The IN pointer 16 provides a representation of the location of a succeeding verbline 12 which is nested in the current verbline 12.

For example, in Figure 2 the verbline No. 1 has nested in it the verbline No. 2. In the corresponding token table 14 of Figure 3 the verbline No. 1 has an IN pointer 16 equated to 2. The IN pointer 16 exists as a data entry in the memory means 9c, and is generated by the instruction means. The IN pointer 16 provides a representation to the CPU 9a, in use, of a path to proceed to verbline No. 2 from verbline No. 1.

Similarly, the verbline No. 2 has nested in it the verblines Nos. 3, 4 and 5. In the token table 14 corresponding to the table of textual instructions 10 (Figure 2) the verbline No. 2 has an IN pointer 16 equated to 3. A corresponding data entry is created by the instruction means and stored in the memory means 9c. The IN pointer provides a representation of a path of execution for the CPU 9a to verbline No. 3 from the verbline No. 2.

Thus, the IN pointer 16 directs the command instruction means from a current verbline 12 to a nested verbline 12. The pointers also comprise a second pointer 18 conveniently referred to as a FORWARD pointer 18.

The FORWARD pointer 18 provides a representation of the location of a succeeding verbline 12 which is at a level of nesting the same as and within a nest of verblines 12 the same as the current verbline 12.

For example, the verbline No. 3 is followed by the verbline No. 4 which is a non-nested verbline 12.

In the token table 14 the verbline No. 3 has a FORWARD pointer 18 equated to 4. The FORWARD pointer 18 provides a representation to the CPU 9a of a path to proceed from the verbline No. 3 to the verbline No. 4. Corresponding data entry is created by the instruction means and is stored in the memory means 9c.

Since the verbline No. 4 is not nested in the verbline No. 3 there is no IN pointer 16 for the verbline No. 3. In such cases the relevant pointer and data entry in the second storage means is set to zero or some other inactive value such as, for example~1.

Similarly, the verbline No. 4 is immediately followed by the verbline No. 5 which is a nonnested verbline 12. The verbline No. 4 has a FORWARD pointer 18 equated to 5 and an IN pointer 16 equated to zero. The FORWARD pointer 18 provides a representation of a path of execution of the CPU 9a to verbline No. 5 from verbline No. 4.

The equation of the IN pointer 16, for verbline No. 4, to zero indicates that there is no verbline 12 nested in verbline No. 4. That is, there is no IN pointer for verbline No. 4. A similar case exists for verblines Nos. 5, 6 and 7 of the example of Figure 2.

The pointers further comprise a third pointer 20 conveniently referred to as an OUT pointer 20. The OUT pointer 20 provides a representation of the location of a preceding verbline 12 which nests the current verbline 12.

For example, in Figure 2, the verbline no. 2 is nested by the verbline No. 1. In the corresponding token table 14 the verbline No. 2 has an OUT pointer 20 equated to 1. A corresponding data entry is created by the instruction means and stored in the memory means 9c. The OUT pointer 20 provides a representation of a path to the CPU 9a to proceed from verbline No. 2 to verbline No. 1.

Similarly, the verblines Nos. 3, 4 and 5 have OUT pointers 20 equated to 2 indicating a path from each of the verblines Nos. 3, 4 and 5 to verbline No. 2.

The verblines Nos. 1 and 7 of the example of Figure 2 have no nesting verblines and thus have OUT pointers 20 equated to an inactive value, such as zero, with corresponding data entries generated in the memory means 9c.

The pointers also comprise a fourth pointer conveniently referred to as a BACK pointer 22. The BACK pointer 22 provides a representation of the location of a preceding verbline 12 which is at a level of nesting the same as and within a nest of verblines 12 the same as the current verbline 12.

For example, the verbline No. 6 is preceded by the non-nesting verbline No. 2 and has in the token table 14, a BACK pointer 22 equated to 2. The BACK pointer 22 has a corresponding data entry generated by the instruction means and stored in the memory means 9c.

The BACK pointer 22 indicates a path from verbline No. 6 to verbline No. 2 for the apparatus 8 under control of the command instruction means.

Similarly, verbline No. 7 has a BACK pointer 22 equated to 1 indicating a path to verbline No. 1 from verbline No. 7. The verblines Nos.

1, 2 and 3 of the example of Figure 2, have no preceding non-nesting verblines and so their corresponding BACK pointers 22 are set to an inactive value, such as zero.

The pointers 16, 18, 20 and 22 are used in a a manual process in accordance with the present invention and the pointers 16, 18 and 20 are used in an automatic process in accordance with the present invention to control the operation of the apparatus 8 in accordance with the command instruction means under direction of the instruction means.

Each of the pointers has associated with it an initiating command. The IN pointer 16 is associated with an IN command, the FOR WARD pointer 18 a FORWARD command the OUT pointer 20 an OUT command and the BACK pointer 22 a BACK command.

The initiating commands are, in use, entered by a user of the apparatus 8 in the I/O means 9d, interpreted by the operating system 9f and directed by the CPU 9a and the instruction means to follow execution in a path presented by a relevant pointer 16, 18, 20 or 22 for a current verbline 12 of the command instruction means.

For example, in the manual process, an IN command given at a verbline No. 2 of the table of text instructions 10, shown in Figure 2, would direct the CPU 9a, via the relevant IN pointer 16 (equated to 3), to verbline No.

3. It is envisaged that the initiating commands could be given by any letter keys or control functions of a keyboard of the l/O means 9d or via a joystick control or light pen or the like.

The manual process follows an operational sequence shown in the flow chart of Figure 4 directed by the instruction means. The flow chart comprises operational blocks having reference numerals 30 to 68. The CPU 9a is maintained in an idle state of operation in the operational block 30. In this state the CPU 9a is left free to service requests from peripheral devices, such as the I/O means 9d. When an initiating command is detected by the CPU 9a from a keyboard of the I/O means 9d the operating system 9f interprets the initiating command and presents it to the instruction means. The instruction means directs the CPU 9a to perform checks to determine which of the abovementioned commands was given.

The blocks 32 to 38 direct the CPU 9a to make a test for an IN command, a FORWARD command, an OUT command and a BACK command respectively.

The test comprises comparing the given initiating command to the four initiating commands. In the blocks 32, 34, 36 and 38 the given initiating command is compared to the IN command, the FORWARD command, the OUT command and the BACK command respectively and in such order. If in the block 32 the CPU 9a determines that the given initiating command is not an IN command control is passed to the block 34. Similarly in the block 34 the CPU 9a determines whether or not the given initiating command is a FOR WARD command and if not passes control of the data processing system to the block 36 and similarly to the block 38.

The test is carried out only until the given instructing command is recognised. For example, if an IN command was given the test of block 32 would recognise the command and no further command recognition tests would be made.

The recognised command is checked for validity before the command is executed. As described hereinabove it is not valid to perform some of the commands on certain verblines 12 in the text table 10. The blocks 40 to 46, respectively corresponding to the blocks 32 to 38, check that the relevant pointer 16, 18, 20 or 22 of the token table 14 represents a valid pointer. Conveniently, an in valid pointer is equated to zero (or~1) and the blocks 40 to 46 test to establish if the recognised command is associated with a pointer equated to a non zero positive number (or a negative number). The recognised command may only be executed if the command is a valid command for the verbline 12 at which the instructing command is given. That is, where no valid pointer exists for the given command at the current verbline 12 command is not executed.

For example, an IN command given at verbline No. 4 of the table of textual instructions 10 of Figure 2 will be recognised as such a command but will not be executed since the IN pointer 16 is equated to zero.

Where the relevant pointer is a valid pointer the blocks 48 to 54 respectively, direct the instruction means to direct the CPU 9a to execute the command. The block 48 directs the CPU 9a via the operating system 9f to execute the IN command, and similarly, the blocks 50, 52 and 54 direct the CPU 9a to execute the FORWARD, OUT and BACK commands respectively. In executing a command the CPU 9a is directed by the manual process of the present invention to execute the table of instructions 10 stored in the second storage means in accordance with the command instruction means directed by the pointers 16, 18, 20 and 22 of the token table 14. At completion of execution of a given command by one of the blocks 48 to 54 control is passed back to the block 30 to await further initiating commands from the user of the apparatus 8.

Where no command is recognised or no valid command is received the process directs control to the block 56. The block 56 is provided to indicate that an error has occurred.

Conveniently, the block 56 directs an error message to be generated to indicate the nature of the error. The error message is transferred to the I/O means 9d via the bus 9b under direction of the CPU 9a and the bus controller 9e and may be displayed on a video display unit or printer, where appropriate.

Then control is passed back to the block 30 to await further initiating commands.

Also, in Figure 4, there is shown a sub-flow chart connected into the main flow chart by dashed lines. The sub-flow chart provides a control to direct execution of the data processing system to proceed forwardly or backwardly n terms from a current verbline 12. That is, where the current verbline 12 is a recursive verbline 12, similar to a FORTRAN IV DO loop for example, commands may be given to direct the CPU 9a to proceed forwardly or backwardly as the case may be, through the terms of the recursive verbline 12.

To proceed through the terms of a recursive verbline 12 that relates to data in a data file in the third storage means of the memory means the CPU 9a increments or decrements a memory address pointing to memory locations in the third storage means.

In such manner the CPU 9a can be directed forwardly or backwardly a number of records of data in a data file. Such control allows a user to browse through the data records of a data file in accordance with the control of the command instruction means and subject to the manual control process.

Commands, conveniently referred to as FOR WARD n RECORDS and BACKWARD n RE CORDS may be given by an operator via the l/O means 9d to direct the CPU 9a to proceed through the terms of a recursive verbline 12 to browse through the data records of a data file. The commands cause the CPU 9a to leave the the control of block 30 and proceed through the recognition tests. The blocks 58 and 60 provide further recognition tests and will recognise a FORWARD n RECORDS and a BACKWARD n RECORDS initiating command, respectively.

The blocks 62 and 64 test whether the initiating command is valid for the current verbline 12.

The blocks 62 and 64 determine an initiating command invalid if it requests records that do not exist in the records accessed by the current verbline 12 or, if the current verbline 12 is not of a recursive type.

For example, a BACK n RECORDS command where the current verbline 12 points to a first record of a data file in the third storage means will not be allowed.

Where the command is valid, blocks 66 and 68 direct the CPU 9a via the operating system 9f to proceed forwardly or backwardly n records through the records accessed by the current verbline 12.

Once the nth record is accessed, control is passed back to the block 30.

If no command is recognised or tested to be valid then control proceeds to the error block 56 and then to the command entry block 30, as described hereinabove.

Under manual control there are, as described hereinabove, six types of command to effect 6 modes of process control which is hereinafter referred to as hexa-directional control.

The automatic process follows an operational sequence shown in the flow chart of Figure 5. The flow chart comprises operational blocks 80 to 96.

The automatic process follows a path of control defined by command instruction means and described by the pointers 16, 18, 20 and 22 of the token table 14 contained as data entries in the memory means 9c and subject to the direction of the instruction means.

Once execution of the table of instructions 10 has been directed by the operator the CPU 9a comes under the control of the block 80 and is directed by the instruction means. The block 80 directs the CPU 9a to execute the current verbline 12 only once.

The execution proceeds to a first test stage at the block 82. The first stage comprises testing if there are any data records remaining to be considered in a file of the third storage means at which the current verbline 12 is operating. A flag is used to represent if there are records remaining to be considered by the current verbline 12. The flag is conveniently referred to as an end of data EOD flag.

Conceivably, whilst data remains to be considered the EOD flag is not set and when no data remains to be considered the EOD flag is set.

If there is more data to be considered by the current verbline 12 then the CPU 9a is directed by the block 80 to perform the verbline 12 once more.

The verbline 12 is performed recursively until the end of the data (EOD) is detected and the EOD flag is set. Then block 82 directs the CPU 9a to test the validity of the pointers 16, 18 and 20 to determine the future course of the process of the present invention as controlled by the command instruction means.

In the current embodiment of the present invention it is desired to perform nested verblines 12 in a manner similar to that of nested DO loops in FORTRAN IV. To achieve this the block 84 directs the CPU 9a via the operating system 9f to test the IN pointer 16, corresponding to the current verbline 12, first. So, if a nested verbline 12 exists, it is to be performed to its entirety before the next term of the current verbline 12 is executed. For example, verbline No. 2 of the text table 10 of Figure 2.

Furthermore, a group of nested verblines 12 are to be treated in a similar manner to a singular nested verbline 12. If no valid IN pointer 16 exists the block 86 directs the instruction means to direct the CPU 9a, via the operating system 9f, to test the FORWARD pointer 18 for the current verbline 12.

Similarly, the block 88 directs the CPU 9a via the operating system 9f to test the validity of the OUT pointer 20 if there is no valid IN or FORWARD pointers 16 or 18 for the current verbline 12. As can be seen in the example of Figure 2, an OUT pointer 20 is required to direct execution out of a nested set of verblines 12.

The blocks 90 to 94 direct the CPU 9a to perform the command corresponding to a valid pointer 16, 18 or 20 respectively. Once execution of the command is completed, in accordance with the token table 14 under direction of the instruction means, control of the apparatus 8 is directed back to the block 80.

If all the tests in the blocks 84 to 88 establish no valid pointer 16, 18, or 20 for the current verbline 12, the block 96 recognises an error condition and alerts the user by giving an error warning accordingly. Once the error warning is given, block 96 directs the CPU 9a to perform a verbline once, under control of the block 80 and the automatic process of the present invention continues. The automatic control process may be interrupted by execution of an interrupt command means.

The interrupt may be executed by an operator of the apparatus 8 via the I/O means 9c.

The interrupt command means allows the user to interrupt the automatic process and direct operation of the data processing system in accordance with the manual process.

The interrupt command means may also be used to switch from the manual process of operation to the automatic process of operation.

The pointers stored in the token table 14 preferably are removed from the memory means 9c, by the instruction means once the process of operation has been executed through to completion under control of the command instruction means. Any one or more of the pointers may be SWITCHED OFF or disabled at any desired verbline 12. The disabling of the Pointer at a verbline 12 may be directed by the instruction means in order to invalidate the pointer at that verbline 12. Then a command correspondent with the disabled pointer cannot be executed for that particular verbline 12.

A pointer may be SWITCHED OFF by negating the corresponding data entry in the memory means 9c for the relevant verbline 12 or verblines 12. Then the tests for validity as described hereinabove will show the command to be invalid for that verbline 12.

The disabling of pointer could be associated with a user's data processing system access code, so that the user's ability to operate all or any part of the process or to view all or any of the data stored in the data processing system is dependent on a level of security provided by his/her access code.

In our co-filed British Patent Application No.

8517426 entitled "Data Processing System", (Agents ref: HL 30585), there is described and claimed a data processing system for data storage and data retrieval comprising a system bus, a bus controller, a memory means, an operating system, a central processing unit (CPU) and an input/output means, the system bus being arranged to provide electrical communication between the components of the apparatus subject to the bus controller and subject to the operating system, the memory means comprising a first storage means containing a plurality of instructions for use in an instruction means to direct operation of the data processing system and a second storage means containing, in use, a plurality of command instructions for use in a command instruction means to control operation of the data processing system, the operating system providing an interface between the instruction means and the command instruction means and the remainder of the data processing sys tem, the command instruction means control ling the data processing system under direction of the instruction means, and the input/output means being for input of data into the apparatus and output of data from the apparatus, the command instructions comprising command components and connection components each of the command components and each of the connection components having one or more parameter components, the command components controlling operation of the apparatus subject to one or more parameter components related by one or more of the connection components such that the structure of the command instruction is independent of the order of the parameter components and their corresponding connection components.

In our co-filed British Patent Application No.

entitled "Data Processing System" there is also described and claimed a data processing system for data storage and data retrieval comprising a system bus, a bus controller, a memory means, an operating system, a a central processing unit (CPU), and an input/output means, the system bus being arranged to provide electrical communication between the components of the apparatus subject to the bus controller and subject to the operating system, the memory means comprising a first storage containing a plurality of instructions for use in an instruction means to direct operation of the data processing system and a second storage means containing, in use, a plurality of command instructions for use in an instruction means to control the operation of the data processing system, the operating system providing an interface between the instruction means and the command instruction means and the remainder of the system, the command instruction means controlling the data processing system under direction of the instruction means, and the input/output means being for input of data into the apparatus and output of data from the apparatus, the memory means also comprising a third storage means, containing a plurality of data storage means, the data storage means including raw data storage means, first data definition storage means and second data definition storage means.

The entire disclosure of this co-filed application is to be considered as being imported into the present specification. Modifications and variations such as would be apparent to a skilled addressee are deemed within the scope of the present invention. For example, the token table 14 could be generated dynamically instead of statically, so that the apparatus 8 determines the relevant pointers as the process proceeds without creating a store for all the pointers relevant to the store of command instructions generated by the user and contained in the second storage means.

Claims (20)

1. A data processing system for data storage and data retrieval characterised in that it comprises a central processing unit, a memory means, an input/output means and an operating system linked by a system bus under control of a bus controller, the memory means having a first storage means containing a plurality of instructions for use in an instruction means to direct operation of the data processing system and a second storage means provided with, in use, a plurality of instructions for use in a command instruction means, the operating system providing interface for the instruction means and the command instructions means to the remainder of the data processing system, the command instruction means controlling the data processing system under direction of the instruction means, the instruction means generating and assigning pointers for each of the instructions in command instruction means, the pointers representative of the location of preceding and succeeding instructions relative to a current instruction, wherein the pointers comprise a first pointer representative of the location of a succeeding instruction which is nested in the current instruction, a second pointer representative of the location of a succeeding instruction which is at a level of nesting the same as and within a nest of instructions the same as the current instruction, a third pointer representative of the location of a preceding instruction which nests the current instruction and a fourth pointer representative of the location of a preceding instruction which is at a level of nesting the same as and within a nest of instruction the same as the current instruction, the system being manually controllable by a manual control means and/or automatically controllable by an automatic control means.

2. A data processing system according to claim 1, characterised in that the instruction means comprises means to allow control of the direction of operation of the data processing system under control of the command instruction means such that data records accessed by the command instruction means in respect of a current instruction may be stepped through forwardly or backwardly.

3. A data processing system according to claim 1 or 2, characterised in that it is manually controllable by the manual control means in accordance with the command instruction means and subject to any or all of the pointers.

4. A data processing system according to claim 1 or 2, characterised in that it is automatically controllable by the automatic control means in accordance with the command instruction means and subject to any or all of the first pointer, the second pointer and the third pointer.

5. A data processing system according to any one of the preceding claims, characterised in that the memory means further comprises a third storage means capable of containing data to be accessed and processed.

6. A data processing system according to any one of the preceding claims, characterised in that the command instruction means comprises textual command instructions stored in the second storage means and generated by a user of the data processing system via the input/output means.

7. A data processing system according to any one of the preceding claims 1 to 6, characterised in that the command instruction means comprises implied textual command instructions stored in the second storage means and generated in response to instructions entered into the data processing system by a user via the input/output means in respect of queries generated by the instruction means.

8. A data processing system according to claim 6, characterised in that the textual command instruction in the second storage means enable manual control, by the manual control means, and/or automatic control, by the automatic control means, of the data processing system to follow a desired direction of execution to access and process data from the memory means.

9. A data processing system according to claim 7, characterised in that the implied textual command instructions enable manual control, by the manual control means, or automatic control, by the automatic control means, of the data processing system to follow a desired direction of execution to access and process data in the memory means.

10. A data processing system according to any one of the preceding claims 5, 6 or 8, characterised in that the command instructions in the second storage means have a physical location on a display means of the input/output means such that, a textual instruction which succeeds the current textual instruction and which is nested in the current textual instruction is indented from the current textual instruction and is represented by the first pointer, a textual instruction which succeeds the current textual instruction and which is at a level of nesting the same as and within a nest of textual instructions the same as the current textual instruction is located immediately below the current textual instruction and is represented by the second pointer, a textual instruction which precedes the current textual instruction and which nests the current textual instruction is positioned so that the current textual instruction appears to be indented from it and is represented by the third pointer and a textual instruction which precedes the current textual instruction and which is at a level of nesting the same as and within a nest of textual instructions the same as the current textual instruction is located immediately above the current textual instruction and is represented by the fourth pointer.

11. A data processing system according to any one of the preceding claims, characterised in that means is provided to allow interrupt in the operation of the system to change control from the manual control means to the automatic control means.

12. A data processing system according to any one of the preceding claims 1 to 11, characterised in that means is provided to allow interrupt in the operation of the system to change control from automatic control means to the manual control means.

13. A process for the control of a data processing system in relation to data storage and data retrieval, characterised in that it comprises accepting a pluraltiy of command instructions for a command instruction means from an input/output device and storing them in a second storage means under direction of an instruction means having a plurality of instructions stored in a first storage means via a system bus under control of a bus controller and interfaced by an operating system, generating and assigning pointers to each instruction of the command instructon means, the pointers representative of the location of preceding and succeeding instructions relative to a current instruction, wherein the pointers comprise a first pointer representative of the location of a succeeding instruction which is nested in the command instruction, a second pointer representative of the location of a succeeding instruction which is at a level of nesting the same as and within a nest of instructions the same as the current instruction, a third pointer representative of the location of a preceding instruction which nests the current instruction and a fourth pointer representative of the location of a preceding instruction which is at a level of nesting the same as and within a nest of instructions the same as the current instruction, and storing the pointers in an array, the process being manually controllable by a manual control means and/or automatically controllable by an automatic control means to follow a desired direction of execution.

14. A process according to claim 13, characterised in that it comprises manual control by the manual control means in accordance with the command instruction means and subject to any or all of the pointers.

15. A process according to claim 13, characterised in that it comprises automatic control by the automatic control means in accordance with the command instructon means and subject to any or all of the first pointer, the second pointer and the third pointer.

16. A process according to any one of the preceding claims 13 to 15, characterised in that it comprises storing data in a third storage means, the data to be accessed and processed by the command instruction means under direction of the instruction means.

17. A process according to any one of the preceding claims 13 to 16, characterised in that a user enters a plurality of textual command instructions via the input/output means into the second storage means to direct the control of the instruction means.

18. A process according to any one of the preceding claims 13 to 16, characterised in that a user creates a plurality of implied textual command instructions via the input/output means into the second storage means chosen from a plurality of implied textual command instructions presented by the instruction means.

19. A process according to claims 16 or 17 characterised in that a user enters textual command instructons into the input/output means, the textual command instructions located physically on a display means of the input/output means such that, a textual instruction which succeeds the current textual instruction and which is nested in the current textual instruction is indented from the current textual instruction and is represented by the first pointer, a textual instruction which succeeds the current textual instruction and which is at a level of nesting the same as and within a nest of textual instructions the same as the current textual instruction is located immediately below the current textual instruction and is represented by the second pointer, a textual instruction which precedes the current textual instruction and which nests the current textual instruction is set so that the current textual instruction appears to be indented from it and is represented by the third pointer, and a textual instruction which precedes the current textual instruction and which is at a level of nesting the same as and within a nest of textual instructions the same as the current textual instruction is located immediately above the current textual instruction and is represented by the fourth pointer.

20. A data processing apparatus substantially as hereinbefore described with reference to the accompanying figures.