GB2165091A - IGFET and method for fabricating same - Google Patents

Abstract

An IGFET (10) with reduced parasitic bipolar effects comprises a semiconductor wafer (12) having a drain region (20, 22) of first conductivity type contiguous with a wafer surface (14). A body region (24) of second conductivity type is diffused into the wafer (12) from a portion of the wafer surface (14) so as to form a body/drain PN junction (26). A source region (28) of first conductivity type is diffused from the water surface (14) within the boundary of the body region (24) so as to form a source/body PN junction (30) which extends to a predetermined depth from the wafer surface (14). The source/body PN junction (30) is spaced from the body/drain PN junction (26) so as to define a channel region (32) in the body region (24) at the wafer surface (14). An aluminium layer (42) is formed in the wafer surface (14) such that the aluminium electrically contacts via aluminium "spikes" (43) the source/body PN junction (30) from being biased during device (10) operation. <IMAGE>

Description

SPECIFICATION IGFET and method for fabricating same The present invention relates to insulated gate field effect transistors (IGFETs) such as metal oxide semiconductor field effect transistors (MOSFETs). It is applicable to IGFETs generally and to lateral MOS devices. Illustratively, the invention may be applied to vertical MOSFETs wherein source and gate electrodes are disposed on one surface of a semiconductor wafer and a drain electrode is disposed on an oposing surface of the wafer. The invention is particularly applicable to vertical, double-diffused MOSFET (VDMOS) devices such as conductivity modulated FETs (COMFETs). In the following, the invention and its background will be described, by way of example, with reference to VDMOS devices.

A VDMOS device includes a semiconductor wafer in which source, body and drain regions of alternate conductivity type are disposed in series. The body region is disposed adjacent to a wafer surface and the source and drain regions are located so as to define the length and width of the channel region in the body region at that surface. The term VDMOS derives from the method for fabricating the device.

The method constitutes providing a drain region at a semiconductor wafer surface and diffusing a body region dopant and a source region dopant, typically sequentially, into a portion of the drain region through a mask aperture.

An insulated gate electrode is disposed on the wafer surface over the channel region. During device operation, when a voltage greater than a particular threshold voltage is applied to the gate electrode, the conductivity type of the body region in that portion of the channel region that is contiguous with the wafer surface is inverted. This forms what is termed an inversion channel, which permits electron or hole current flow between the source and drain regions. Thus, device operation is described as being unipolar in nature, with electron or hole flow being selectively modulated by an applied voltage to the gate. Further elaboration on conventional VDMOS structures and processing may be found in U.S. Patent No. 4,145,700, POWER FIELD EFFECT TRANSISTORS, C.J. Jambotkar, March 1979, and in U.S.Patent No. 4,072,975, INSULATED GATE FIELD EFFECTTRANSISTOR, A. Ishitani, February 7, 1978.

A COMFET is a variety of VDMOS device which further incorporates a fourth semiconductor region, of opposite conductivity type to the drain region, contiguous with the drain region. This fourth semiconductor region, which may be referred to as an anode region, provides a source of charge carriers during device operation and serves to modulate the conductivity of the drain region adjacent thereto.

One of the significant characteristics of a COMFET device is its greatly reduced on-resistance compared to an equivalently structured three layer VDMOS FET. Further elaboration on the structure of a COMFET may be found in commonly assigned U.S.

Patent No. 4,364,073, POWER MOSFET WITH AN ANODE REGION, H.W. Becke et al., December 14, 1982.

Inherent in the three layer source/body/drain structure of a MOSFET is a parasitic NPN or PNP bipolar transistor. The source/body/drain MOSFET structure corresponds to a parasitic emitter/base/collector bipolar structure. During operation of the MOSFET, should the emitter/base PN junction be forward biased, the parasitic bipolar transistor will be turned on. Since this is deterimental to MOSFET performance, various efforts have been employed so as to reduce the gain of the parasitic bipolar transistor. An example of such an effort is described in the previously cited patent to A. Ishitani, as well as in U.S. Patent Application Serial No.582,601, VERTIC AL MOSFETWITH REDUCED BIPOLAR EFFECTS AND METHOD FOR MAKING SAME, L.A. Goodman et al., filed February 22, 1984 which corresponds to British patent application 2154794.

Reduction of the gain of the parasitic bipolar transistor(s) in a COMFET is of particular importance in that the sum of the gains of the source/body/drain parasitic bipolar transistor and the anode/drain/body parasitic bipolar transistor must be kept less than one so as to prevent latchup of the parasitic NPNP of PNPN thyristor. Should latchup occur, gate control will be lost and the device will no longer operate as a COMFET.

Accordingly, it is desirable to reduce the likelihood of latchup in COMFETS, as well as to reduce the effects of the parasitic bipolar transistor in three layer IGFET devices.

Aspects of the present invention are specified in the claims. According to one aspect there is provided an IGFET with reduced parasitic bipolar effects which comprises a semiconductor wafer and having a drain region of first conductivity type contiguous with a wafer surface. A body region of second conductivity type is diffused into the wafer from a portion of the wafer surface so as to form a body/drain PN junction. A source region of first conductivity type is diffused from the wafer surface within the boundary of the body region so as to form a source/body PN junction which extends to a predetermined depth from the wafer surface. The source/body PN junction is spaced from the body/ drain PN junction so as to define a channel region in the body region at the wafer surface.Aluminum is formed on the wafer surface such that it contacts the source/body PN junction at the predetermined depth and prevents the source/body PN junction from being forward biased during device operation.

The invention will now be described by way of example with reference to the accompanying drawing in which the Figure illustrates a sectional view of an illustrative VDMOS device incorporating the present invention.

As shown in the FIGURE, a VDMOS device 10 incorporating the present invention may be either a three layer MOSFET or a four layer COMFET. For clarity of description, the invention is described as being embodied in an N channel VDMOS device, although it should be understood that all of the conductivity types may be reversed so as to form a P channel VDMOS device. The device 10 comprises a semiconductor wafer 12 having first and second major surfaces 14 and 16 respectively. Disposed across the second major surface 16 is a relatively high conductivity region 18 of either Nt or P+ type material. In a three layer N channel MOSFETthe region 18 is of N+ type material and is referred to as a drain region. In an N channel COMFETthe region 18 is of P+ type material and is referred to as an anode region.In the N channel COMFET structure an N+ type drain region 20 optionally overlies the anode region 18 as shown by the broken line in the illustration. Contiguous with the N + type drain region 20, or with the relatively high conductivity region 18 when the region 20 is not present, is an Ntype extended drain region 22 which extends to the first major surface 14.

Extending into the wafer 12 from the first surface 14 is a P- type body region 24 which forms a body/drain PN junction 26 at its interface with the N-extended drain region 22. In a preferred embodiment the body region 24 is diffused into the wafer from a selected portion of the surface 14 such that the body/drain PN junction 26 intercepts the surface 14 in the form of a regular polygon such as a hexagon or square. Extending into the wafer 12 from the first surface 14 within the boundary of the body region 24 is an N + type source region 28 which forms a sourcelbody PN junction 30 at its interface with the body region 24. The source/body PN junction 30 is spaced from the body/drain PN junction 26 at the surface 14 so as to define the length and width of a channel region 32 in the body region at the first surface 14.The source region 28 is typically annular, although not circular, in shape.

The outer portion of the sourcelbody PN junction 30 intercepts the surface to that of the body/drain PN junction 26 intercept. Extending from the surface 14 into the central portion of the body region 24, and surrounded by the annular source region 28, is a P+ type supplementary body region 34.

Disposed on the first surface 14 over the channel region 32 is an insulated gate electrode which comprises gate insulation 36 on the surface 14 and a gate electrode 38 on the gate insulation 36. The gate insulation 36 typically comprises silicon dioxide in the thickness range of approximately 500 to 2,000 Angstroms, and the gate electrode 38 typically comprises doped polycrystalline silicon. An insulating layer 40, typically comprising a silicate glass such as phosphosilicate glass (PSG), borosilicate glass (BSG) or borophosphosilicate glass (BPSG) overlies the gate electrode 38 so as to electrically isolate the electrode from overlying layers. An aluminum source electrode 42 overlies the insulating layer 40 and contacts the first surface 14 so as to form a contact with the source region 28 and the body region 24.A drain electrode 44 contacts the high conductivity region 18 on the second surface 16.

It is critical to the method of the present invention that the aluminum source electrode 42 be deposited such that it "spikes" into the wafer 12 to at least the depth of the source/body PN junction 30, so as to contact the P- body region 24. The aluminum spikes are illustrated in the Figure at 43. Elaboration upon this aluminum spiking phenomenon can be found in U.S. Patent No.3,609,470, SEMICONDUCTOR DE VICES WITH LINES AND ELECTRODES WHICH CON TAIN 2 to 3 PERCENT SILICON WITH THE REMAIN DER ALUMINUM, Lubertus L. Kulper, September 28 1971. In the present invention, it is advantageous for the aluminum to spike through and contact as great an area of the source/body PN junction 30 as is possible without detrimentally affecting the channel region 32.At the optimum spiking depth, the aluminum spikes 43 penetrate the source/body PN junction 30 but do not extend a substantial distance into the body region 24.

The aluminum spiking is achieved by subjecting the device to a heat treatment either during or following the deposition of the source electrode 42.

In the preferred embodiment the aluminum source electrode 42 is deposited by conventional vapor deposition means such as evaporation or sputtering and is then heat treated at approximately 400" to 450"C for a period of approximately 15 minutes to one hour. This yields aluminum spikes 43 penetrating to a distance of approximately 0.5 to 1.5 microns from the surface 14. Since 1.5 microns is the approximate maximum spiking distance with this heat treatment, other device processing should ensure that the depth of the source/body PN junction 30 from the surface 14 is kept less than 1.5 microns.

In the preferred embodiment the depth of the source/body PN junction 30 is less than 1 micron, and optimally is less than approximately 0.5 micron.

This is relatively shallow compared to conventional devices, which typically have source regions extend- ing to depths greater than 1 micron. So as to controllably achieve this relatively shallow source/ body PN junction depth, it is preferable to use arsenic as the N type dopant for the source region 28. Although phosphorus could alternatively be used as an N type source dopant, it is more difficult to control the diffusion thereof to less than 1 micron.

In the fabrication of the device 10 the insulated gate electrode serves as a mask for locating the source and body regions 28 or 24 at the surface 14.

The insulated gate electrode typically has the configuration of an apertured layer, and the body and source region dopants are sequentially introduced into the wafer 12 through the apertures. The aperture provided by the insulated gate electrode is identified at 46 in the FIGURE. From the standpoint of maximizing the effectiveness of the spiking of the present invention, the contact area of the source electrode 42 on the surface 14 should overlie the source/body PN junction 30, at points removed from the channel region 32, to the greatest extent possible. This will maximize the area of the source/body PN junction 30 which is contacted by the aluminum spikes 43 following the indicated heat treatment.

Additionally, when practicing the present inven tion the dopant concentration in the P- type body region 24 should be adjusted so as to compensate the device threshold voltage for the relatively shallow diffusion of the source region 28. That is, the diffusion which yields a relatively shallow depth for source region 28 yields a relatively small lateral diffusion distance as well. Since the threshold voltage, (i.e., the voltage at which the inversion channel is formed) is controlled by the carrier concentration at the source/body PN junction 30 adjacent to the channel region 32, the P- dopant concentration in the body region 24 at the source/ body PN junction 30 must be reduced commensurately with the reduction in the lateral diffusion distance of the N+ dopant of the source region 28.

The aluminum spikes 43 effectively reduce the forward current gain oi of the parasitic bipolar transistor corresponding to the NPN source/body/ drain structure of the VDMOS device 10. Comparing a device without aluminum spikes to a device incorporating the present invention, we have observed an a of approximately 0.9 on the unspiked device and a ' 0.25 on a typical spiked device. When incorporated in COMFETs, the aluminum spikes 43 have been observed to increase latchup currents by factors ranging up to one hundred.

Additionally, the method of the present invention may obviate the need for the P+ type supplementary body region 34 in that the aluminum spikes 43 provide contact to both the body region 24 and the source/body PN junction 30, thereby connecting the P- body region 24 to the source electrode 42.

Furthermore, the method of the present invention may simplify the configuration of the source region 28 in that it may no longer be necessary to provide an annular shaped region. In that the aluminum spikes 43 project to the depth of the source/body PN junction 30, the need for the supplementary region 34 to connect the body region 24 to the source electrode at the surface 14 may no longer be required.

Lastly, it should be understood that although the invention has been described with reference to VDMOS devices, it is also readily applicable to lateral MOS devices as well as IGFETs, generally.

Claims (8)

1. Amethod for fabricating an lGFETcomprising the steps of providing a semiconductor wafer having a drain region of first conductivity type contiguous with a wafer surface, diffusing a body region of second conductivity type into the wafer from a portion of the surface so as to form a body/drain PM junction, and diffusing a source region of first conductivity type within the boundary of the body region so as to form a source/body PN junction which extends to a predetermined depth from the wafer surface, said source/body junction being spaced from said body/drain junction so as to define a channel region in the body region at the surface, the method comprising the further step of forming an aluminum layer on said wafer surface so as to contact the source/body junction at said predetermined depth, so as to prevent the source/ body PN junction from being forward biased during device operation.

2. A method in accordance with claim 1 wherein the step of forming said aluminum layer comprises: depositing aluminum; and heating said aluminum at approximately 400450"C for approximately 15 minutes to one hour.

3. A method in accordance with claim 1 or 2 wherein said predetermined depth of the source/ body PN junction is less than approximately 1.0 micron.

4. A method in accordance with claim 1,2 or 3 comprising diffusing arsenic to form said source region.

5. An IGFETcomprising a semiconductor wafer having a drain region of first conductivity type contiguous with a wafer surface, a body region of second conductivity type extending into the wafer from a portion of the surface so as to form a body/drain PN junction, and a source region of first conductivity type within the boundary of the body region so as to form a source/body PN junction which extends to a predetermined depth from the wafer surface, said source/body junction being spaced from said body/drain junction so as to define a channel region in the body region at the surface, the IGFET further comprising: an aluminum electrode disposed on said wafer surface, said electrode including spikes which contact the source/body junction at said predetermined depth, such that the source/body PN junction is not forward biased during device operation.

6. An IGFETin accordance with claim 5, wherein: said predetermined depth of the source/body PN junction is less than approximately 1.0 micron; and said spikes project to a depth of approximately 1.0 micron.

7. A method for fabricating an IGFET substantial ly as hereinbefore described with reference to the accompanying drawing.

8. An IGFET substantially as hereinbefore described with reference to the Figure of the accompanying drawing.