GB2158326A - Testing arrangements of a digital switching systems - Google Patents

Abstract

To test a digital line from a switching centre to subscriber's apparatus a loopback test method is used, in which a pseudo-random bit sequence is sent from the exchange via the GO path and looped back at a desired one of three points (A, B, C) in the path. After each loopback the bit sequence as it returns is monitored and its condition indicates whether there is an error present. By successive use of the different loopback points a detected error can be located. Generation of the pseudo-random bit sequence uses a feedback shift register, and monitoring is effected by applying the returned bit sequence to a similar feedback shift register whose condition thereafter indicates whether there is an error present. The output of the second register is used, with a counter to so control a third feedback shift register to eliminate errors due to the taps on the second register. <IMAGE>

Description

SPECIFICATION Testing arrangements of a digital switching systems This invention relates to switching systems which are fully digital up to the subscriber's apparatus.

In such a system it is necessary to be able to test the transmission path between the switching centre and the subscriber's apparatus. A known way to do this is to send known data patterns from the switching centre to the exchange, which latter "echoes" the patterns back to the switching centre, either unmodified or modified in known manner. The switching centre then monitors what it receives in the light of what was sent and determines therefrom whether there is an error condition.

The present invention relates to an improvement to such a system, and in accordance with the invention there is provided a method of testing the transmission path which extends from a digital switching centre to a digital subscriber's apparatus, in which a digital word is generated as a pseudo-random bit sequence and transmitted from the digital centre towards the subscriber's apparatus, in which the GO and RETURN signal paths can be interconnected temporarily at a plurality of points between the point of origin of said pseudo-random sequence and the subscriber's apparatus, so that the pseudo-random sequence can be looped back at any one of said points, in which when a loopback test is performed the bit sequence which is thereby returned to the point of origin is monitored to assess the presence or absence of errors, and in which the loopback and monitoring operations are repeated at said plurality of points so as to determine the location of any error detected in the course of said monitoring.

An embodiment of the invention will now be described with reference to the accompanying drawings, in which Fig. 1 is a simplified diagram explanatory of the present invention, while Fig.

2 shows logic circuits forming part of the exchange.

The provision of a numbr of loopbacks within the digital transmission line circuits at the switching centre and subset enables two types of test to be performed. These are short duration fault diagnostic tests via progressive loopback testing to identify fault location on inoperative lines, and longer duration tests based on a loopback at the subset to obtain a measure of the transmission performance of each line.

Both types of tests could be performed on a routine basis during periods of low traffic activity.

Three possible positions at which loopback can be performed for testing, are used, as indicated in the arrangement of Fig. 1. These positions are: (a) A loopback of the 384 Kbit/s AMI (Alternate Mark Inversion) bit stream at the output of the Digital Transmission (DTx) chip 1 for loopbacks at the exchange end of the transmission link.

(b) A loopback at the line transformer 2 associated with the analogue circuits at the exchange end of the transmission link. This loopback when provided, needs the addition of a relay and a small number of logic gates.

(c) A loopback (or reflection test) at the B channel interface of the Digital Transmission (DTx) chip 3 at the subscriber's set enabling loopbacks at the subset end of the transmission link.

The B channel is one of the channels provided by the splitting of the bit stream into several interlaced channels. It is usually used as two separate and independent channels designated B1 and B2.

Note that loopbacks can be added at other points if desired.

The basic principle of loopback testing in the present system involves the transmission of a pseudo-random test pattern in the B channels, and a check upon the received data. No loopback testing of the D channel (another channel provided in the bit stream) is performed, so that during a loopback test the signalling channel is available for the control of the test and/or setting up of calls. Similarly no loopback checking is performed on the sync., or the parity bits which accompany the data.

The technique of double buffering used for the B channel interfaces means that the B1 and B2 channels are not treated as one continuous data channel, because of the likelihood that the two B channels will be returned with different frame delays. Therefore, each B channel is tested independently. Note that for fault diagnostic testing only one channel normally needs to be tested. Note also that in the present system the B channel is used to provide two separate channels.

The effect of double buffering on the B channel, plus the variable slave (subset) transmission delay technique (used to ensure a suitable guard time after the transmit burst at the exchange end of the transmission link) means that it is not feasible to directly compare the received pseudo-random pattern with that transmitted using a fixed frame delay offset, as the overall frame delay could legitimately change during a test through the correct operation of the double buffer or variable delay circuits.

A method of synchronising the transmit and receive data and thereby calculating the overall frame delay could be devised, but it would be too complex and might mean that only 7 out of the 8 B channel bits were available for testing. Hence another technique of checking the received data is used, whereby the integrity of the received pseudo-random pattern is checked.

The received pseudo-random pattern is compared against the feedback term produced when the transmit pseudo-random pattern algorithm is performed upon the received data. This technique however, gives a multiplication of errors, so that one error in the received data causes further errors depending upon the number of feedback terms used to generate the pseudorandom pattern. The use of another stage of checking can eliminates such multiplication of errors, producing a test which gives a close approximation to the true error rate, since that only 8 out of the 20 bits in each burst are being checked.

The theory of this integrity checking is described below.

The loopback tests are to be controlled from the switching centre's control means, referred to as the MTSI, using the line circuit control bits in the channel bus (a 32 channel serial multiplex at 2048 kbit/s) giving access thereto. The pseudo-random pattern is generated and checked in the MTSI and its interface to the line under test via the appropriate B channel bus (again a 32 channel serial multiplex at 2048 kbit/s).

Loopbacks (A) and (B) are controlled by DC inputs to the DTx chip, block 1, and the loopback etc. in block 4 respectively. Loopback (C), the reflection test at the subset, is set up through the D channel signalling path controlling another DC input to the DTx chip 3.

For loopbacks (A) and (C) above the subset can originate a call during a test, either by the exchange detecting a received signal (i.e. received AGC) in case (A) or through the D channel signalling path in case (C). For the loopback case (B), the subset is not able to originate a call, but as this mode is normally only used during short-term fault diagnostic tests this is not a problem. In all cases of loopback testing, the exchange can abort a test and revert to normal operation when required.

The implementation of this loopback philosophy has some impact upon the software needed to control all of the equipment on one shelf of the equipment to set up, control and process the information generated from the tests. Such a shelf carries equipment for a number of lines, and is called a group shelf. The hardware needed consists of approximately one half of a card and includes the generation of all the clocks and strobes required to drive the digital transmission interfaces.

The use of three loopbacks as described above, together with a line current alarm (i.e. when line current drawn is outside the specified limits), enables the location of the majority of faults to be identified as either faulty exchange DTx chip, faulty exchange block 4, a line fault or a subset failure.

This circuit, Fig. 2, which is in the above-mentioned MTSI, provides a method for measuring the number of errors on the digital transmission link. It employs a novel method of synchronising the receive logic onto the transmitted sequence so that the circuit can cope with any external delay and also with changes of delay during operation.

Shift register A, to A7 generates a 1 27-bit pseudo-random sequence, corresponding to the generator polynomial x7 + x + 1. Tables of polynomials that generate other maximal length sequences have been widely published. Gate G1 is included to ensure that th circuit does not latch into an "all zero" state.

Shift register B1 to B7 takes the received data and produces a one at the output of gate G2 whenever a violation is detected in the pseudo-random sequence. Gate G3 is included to ensure that a received sequence of all zeroes indicates violation.

A single bit in error causes an immediate violation followed by two additional violations as a consequence of the nature of the feedback used. Shift register C1 to C7 identifies and cancels out the additional violations. This last shift register has to be initialised, which is done after a continuous period with no violations. This period is recognised by counter Xl which is synchronously cleared by a violation. When the counter reaches its maximum value it is disabled and inhibits the feedback term of shift register C, to C7 until another violation is detected.

In a practical circuit, all three shift registers can be extended together to 20 or 30 bits long each, and X, then becomes an 8-bit counter looking for a period of 256 cycles without a violation.

For a generator polynomial G(x) of order N, the transmitter section generates a transmit sequence T(x) whose kth bit is given by the coefficient of xk+l in: T(x)= A(x)/G(x) (1) where A(x) represents the initial state of the shift register, so that A(x) has order less than N and gate G, ensures that A(x) is not zero.

Now let the polynomial E(x) represent the errors so that the received sequence R(x) is R(x) = T(x) + E(x) = A(x)/G(x) + E(x) (2) Ignoring gate G2, if register B1 to B7 is initialised B(x) where the order of B(x) is less than N, then the detected violations V(x) are: V(x) = [R(x) + B(x)/xN].G(x) = A(x) + E(x).G(x) + B(x).G(x)/xN (3) = E(x).G(x) + K(x) where the order of K(x) is less than N. For the moment ignoring the initialising circuit, the true error output F(x) is: F(x) = V(x) + C(x)/xN]/G(x) = [E(x).G(x) + K1(x)J/G(x) (4) = E(x) + K'(x)/G(x) where C(x) represents the initial state of register C, to C,. When the initialising circuit is included, it will be seen that it will clear the K'(x) term for coefficients after the period with no violations. This leaves F(x) = E(x) + K"(x) where K"(x) is eventually all zeros as desired.

Thus it will be seen that spurious error indications due to the taps on the second register are eliminated by the combination of the counter xl and the third register C1-C7.

Claims (6)

1. A method of testing the transmission path which extends from a digital switching centre to a digital subscriber's apparatus, in which a digital word is generated as a pseudo-random bit sequence and transmitted from the digital centre towards the subscriber's apparatus, in which the GO and RETURN signal paths can be interconnected temporarily at a plurality of points between the point of origin of said pseudo-random sequence and the subscriber's apparatus, so that the pseudo-random sequence can be looped back at any one of said points, in which when a loopback test is performed the bit sequence which is thereby returned to the point of origin is monitored to assess the presence or absence of errors, and in which the loopback and monitoring operations are repeated at said plurality of points so as to determine the location of any error detected in the course of said monitoring.

2. A method as claimed in claim 1; in which the pseudo-random bit sequence is generated by a feedback shift register and the sequence which returns to the point of origin as a result of the loopback is monitored by applying it to another feedback shift register, and in which the condition of the second feedback shift register after said application indicates whether any error is present and in which a third feedback shift register associated with the second feedback shift register is used, under control of the contents of the second register to cancel errors caused by the taps on the second register.

3. A method of testing the transmission path which extends from a digital switching centre to a digital subscriber's apparatus, substantially as described with reference to the accompanying drawings.

4. An automatic telecommunication switching system in which transmission paths each extend from a digital switching centre to a digital subscriber's apparatus, in which to test such a path a digital word is generated as a pseudo-random bit sequence and transmitted from the digital centre towards the subscriber's apparatus, in which the GO and RETURN signal paths can be interconnected temporarily at a plurality of points between the point of origin of said pseudo-random sequence and the subscriber's apparatus, so that the pseudo-random sequence can be looped back at any one of said points, in which when a loopback test is performed the bit sequence which is thereby returned to the point of origin is monitored to assess the presence or absence of errors, and in which the loopback and monitoring operations are repeated at said plurality of points so as to determine the location of any error detected in the course of said monitoring.

5. A system as claimed in claim 1, in which the pseudo-random bit source is generated by a feedback shift register and the sequence which returns to the point of origin as a result of the loopback is monitored by applying it to another feedback shift register, in which the output of the second feedback shift register after said application indicates whether errors are present, and in which a third feedback shift register associated with the second feedback shift register is used, under the control of the second register, to cancel errors due to the taps on the second register.

6. An automatic switching system, substantially as described with reference to the accompanying drawings.