GB2157521A - Improvements relating to interface circuits - Google Patents

Abstract

A semi-conductor switch (not shown) in a high voltage circuit is operated by low voltage logic and therefore requires some form of isolation in an interface circuit. This is provided by capacitors (3, 4) in each line from the logic circuit so that the output (8, 9) is 'floating' in relation to the input (1, 2). To achieve the necessary size of signal a voltage multiplier may be incorporated in the interface circuit, between the capacitors and the output (Fig. 2). The circuit is conveniently monolithically constructed on a substrate as an integrated circuit. <IMAGE>

Description

SPECIFICATION Improvements relating to interface circuits This invention relates to interface circuits. It is concerned primarily with interfacing high voltage bidirectional signals with low voltage logic control.

Direct control of a bidirectional semiconducting switch from a low voltage requires some form of isolating drive technique. Known solutions to the problem include electro-mechanical relays, whose short-comings are well known, and opto-copled devices, which deteriorate with time, are costly and have limited application.

It is the aim of this invention to provide a more reliable, low cost and versatile alternative.

According to the present invention there is provided an interface circuit with a low voltage input, and capacitive coupling in each line to a high voltage output circuit.

Thus, a switch governed by the output circuit is isolated from control logic at the input using a 'floating' technique.

The circuit will generally incorporate a voltage multiplier between the capacitive coupling and the output circuit and its components can readily be monolithically integrated with the capacitive coupling.

For a better understanding of the invention, some embodiments will now be described, by way of example, with reference to the accompanying drawing, in which: Figure 1 is a diagram of an interface circuit incorporating a voltage doubler, Figure 2 is a diagram of an interface circuit with a voltage quadrupler, and Figure 3 is a perspective view of the circuit of Figure 1 embodied in a wafer.

The circuit of Figure 1 is for driving capacitive loads and has input terminals 1 and 2 to which are applied clock-waveforms of opposite phase. These will pass through DC isolating capacitors 3 and 4to a voltage doubler comprising a bridging diode 5 and diodes 6 and 7 arranged in opposite senses in the lines to output terminals 8 and 9, the latter being bridged by resistor 10. The load across the output terminals is represented by a capacitor 11.

The input may be any form of applied logic, and the circuit is capable of being driven directly from 5 volt and microprocessor outputs. The output can be used to control semiconductor switches which may be operating at 240 volts, but which will be safely isolated from the input logic. These switches may be bidirectional M.O.S. Switches, of either enhancement or depletion type, or junction field effect transistors, for example.

With terminal 1 at logic '1' level and terminal 2 at logic '0', current will flow into the load capacitor 11 through capacitors 3 and 4. These will therefore partly charge in one direction during the applied half cycle to a fraction of the differentially applied input voltage, the charge value being determined by all these capacitances. During the next half cycle, the current path will be in the opposite direction via capacitor 4, diode 5 and capacitor 3. The previous charge on the two isolating capacitors 3 and 4 will therefore practically cancel over this period.

Subsequent cycles will progressively charge up capacitor 11 to a final value.

Figure 2 shows an equivalent circuit for voltage quadrupling, and it will be understood that other, higher multiplication factors can be obtained by different combinations of capacitors and diodes.

Although such a circuit may be built up from discrete components, it will be preferred to construct it monolithically, as shown in Figure 3, where various parts are referenced as in Figure 1.

The circuit is formed on a silicon substitute 12 which provides the necessary mechanical strength.

This has a silicon oxide superstructure 13 with a poly silicon layer 14 in which the diodes and resistors are formed.

This layer 14 is lightly doped with N type impurity and the diodes are formed by implanting P type inpurity into selected regions of it to form semiconductor-functions. The two adjacent regions of each diode are identified by panel N with the association number 5, 6 or 7 as a subscript.

The capacitors 3 and 4 are formed by a thick silicon oxide layer 15 with aluminium depositions 16 and 17 on the upper face, to which the input terminals 1 and 2 are attached, and N+ regions 18 and 19 implanted in the layer 14. The layer 15 provides the necessary isolation between the high voltage in the poly silicon layer and the low voltage logic input. Aluminium depositions 20 and 21 provide the junctions between these capacitors and the diodes.

The resistor 10 is formed by a high sensitivity Npoly silicon region, and the coupling to the output terminals 8 and 9 is by means of further aluminium depositions 22 and 23.

It will be understood that there are alternatives to the materials and components referred to above.

For example, it is contemplated that silicon on sapphire might be an improvement on poly silicon, and that using active components (i.e. transistors) rather than passive ones such as diodes and resistors might lead to a more compact unit.

However, at least in the device described the fabrication entails few mask stages and is consequently high yielding (i.e. low failure rate) and of low cost.

1. An interface circuit with a low voltage input, and capacitive coupling in each line to a high voltage output circuit.

2. An interface circuit as claimed in Claim 1, incorporating a voltage multiplier between the capacitive coupling and the output circuit.

3. A circuit as claimed in Claim 2, wherein the

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (4)

**WARNING** start of CLMS field may overlap end of DESC **. SPECIFICATION Improvements relating to interface circuits This invention relates to interface circuits. It is concerned primarily with interfacing high voltage bidirectional signals with low voltage logic control. Direct control of a bidirectional semiconducting switch from a low voltage requires some form of isolating drive technique. Known solutions to the problem include electro-mechanical relays, whose short-comings are well known, and opto-copled devices, which deteriorate with time, are costly and have limited application. It is the aim of this invention to provide a more reliable, low cost and versatile alternative. According to the present invention there is provided an interface circuit with a low voltage input, and capacitive coupling in each line to a high voltage output circuit. Thus, a switch governed by the output circuit is isolated from control logic at the input using a 'floating' technique. The circuit will generally incorporate a voltage multiplier between the capacitive coupling and the output circuit and its components can readily be monolithically integrated with the capacitive coupling. For a better understanding of the invention, some embodiments will now be described, by way of example, with reference to the accompanying drawing, in which: Figure 1 is a diagram of an interface circuit incorporating a voltage doubler, Figure 2 is a diagram of an interface circuit with a voltage quadrupler, and Figure 3 is a perspective view of the circuit of Figure 1 embodied in a wafer. The circuit of Figure 1 is for driving capacitive loads and has input terminals 1 and 2 to which are applied clock-waveforms of opposite phase. These will pass through DC isolating capacitors 3 and 4to a voltage doubler comprising a bridging diode 5 and diodes 6 and 7 arranged in opposite senses in the lines to output terminals 8 and 9, the latter being bridged by resistor 10. The load across the output terminals is represented by a capacitor 11. The input may be any form of applied logic, and the circuit is capable of being driven directly from 5 volt and microprocessor outputs. The output can be used to control semiconductor switches which may be operating at 240 volts, but which will be safely isolated from the input logic. These switches may be bidirectional M.O.S. Switches, of either enhancement or depletion type, or junction field effect transistors, for example. With terminal 1 at logic '1' level and terminal 2 at logic '0', current will flow into the load capacitor 11 through capacitors 3 and 4. These will therefore partly charge in one direction during the applied half cycle to a fraction of the differentially applied input voltage, the charge value being determined by all these capacitances. During the next half cycle, the current path will be in the opposite direction via capacitor 4, diode 5 and capacitor 3. The previous charge on the two isolating capacitors 3 and 4 will therefore practically cancel over this period. Subsequent cycles will progressively charge up capacitor 11 to a final value. Figure 2 shows an equivalent circuit for voltage quadrupling, and it will be understood that other, higher multiplication factors can be obtained by different combinations of capacitors and diodes. Although such a circuit may be built up from discrete components, it will be preferred to construct it monolithically, as shown in Figure 3, where various parts are referenced as in Figure 1. The circuit is formed on a silicon substitute 12 which provides the necessary mechanical strength. This has a silicon oxide superstructure 13 with a poly silicon layer 14 in which the diodes and resistors are formed. This layer 14 is lightly doped with N type impurity and the diodes are formed by implanting P type inpurity into selected regions of it to form semiconductor-functions. The two adjacent regions of each diode are identified by panel N with the association number 5, 6 or 7 as a subscript. The capacitors 3 and 4 are formed by a thick silicon oxide layer 15 with aluminium depositions 16 and 17 on the upper face, to which the input terminals 1 and 2 are attached, and N+ regions 18 and 19 implanted in the layer 14. The layer 15 provides the necessary isolation between the high voltage in the poly silicon layer and the low voltage logic input. Aluminium depositions 20 and 21 provide the junctions between these capacitors and the diodes. The resistor 10 is formed by a high sensitivity Npoly silicon region, and the coupling to the output terminals 8 and 9 is by means of further aluminium depositions 22 and 23. It will be understood that there are alternatives to the materials and components referred to above. For example, it is contemplated that silicon on sapphire might be an improvement on poly silicon, and that using active components (i.e. transistors) rather than passive ones such as diodes and resistors might lead to a more compact unit. However, at least in the device described the fabrication entails few mask stages and is consequently high yielding (i.e. low failure rate) and of low cost. CLAIMS

1. An interface circuit with a low voltage input, and capacitive coupling in each line to a high voltage output circuit.

2. An interface circuit as claimed in Claim 1, incorporating a voltage multiplier between the capacitive coupling and the output circuit.

3. A circuit as claimed in Claim 2, wherein the components of the multiplier circuit are monolithically integrated with the capacitive coupling.

4. An interface circuit substantially as hereinbefore described with reference to Figure 1, Figures 2 or Figure 3 of the accompanying drawing.