GB2154060A

GB2154060A - Semiconductor integrated circuit device

Info

Publication number: GB2154060A
Application number: GB08502453A
Authority: GB
Inventors: Setsuo Ogura; Shizuo Kondo; Makoto Furihata
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1981-09-24
Filing date: 1985-01-31
Publication date: 1985-08-29
Also published as: DE3235409A1; GB2154060B; GB2154061B; FR2514200B1; SG40887G; HK69187A; FR2533367A1; GB8502454D0; JPS5851561A; GB2107117A; IT1153730B; HK69887A; GB2154061A; GB8502453D0; IT8223326A0; MY8700644A; FR2533367B1; FR2514200A1; GB2107117B

Abstract

A semiconductor integrated circuit device has a complementary MISFET circuit and an I<2>L circuit formed on the same substrate. The MISFET circuit forms the input stage (I) of the IC and the I<2>L circuit forms the output stage (II), the output of the MISFET circuit is fed directly into the I<2>L circuit. This arrangement gives a high operating speed, useful output level and high density of integration. <IMAGE>

Description

1

SPECIFICATION

Semiconductor integrated circuit devices The present invention relates to a semiconduc- 70 tor integrated circuit device having a complementary insulated gate field effect transistor circuit and an integrated injection logic circuit on the same semiconductor substrate.

Semiconductor integrated circuit devices (hereinafter referred to as CMISFET- 12 L ICs) having a complementary insulated gate field effect transistor circuit (hereinafter referred to as a CMISFET) and an integrated injection logic circuit (hereinafter referred to as an 12 L) on the same semiconductor substrate, have heretofore been known. For instance, a CMISFET- 12 L IC has been disclosed in United States Patent No. 4,122,481, or in Japanese Patent Laid-Open No. 52482/1979.

United States Patent No. 4,122,481 and Japanese Patent Laid-Open No. 52482/1979 do not say much about the relationship of the connection between the CMISFET circuit and the 12L circuit.

Embodiments of the invention will now be described by way of example, with reference to the accompanying drawings, in which:

Figure 1 is a sectional view of an integrated circuit according to the first embodiment of the present invention; Figures 2A to 2H are sectional views of steps in the process for producing the integrated circuit of Fig. 1; Figure 3 is a circuit diagram which schematipally illustrates the first embodimsent; Figure 4 is a plan view which schematically shows the layout of the connection between circuit I and circuit 11 of Fig. 3; Figure 5 is a plan view of the load transisto r; Figure 6 is a circuit diagram showing the second embodiment of the present invention; Figure 7 is a circuit diagram showing the third embodiment; Figure 8 is a sectional view of an integrated circuit according to the fourth embodiment of the present invention; and Figure 9 is a circuit diagram which schema- tically illustrates the fourth embodiment.

Reference will first be made to Figs. 1 to 5, which illustrate a first embodiment of the present invention.

Fig. 1 is a diagram showing the construc- tion of a CMISFET- 12 L IC according to the present invention, in which the region X, shows the construction of the complementary MISFETs, and the region X2 shows the construction of the 12 L elements.

As shown in Fig. 1, unlike conventional devices, the integrated circuit of this embodiment makes use of a substrate which is prepared by growing a p-type epitaxial layer 2 of a low impurity concentration on a p-type silicon substrate 1 of a low impurity concentra- GB 2 154 060A 1 tion. Reference number 16 denotes an n 'type buried layer formed under the well region that will form the 12 L circuit, 3 denotes a first n-type well region of a low concentration formed in the p-type layer 2, and 4 denotes a second n-type well region having an impurity concentration, smaller than that of the first ntype well region 3. An 12 L consists of a p-type injector region 5, a p-type base region 6 of an npn inverse transistor, an n ±type collector region 7 of the npn inverse transistor and an n±type emitter contact region 8 formed in the first n-type well region 3. The n-type well region 3 forms an emitter region for the npn inverse transistor. A p-channel MISFET consists of p±type source and drain regions 9 formed in the second n-type well region 4, a gate insulation film 11, and a polycrystalline silicon layer 14 that serves as a gate elec- trode. An n-channel MISFET consists of n+type source and drain regions 10 formed in the p--type layer where no well region is formed, a gate insulation film 12, and a polycrystalline silicon layer 15 that serves as a gate electrode.

Figs. 2A to 2H are diagrams illustrating the process for producing the integrated circuit of Fig. 1. Complementary MISFETs are formed in the area X1, and 12 L elements are formed in the area X2.

Referring to Fig. 2A, first, n-type impurities such as arsenic impurities are selectively introduced into a predetermined portion of a ptype silicon substrate 1 by diffusion tech- niques or ion implantation techniques, and ptype doped silicon is deposited on the substrate by epitaxial growth to form a p--type layer 2 (impurity concentration N: 1015 atoms /CM3). At the same time, an n ±type buried layer 16 is also formed owing to the diffusion of the n-type impurities.

As shown in Fig. 2B, an n-type well region 4 is selectively formed in the p --type 2 in order to form p-channel MISFETs. In order to selectively form the n-type well region 4, an oxide film 30 of a thickness of 500 angstroms is first formed by thermal oxidation on the whole surface of the p-type epitaxial layer 2, and an S'3N, film 31 of a thickness of 1500 angstroms is formed thereon by the chemical vapor deposition method (hereinafter referred to as the CVD method). Then the oxide film 30 on that portion where the n-type well region is to be formed and the Si3N, film 31, are selectively removed by plasma etching using a photoresist film (not shown) as a mask, such that the surface of the p-type epitaxial layer 2 is exposed. Masks for forming all the n-type well regions are completed in this step so that all the positions of all the well regions are determined by the masks. Thereafter, the windows for forming the ntype well regions that form the low-concentration 12 L are covered with a suitable mask such as a thick photoresist film 32 as shown in Fig.

2 GB 2 154 060A 2 2B, and n-type impurities such as phosphorus ions are implanted (N: 1016 atoMS/CM3) to form the n --type well region 4 which has a low impurity concentration. Although the impurity concentration is low, the well region 4 should preferably be formed by the ion implantation method since it is possible to control the concentration precisely.

Then, the low-concentration n-type well re- gion 3 is formed as shown in Fig. 2C. After the photoresist film 32 is removed, the n-type well region 4 is covered with a thick photoresist film 33, and n-type impurities such as phosphorus ions are implanted (N: 107 atoms/ CM3) to form the low-concentration ntype well region 3. The well region 3 should preferably be formed by the ion implantation technique since it is possible to control the impurity concentration precisely as mentioned above.

A field oxide film is then formed as shown in Fig. 2D. After the photoresist film 33, the Si,N4 film 31 and the SiO, film 30 are removed in succession, an oxide film (S'02 film) 34 of a thickness of 500 angstroms is formed by thermal oxidation on the exposed surfaces of the epitaxial layer 2, and then an S'3N4 film 35 of a thickness of 1500 angstroms is formed by the CVD method. The SO, film 35 is then selectively removed by plasma etching using a photoresist film (not shown) as a mask, so that the Si02 film 34 is partially exposed. To prevent the formation of an inversion layer under the field oxide film under this condition, p-type impurities such as boron ions are implanted while the photoresist film is still in place. The photoresist film is then removed, and a field oxide film (Si02 film) 17 is formed by thermal oxidation to a thickness of 9000 angstroms using the SO, film 35, which is not permeable to oxygen, as a mask.

Then, as shown in Fig. 2E, the gate insulation films and the gate electrodes of the MISFETs are formed. After the S'02 film 34 and the SO, film 35 are removed, a gate insulation film (Si02 film) is formed to a thickness of 500 angstroms by thermal oxidation on the whole surface of the exposed epitaxial layer 2. A polycrystalline silicon layer is then formed to a thickness of 3500 angstroms on the whole surface of the substrate by the CVD method. Phosphorus impurities are introduced into the polycrystalline silicon layer by diffusion to decrease its sheet resistance to such a level that it can be used as gate electrodes. To complete the gate electrodes, the polycrystalline silicon layer and the gate insulation film are selectively removed by plasma etching using a photoresist film as a mask. The gate insulation films 11, 12 and the gate electrodes 14, 15 of the MISFETs are thus completed. At the same time, the surface of the epitaxial layer 2 on the 12 L side is exposed.

Next, a p-type semiconductor region is formed as shown in Fig. 2F. First, to prevent the exposed epitaxial layer 2 from being contaminated, an S'02 film 25 is formed to a thickness of 100 to 200 angstroms by thermal oxidation on the surface of the epitaxial layer 2, and also on the surfaces of the polycrystalline silicon layers 14, 15. Then an Si02 film 36 is formed to a thickness of 1500 angstroms by the CV1) method. The S'02 film 36 is selectively removed by plasma etching using a photoresist film (not shown) as a mask, to complete the mask for forming the ptype regions. When forming the mask 36, the processing with photoresist does not require so high a precision. That is, the mask may be slightly shifted provided that its ends 36a, 36b and 36c are on the field oxide film 17. Then p-type impurities such as boron ions are implanted (or diffused) into the surfaces of the n-type well regions 3, 4 not covered by the polycrystalline silicon layer 14, the field oxide film 17 and the mask 36, in order to form the p-type regions 5 and 6 that serve as the injector and base of the 12 L, and to form the p±type source and drain regions 9 of the pchannel MISFETs. As will be obvious from Fig. 2F, the p- type region 5 is self-aligned by the field oxide film 17, and the p' -type source and drain regions 9 are self-aligned by the field oxide film 17 and by the polyerystalline silicon 14.

Next, as shown in Fig. 2G, n-type semiconductor regions are selectively formed in the epitaxial layer 2 and in the n-type well region 3. First, the S'02 film 36 is removed, and a new Si02 film 37 is formed to a thickness of 1500 angstroms by the CV1) method. The Si02 film 37 is then selectively removed by plasma etching using a pkotoresist film (not shown) as a mask, to complete the mask for forming the n-type regions. When forming the mask 37, the processing with photoresist does not require a high precision, as when forming the mask 36. Then n-type impurities such as phosphorus ions are implanted into the surface of the epitaxial layer 2 where the polycrystalline silicon layer 15 and the field oxide film 17 have not been formed, and into the surface of the well region 3 where the mask 37 and the field oxide film 17 have not been formed, thereby forming the emitter contact region 8 of the 12 L, and the n '-type source and drain regions 10 of the n- channel

MISFETs.

Next, an n-type collector region is formed as shown in Fig. 2H. That is, after the S'02 film 37 is removed, a new S'02 film 38 is formed to a thickness of 1500 angstroms by the CV1) method. The S'02 film 38 is then selectively removed by plasma etching using a photoresist film (not shown) as a mask, to complete the mask for forming the n-type collector region. Then n-type impurities such as phosphorus ions are introduced by implan- 3 GB 2 154 060A 3 tation (or diffusion) to form an n-type collector 7.

After the Si02 film 38 is removed, an Si02 film 18 (see Fig. 1) is formed on the whole surface of the substrate to a thickness of 1500 angstroms as an interlayer insulation film by the CVD method. After contact holes have been formed in theS'02 film 18, alumi num is deposited thereon to a thickness of 8000 angstroms by the vacuum evaporation method. The aluminum layer is patterned to the desired shape to form the aluminum elec trodies 19 to 24 that are in ohmic contact with each region. Thus, the CMISFET-12 L IC of the construction shown in Fig. 1 is completed. 80 According to this construction, use is made of a p--type silicon layer of a low impurity concentration as a substrate, and the 12 L cir cuit and the p-channel MISFETs are formed in the n-type well regions that are separately formed in the substrate. Therefore, the im purity concentration can be controlled for each of the well regions. By making the impurity concentration in the n-type well re gion 3 on the 12 L side greater than the im purity concentration of the well region 4, therefore, the inverse current amplification factor fli of the inverse transistors in the 12 L circuit can be enhanced to realize a 12 L which operates at high speeds and which consumes 95 a reduced amount of electric power. With the impurity concentration being made low in the n-type well region 4 on the p-channel MISFET side, furthermore, high-speed operation can be realized even when the gate width of the MISFET is reduced. Accordingly, the chip size can be reduced but the high-speed operation is maintained.

Further, as will be obvious from the method of manufacturing the integrated circuits ex- 105 plained in conjunction with Figs. 2A to 2H, the well regions 3, 4 are formed in the epitaxial layer 2 before forming the field oxide film 17 by the selective oxidation technique.

In the well region 4 constituting the 12 L, therefore, a field oxide film can be formed in the 12 L elements to prevent the formation of parasitic transistors. The surface of the well region 3 under such a thick field oxide film is difficult to invert. Therefore, a wide range of power-supply voltages can be applied, and increased freedom is provided for laying out the wiring. Further, the surface of the well region 4 is also difficult to invert. Accordingly, the above-mentioned advantages are brought about.

When forming the CMISFETs, furthermore, employment of the silicon gate processing technique makes it possible to obtain a CMIS FET-12L IC of a high density.

In order to obtain the CMISFET-12 L IC hav ing a complementary MISFET circuit which operates at high speeds and which is highly integrated, and an 12 L circuit which operates at high speed and which consumes a reduced amount of power, formed in the same substrate, (1) the complementary MISFET circuit which operates at speeds faster than the 12 L circuit should be disposed on the input stage of the integrated circuit, and the 12 L circuit should be disposed on the output stage, and (2) the output of the complementary MISFET circuit should be directly connected to the input of the 12 L circuit without an interface circuit being disposed therebetween.

Fig. 3 is a diagram showing the circuits of a CMISFET-12 L IC which is constructed by taking the above-mentioned points into consideration.

In Fig. 3, circuit I is a high-speed circuit consisting of a complementary MISFET circuit, circuit 11 consists of an 12 L circuit operating at speeds slower than circuit 1, and circuit I I I acts to bias the 12 L circuit. In Fig. 3, the symbol Qm denotes MISFETs, and in particular Qm11 and QM2, denote p- channel MISFETs, and QM12 and (IM22 denote n-channel MISFETs. Symbol Q, denotes transistors that constitute the 12 L circuit. In particular, Q111 and QM denote lateral transistors, and Q,12 and Q,32 denote inverse transistors.

Input signals V, from an external source are first received by circuit 1. Circuit I is made up of, for example, an input protection circuit consisting of an input protection resistance R and an input protection diode D, a first-stage inverter consisting of MISFETs Q,11 and QM12, a signal processing circuit (not shown) which is connected thereto, and a final-stage inverter consisting of MISFETs QM2, and QM22 sending the output of the signal processing circuit to the 12 L circuit. Therefore, the input signal V, passes through the input protection circuit and the first-stage inverte7r, and is suitably processed at high speeds in the signal processing circuit, and the processed result is produced from the final-stage inverter in circuit 1.

The output terminal of the final-stage inver- ter is directly connected to the input terminal of circuit 11 without passing through an interface. Therefore, the output signal from the complementary MISFET circuit (circuit 1) is directly supplied to the 12 L circuit (circuit 11).

Circuit 11 is made up of, for example, a firststage inverter consisting of transistors Q,,, and Q,12, a signal processing circuit (not shown) connected thereto, a final-stage inverter consisting of transistors QM and Q,32 sending the output of the signal processing circuit to an external unit, and a load transistor Q, Therefore, the output from circuit I passes through the first-stage inverter of circuit 11, is suitable processed through the signal processing circuit, and the processed result is sent to an external unit via the final-stage inverter and via the load transistor Q, Fig. 4 is a plan view which schematically shows the layout of the connection between circuit I and circuit 11 of Fig. 3, and in which 4 cross-sections formed along the dot-dash chain lines X, X2 denote the same areas as the areas X, and X2 of Fig. 1. Further, the same parts as those of Fig. 1 are denoted by 5 the same reference numbers.

Thus, the circuit consisting of complementary MISFETs is placed on the input side of the integrated circuit, and circuit 11 comprising the 12 L is placed on the output side of the integrated circuit, because of reasons mentioned below. The complementary MISFET circuit operates at speeds faster than the 12 L circuit, and the speed of the integrated circuit can be increased as a whole if it is placed on the input side. Further, unlike the complemen- 80 tary MISFET circuit, the 12 L circuit can be current-d riven. - Placing the 12 L circuit on the output side, therefore, increases the number of fan-outs that can be obtained, other inte- grated circuits can be directly driven, and the performance of the integrated circuit can be enhanced.

Further, circuit 1 is directly connected to circuit 11 without an interface circuit, because of reasons mentioned below.

When the power-source voltage Vcc is 5 volts, the complementary MISFET circuit produces an output current over a range of 10 to 50 ItA and an output voltage over a range of from about 0 volt to about 5 volts. The 12 L circuit, on the other hand, allows the introduction of a current over a range of 10 to 500 gA, and voltage of 1 to 15 volts. When the two circuits are directly connected without an interface circuit, the operation will be as described below. When the MISFET QM21 is on, and the MISFET QM22 is not, i.e., when a high signal level (about 5 volts) is applied to the gate-connection point G, electric current flows from the power source Vcc to the 12 L circuit through MISFET QM21, and the potential rises at the base of the inverse transistor Q12 SO that it is turned on. Therefore, the output OUT of the first-stage inverter in the 12 L circuit goes low (about 0 volt). The current flows through the paths indicated by the arrows A potential nearly equal to Vcc is applied to the emitter of the transistor Q, via the 12 L bias circuit Ill. Therefore, when the MISFET QM21 is turned on, the base potential of the transistor Q12 instananeously rises, and part of tne current flowirig from the transistor GM21 to the 12 L circuit also flows from the collector to the base of the transistor Q, but does not flow to the emitter thereof. The current flow- ing in the other direction is so small that it can be neglected. This can be attributed to the high impurity concentration in the well region 3. When the MISFET QM22 is on (MIS FET QM21 is off), i.e. when a low signal level 125 (about 0 volt) is applied to the point G, the base of the transistor Q02 nearly reaches the ground potential so that it is turned off, and the output of the first-stage inverter in the 12 L circuit becomes a high signal level. Namely, 130 GB 2 154 060A 4 the current flows through the path indicated by the arrow (Z) In this case, the current taken by the complementary MISFET circuit from the 12 L circuit can be absorbed by suitably setting the ratio W/L of the gate width to gate length of the MISFET QM22. Because of these reasons, the complementary MISFET circuit can be directly connected to the 12 L circuit without using an interface circuit.

According to the above-mentioned embodiment, the following effects can be obtained.

(1) The 12 L elements and the p-channel MISFETs are respectively formed in different semiconductor regions, i.e. in different well regions formed at different steps. Therefore, the impurity concentration of each well region can be controlled independently.This makes it possible to slightly increase the impurity concentration in the well region where the 12 L circuit is formed, and to slightly decrease the impurity concentration in the well region where the p-channel MISFETs are formed. Accordingly, it is possible to form an 12 L circuit which operates at high speeds consum- ing a reduced amount of electric power, and a complementary MISFET circuit which operates at faster speeds and which is highly integrated on the same semiconductor substrate. Therefore, a CMISFET-12 L IC is obtained which features high-speed operation, low power consumption, and a high degree of integration.

(2) The well region and the semiconductor substrate have a reversed bias relationship or are at the same potential, so that no isolation region is needed to insulate and separate these regions. This means that the degree of integration can be increased accordingly.

(3) The n-type well region for forming the 12L circuit, the. p-type epitaxial layer for form- ing the n-channel MISFETs and the p-type substrate can be maintained at the same potential (ground potential), to prevent the development of parasitic bipolar transistors. Therefore, the reliability of the integrated cir- cuit can be increased. Further, since the distance between the semiconductor regions does not need to be increased to prevent the formation of parasitic bipolar transistors, the integrated circuit can be easily designed, maintaining an increased degree of integration.

(4) Since the complementary MISFET circuit is directly coupled to the 12 L circuit without any interface circuit, the chip area can be reduced to simplify the design.

(5) A complementary MISFET circuit operates faster than a 12 L circuit. By placing the complementary MISFET circuit on the input side, therefore, the operating speed of the integrated circuit can be increased as a whole. By placing the 12 L circuit on the output side, furthermore, an increased number of fan-outs can be obtained, making it possible to directly drive other elements.

(6) The output characteristics of the inte- GB 2 154 060A 5 grated circuit are greatly improved by provid ing the final output stage of the 12 L circuit with a load transistor QL equivalent to a pull up resistance, as shown in Figs. 3 to 5. That is, provision of the load transistor (IL (a) eliminates the need for attaching an external pull-up resistor for the integrated circuit, and hence enables the integrated circuit to be directly connected to other transistors and integrated circuits, (b) helps increase the abil- 75 ity for driving other integrated circuits (helps increase fan-outs), and (c) helps eliminate the defect that when the external pull-up resis tance is employed, the resistance must be increased with any increase in the power- 80 supply voltage Vc, resulting in an increase in the consumption of electric power through the resistance.

Further, as Fig. 5 schematically illustrates the layout, the load transistor Q, can be easily 85 formed by providing a pl-type region 40 simultaneously with the formation of other p±type region 6 in the n-type well region 3 in which the 12 L circuit is formed, i.e. the load transistor QL can be formed as a pnp lateral transistor which consists of the region 40 and the injector region 5, without modifying the manufacturing conditions or process, and without needing any particular design require ments.

(7) As shown in Fig. 3, an increased cur rent can be passed into the transistor Q,12 of the first stage of the 12L circuit (the current flows from the MISFETs QM21, Q11 as indi cated by the arrows (D to increase the operat- 100 ing speed of the transistor Q,12, and to reduce the frequency loss when signals are transmitted from the complementary MISFET circuit to the 12 L circuit.

The present invention, however, should in no way be limited to the abovementioned embodiment only.

Fig. 6 is a diagram which illustrates another embodiment of the present invention, in 46 which the same parts as those of the first embodiment are denoted by the same reference numbers.

This embodiment does not employ the lateral transistor Q,,, (the injector with respect to the transistor Q,12) in the first stage of the 12 L circuit that was employed in the first embodiment. The construction of the other parts is the same as that of the first embodiment.

The operation in the past where the complementary MISFET circuit I is connected to-the I'L circuit 11 in the integrated circuit is described below. When the p-channel MISFET QM21 is on (the n-channel MISFET QM22 is Off), current flows from the power source Vcc to the 12 L circuit 11 via MISFET QM211 so that the base potential of the inverse transistor Q02 rises. Therefore, the transistor Q,12 is turned on, and the first-stage inverter consisting of the tran- sistor Q,12 produces a low-level output. The current runs from the power source Vc, to ground via the MISFET QM21 and transistor Q,121 Conversely, when the MISFET QM22 is on (MISFET QM21 is off), a discharge current flows from the base of the transistor QH2 to ground via the MISFET QM22, and the potential at the base of the transistor Q,12 nearly reaches ground potential. Consequently, the transistor Q,12 is turned off, and the inverter of the first stage produces a high-level output. In this case, therefore, only a discharge current flows from the transistor (IM to ground via MISFET QM22, and no steady-state current flows.

This embodiment makes it possible to obtain the same effects as (1) to (16) obtained with the first embodiment. When the MISFET QM22 is turned on, no steady-state current flows through the first stage of the 12 L circuit, enabling the consumption of power to be further reduced.

Fig. 7 is a diagram illustrating a further embodiment according to the present invention, in which the same parts as those of the first embodiment are denoted by the same reference numbers.

This embodiment does not employ the pchannel MISFET Q.21 in the inverter in the final stage of the complementary MISFET cir- cuit that was used in the aforementioned first embodiment. In all other respects, however the construction is the same as that of the first embodiment. The operation in the part where the complementary MISFET circuit I is connected to the 12 L circuit 11 in the integrated circuit is now explained. When the p-channel MISFET (IM22 is off, no current path is formed from the lateral transistor Q,11 to the complementary MISFET circuit 1, the transistor Q, is saturated. Therefore, the base potential of the transistor Q,12 rises so that it is turned on, and the first-stage inverter produces a low-level output. The current runs from the power source Vcc to ground via the 12 L bias circuit 111, and transistors Q,11 and Q,12' When the nchannel MISFET QM22 is on, the circuit operates in the same manner as in the first embodiment. This embodiment also makes it possible to obtain the same effects as (1) to (6) of the first embodiment.

The invention can further be modified in a variety of other ways in addition to the abovementioned embodiments. In the above-mentioned embodiments, for instance, the n±type buried layer 16 may be eliminated. In this case, the n-type well regions 3 and 4 may be formed in the p--type silicon substrate 1 without forming the p-type epitaxial layer 2. Further, the high impurity concentration ntype well region where the 12L circuit will be formed, may be formed in the following manner. Ions are implanted simultaneously with the formation of the n-type well region 4 where the p-channel MISFETs will be formed, and ions are again implanted into the well 6 GB2154060A 6 region 3 while the well region 4 is covered by a mask. The above- mentioned order may of course be reversed. Further, the conductivity types of the semiconductor regions may be 5 reversed.

Fig. 8 shows a complementary MISFET-12 L IC according to a still further embodiment of the present invention. According to this embodiment, unlikethe aforementioned embodi- ments, the 12 L circuit is formed in an epitaxial layer that is grown on the substrate, the nchannel MISFETs are formed in the epitaxial layer, in order to increase the local impurity concentration in the epitaxial layer where the 12L circuit will be formed. That is, use is made of epitaxial layers that are insulated and separated as semiconductor regions that correspond to the well regions in the aforementioned embodiments, and the impurity con- centrations are changed.

According to this embodiment as shown in Fig. 8, a low-concentration p-type epitaxial layer 52 is allowed to grow on an n --type silicon substrate 51 having a low impurity concentration. The p--type epitaxial layer 52 is separated by an n-type isolation region 62 into the area X, where the complementary MISFETs will be formed and the area X2 where the 12 L circuit will be formed. P-type impurities such as boron ions are implanted in 95 a part 53 of the p-- type epitaxial layer 52 having a low impurity concentration in the area X2, to increase the impurity concentration. An n1-type injector region 58, and an inverse transistor consisting of n I -type base region 59, an emitter electrode contact region and an emitter region 52, are formed in the region 53 thereby forming an 12 L circuit.

N-channel MISFETs consisting of n '-type source and drain regions 56, a gate insulation 105 film 66 and a polycrystalline silicon layer 67 that serves as a gate electrode, and p-channel MISFETs consisting of pl-type source and drain regions 57, a gate insulation film 63 and a polycrystalline silicon layer 64 that serves as a gate electrode in the n-type well region 54, are formed in the low impurity concentration epitaxial layer 52 in the area X, thereby forming a complementary MISFET cir- cuit.

According to this embodiment, it is also possible to form a complementary MISFET circuit which operates at high speeds and which can be highly integrated, and an 12 L circuit which operates at high speeds consuming a reduced amount of electric power on the same substrate, just like the first embodiment. To obtain these advantages sufficiently, the connections should be realized as in Fig. 9.

In Fig. 9, symbols Q,T denote tran- sistors which correspond to Q of Fig.

3, and which have opposite types of conductivity. Therefore, the relationship of the potential is reversed relative to Fig. 3. That is, the collector (the epitaxial layer 52) of the inverse transistor QIj-2 has a potential of 0.7 volt that is supplied through the 12 L bias circuit III, and the base of the lateral transistor Q,T-, in the same region (in the epitaxial layer 52) has a potential of 0.7 volt that is supplied by the 12 L bias circuit Ill. The injector region which is the emitter of the lateral transistor Q,T-, has been grounded. The potential in the p--type epitaxial layer in the region X, where the complementary MISFET circuit is formed is at ground potential. Therefore, the p-type epitaxial layer 52 is isolated by the n --type semiconductor substrate 51 and by the n-type isolation layer 62, as shown in Fig. 8.

The operation of the part where the complementary MISFET circuit I is connected to the 12 L circuit 11 in the integrated circuit is now described. When the p-channel MISFET CIM21 is on (MISFET QM22 if off), the base potential of the transistor Q,i-2 rises above 0.7 volt, the transistor Q172 is turned off and the first-stage inverter of the 12 L circuit 11 produces a highlevel output. When the n-channel MISFET QM22 is on (MISFET QM21 is off), the base of the transistor QTy nearly reaches ground potential, i.e. the transistor Q, i-2 is turned on, and the first-stage inverter produces a lowlevel output. The current runs from the 12 L circuit 11 to ground via the transistors Q,-,T, QM22. This embodiment makes it possible to obtain the same effects (1), (4), (5) and (6) as mentioned above.

This application was divided out of U.K. Patent Application No. 82.27060 (Published under No. 2107117) and describes matter also described in that application. Also divided out of that application was U.K. Patent Application No. these applications.

- Attention is drawn to

Claims

1. A semiconductor integrated circuit device having a first circuit consisting of 12 L elements and a second circuit consisting of MISFETs, that are formed in a single semiconductor substrate, wherein said second circuit is arranged on the input side of the semiconductor integrated circuit device, said first circuit is arranged on the output side of said semiconductor integrated circuit device, and the output of said second circuit is directly input to said first circuit.

Printed in the United Kingdom for Her Majesty's Stationery Office. Dd 8818935. 1985, 4235Published at The Patent Office. 25 Southampton Buildings. London, WC2A lAY, from which copies may be obtained.