GB2150778A - Electromagnetic relay control circuits - Google Patents

Abstract

A relay has series coils 1 and 2, coil 2 being shorted by switch SW1 during initial actuation. Coil 2 is of high resistance to provide a low holding current and may be replaced by a resistance. A semi-actuated state is prevented by logic element L1 monitoring the voltage applied to coil 2: if this is below a predetermined level, logic element L2 is operated to disable the relay for a time period determined by delay network R6, C2. The power required to maintain the relay after actuation is minimised by the connection of the collector of TR1 to the junction point of coils 1 and 2. <IMAGE>

Description

SPECIFICATION Electromagnetic relay control circuits -Thi & invention relates to circuits for controlling electromagnetic relays.

The invention is particularly (but not exclusively) applicable to relays used in conjunction with microprocessors and using the microprocessor power supply. The capacity of such a power supply is limited and-the use of relays controlled in a conventional' manner may cause overloading. The present invention seeks to alleviate problems caused by this.

An electromagnetic relay requires more electromagnetic power for its initial actuation than to maintain it in the actuated state. The electrical power drain in the on state may be reduced either by connecting a resistor in series with the actuating coil after the initial activation or by using a double wound actuating coil with the second holding coil switched into circuit after actuation. The power consumed during initial switch on may be supplied from a reservoir capacitor and the instantaneous or pulsed electrical load on the power supply may be reduced via a resistor. Fig. 1 shows such a circuit actuated via a transistor TR2. !n Fig. 1 coil 1 is the actuating coil.Coil 2 is the holding coil switched into circuit by the normally closed contacts SW1 (or by a timing circuit, not shown). C1 is the reservoir capacitor and R3 is the power supply load reduction resistor.

One aspect of the invention relates to circuitry additional to the above which acts to- prevent an undesirable condition which may develop during the operation of the circuit of Fig. 1. The undesirable condition is a semi-actuated state of the relay in which the actuating coil 1 provides insufficient energy to fully actuate the relay and open relay contacts SW1. In this condition the actuating switch device (in this semi-switched case TR2) is in the on condition and the voltage at point A has fallen below the actuating or holding voltage levels ensuring that the device can only recover from this condition by turning off the actuating switch TR2 for such a time period as to allow C1 to charge up via R3 and the supply voltage to such a level that the relay will switch normally.In normal operation the device described in Fig. 1 can be put into the undesirable semi-energised state by either switching the actuating switch TR2 too frequently or by initial powering up the supply line with the actuating switch in the on condition.

The circuit shown in Fig. 2 acts to prevent the undesirable semi-actuated state from persisting whilst the actuating switch TR2 remains on.

The action of the circuit is to detect the undesirable low voltage level at point A via logic element L1 and then switch off the actuating switch via logic element L2 and the D5, R4 network. This switching action over-rides any on signal voltage present at the point marked in-put voltage. The network D8, R6 and C2 act to ensure that the actuating switch TR2 remains in the off state until the voltage at point A has recovered sufficiently for the relay to be successfully actuated.

Logic element L1 acts as a voltage load detection and may be either a CMOS or a TTL logic gate with or without hysteresis, or a discrete circuit using bipolar, field effect or other similar semi-conductor devices. The logic element L1 may also itself be an electromagnetic relay. The network D8, R6 and C2 acts as a time delay network and may be any time delay element. If the voltage level detection at point A is sufficiently precise with an appropriate hysteresis the time delay network may be dispensed with. Logic element L2 is any logic element capable of switching the actuating switching TR2 off, for example, any of the types described for logic element L1. D5 sets to isolate logic element L2 when the recovery circuitry is not activated.D5 may be dispensed with if logic element L2 has a suitable isolated output when in the non-activated state (for example, if logic element L2 is an electromagnetic relay or an open collector output TTL integrated circuit).

The switching element TR2 has been shown as an n-p-n transistor, but another switching element may be used, for example an n-p-n transistor or field effect device or another electromagnet relay.

Suppression devices may be fitted to the Coils 1 and Coils 2 without altering the substance of the circuit. Coil 2 may be replaced with a resistor of appropriate value. The advantage of Coil 2 over using a resistor is one of energy efficiency. The replacement of Coil 2 by a resistor does not however, fundamentally change the operation of the circuit as described herein and so does not alter the substance of this application.

Another aspect of the present invention minirnises the electrical energy required to hold the relay in the energised condition.

The novel feature of this circuit is the connection of the collector of transistor TR1 via resistor R5 to the point marked X in Fig. 3. The action of the device is as follows.

The contacts marked SW1 are part of the relay which has a split energised coil marked Coil 1 and Coil 2. When the relay is energised contacts SW1 open providing an electrical disconnection V in is such as to render TR1 and TR2 in non-conducting states. When appropriate energising potential is applied at V1, TR1 and TR2 will conduct provided the supply voltage is appropriate. Ri is of such a value as to adequately limit the current flow through the emitter base junctions of TR1 and TR2.

In the initial energising condition SW1 is closed thus short circuiting coil 2. The full supply voltage is thus present at point X and the current through R5 and TR1 energises TR2 through its base to emitter junction. TR2 thus conducts allowing current to flow through Coil 1 and energising the relay thus opening contacts SW1. The effect of opening contacts SW1 is to bring into circuit Coil 2 which reduces the voltage at X and hence the current through the transistor TR1. Coil 1 and Coil 2 may be arranged such that they wili supply sufficient magnetising force to hold the relay in an energised condition.Electromagnetic relays are devices which require more electromagnetic force to establish energisation than to maintain energisation thus Coil 1 and Coil 2 may be wound with physically different wire and be of different resistance and provide different electromotive force.

The effect of the interconnection of transistor TR1 and resistor R5 to the point X is to allow the emitter to base drive of TR2 to be decreased once the relay has switched.

In a practical embodiment of the invention, Coil 2 is of considerable higher electrical resistance than Coil 1 allowing the voltage at X to drop to such a low value that TR1 is not conducting in the energised state, rather the base-emitter drive of TR2 is supplied via the base-emitter junction of TR1 and R4. R4 is of relatively high value compared to either Coil 1 or Coil 2 and R5 is zero i.e. a short circuit. The overall operation of the device is to allow a voltage at V in to energise the relay but supply relatively little power to the circuit. The relay is maintained in the energised condition with relatively low energy compared to a relay energised without this novel feature.

The circuit illustration shows n-p-n transistors which are used in the associated working model. pn-p transistors or any appropriate electronic switching device including field effect devices may be used in place of the n-p-n transistors shown without altering the substance of the arrangement.

Suppression devices may be fitted to the Coils 1 and Coils 2, for example as shown in Fig. 4.

Coil 2 may be replaced with a resistor of appropriate value, as discussed in relation to Fig. 2.

Fig. 5 illustrates a practical embodiment of the invention utilising the features of Figs. 2 and 3 discussed above.

Claims (10)

1. An electromagnetic relay arrangement including a relay having an actuating coil and one or more pairs of contacts, and holding means for maintaining the contacts in the condition to which they are switched by the actuating coil; characterised by circuit means for preventing semiactuation, comprising voltage sensing means arranged to detect the voltage applied to the holding means, and de-actuating means responsive to said voltage being below a predetermined level to de actuate the relay for a predetermined time.

2. The arrangement of claim 1, in which the voltage sensing means is a logic element.

3. The arrangement of claim 2, in which the logic element is a SMOS or TTL logic gate.

4. The arrangement of any preceding claim, in which the de-actuating means comprises a logic element and a time-delay network.

5. A control circuit for an electromagnetic relay having a first coil and a second coil connectable in series across a supply, the circuit comprising normally closed switch means connected across the second coil and arranged to be opened after initial energisation of the relay, solid-state switching means in series with the coils, and a transistor having a control electrode arranged to receive an actuating signal and having a main current path connected between a control electrode of the solidstate switching means and the junction of the coils, whereby after initial actuation the switch means opens to bring the second coil into circuit thus producing a relatively low voltage at said junction to provide a relatively low holding current through the transistor.

6. The circuit of claim 5, in which the second coil has a resistance which is considerably higher than that of the first coil and the solid-state switching means is a further transistor, the coil resistances being such that said low voltage at said junction supplies the base-emitter drive of the further transistor via the base-emitter junction of the first transistor with the latter not in the energised state.

7. An electromagnetic relay apparatus comprising the arrangement of claim 1 in combination with the control circuit of claim 5.

8. An electromagnetic relay arrangement as claimed in claim 1 and substantially as hereindescribed with reference to Fig. 2 of the drawings.

9. A control circuit as claimed in claim 5 and substantially as herein described with reference to Fig. 3 or Fig. 4 of the drawings.

10. An electromagnetic relay apparatus as claimed in claim 7 and substantially as illustrated in Fig. 5 of the drawings.