GB2145574A - Multi-layer printed circuit boards - Google Patents
Multi-layer printed circuit boards Download PDFInfo
- Publication number
- GB2145574A GB2145574A GB08421094A GB8421094A GB2145574A GB 2145574 A GB2145574 A GB 2145574A GB 08421094 A GB08421094 A GB 08421094A GB 8421094 A GB8421094 A GB 8421094A GB 2145574 A GB2145574 A GB 2145574A
- Authority
- GB
- United Kingdom
- Prior art keywords
- circuit board
- glass
- printed circuit
- pins
- polyimide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011521 glass Substances 0.000 claims abstract description 36
- 239000004020 conductor Substances 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000005476 soldering Methods 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 21
- 230000007704 transition Effects 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 239000005340 laminated glass Substances 0.000 description 4
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0154—Polyimide
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/0949—Pad close to a hole, not surrounding the hole
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1377—Protective layers
- H05K2203/1394—Covering open PTHs, e.g. by dry film resist or by metal disc
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/17—Post-manufacturing processes
- H05K2203/176—Removing, replacing or disconnecting component; Easily removable component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
A multilayer printed circuit board, in which the risk of damage during removal and replacement of components is reduced, is formed from layers of epoxy-glass carrying conductors (6,7). Connection pins (3) of components (2) mounted on a face of the circuit board (1) extend through holes (8) in the circuit board (1) and protrude from the opposite face. A polyimide-glass layer (13) covers the opposite face of the circuit board (1) and carries conductive pads (9) for connection to the ends of the pins (3) by means of solder (14). The polyimide-glass (13) has a higher transition temperature (260 DEG C-280 DEG C) than that of the epoxy-glass (120 DEG C) so that it suffers minimal loss of adhesion to the pads (9) at the temperature of the molten solder (220 DEG C-250 DEG C). <IMAGE>
Description
SPECIFICATION
Improvements in or relating to printed circuit boards
Background to the invention
This invention relates to printed circuit boards, and especially to printed circuit boards which facilitate the removal and replacement of components.
It is common to mount complex electronic components on printed circuit boards by inserting pins of the components into plated through-holes of the circuit and soldering them in place. The plated through-holes normally provide connections between the pins and conductive material forming part of the circuit and situated at different levels of the board, which is usually fabricated of epoxyglass material.
If it is necessary to remove a component, for example to replace it because it is faulty, it is found that the heat used to melt the solder tends to cause the board to expand and damage thTT circuitry of the board. The problem is especially serious with modern verylarge-scale integrated-circuit components mounted in so-called pin grid array packages.
Th large number of densely packed pins in such an array (typically above 100) requires the solder for all the pins to be melted simultaneously if the process is not to be inconveniently long. The great amount of heat that is therefore applied, and the relatively great thickness of the board which is needed to provide the large number of interconnections required, then exacerbate the expansion problem and hence the damage to the board. Yet, because those components are expensive, it is all the more desirable to repair a board rather than to discard it. It has indeed been suggested that the only solution to the problem is to use sockets, which are soldered into the board. The components are then plugged into the sockets, but this method increases both the cost and the bulk of the board and may decrease reliability.
Summaries of the invention
The invention provides a multilayer printed circuit board including alternate layers of epoxy-glass and conductive material; a polyimide-glass layer on one face of the circuit board; and conductive pads on the outer face of the polyimide-glass layer for connection to component connection pins; the arrangement being effective to reduce the risk of damage to the circuit board during removal and replacement of components mounted thereon.
The invention also provides a method of manufacturing a multilayer printed circuit board assembly including the steps of; forming a stack by bonding together a plurality of epoxy-glass layers carrying conductive portions and an overlying layer of polyimide-glass having conductive areas including conductive pads on its outer face; locating a component having connection pins on the circuit board so that at least some of the connection pins engage said conductive pads; and soldering the pins to the pads.
Advantageously a substantially complete layer of conductive material extends between the polyimide-glass layer and the adjacent epoxy-glass layer.
Preferably the polyimide-glass and epoxyglass layers are pre-cured and bonded by completing the cure of sheets of pre-preg interleaved between the said layers, one sheet of pre-preg being adjacent to the said substantially complete layer of conductive material.
Brief description of the drawings
A printed circuit board constructed in accordance with the invention will now be described in greater detail, by way of example, with reference to the accompanying drawing, in which:
Figure 1 is a section through a part of the board, also showing a part of a mounted component;
Figure 2 is a plan view (without the component) of the part of the board shown in Figure 1 as seen from above; and
Figure 3 is a diagram showing the dispositions of holes in a region of a board associated with an individual component.
Description of preferred embodiment
Referring to Figures 1 and 2, the board, indicated generally by the reference numeral 1, is shown carrying a component 2. The component 2 is a pin grid array package having a large number of pins (e.g. 135 or 179) of which only one pin 3 is shown.
The board 1 is a multilayer board (not all the layers being shown) and contains, as is well known, conductive material in internal layers inter-connected by plated throughholes. One such hole, a hole 4 is shown, having plating 5. The internal layers may be voltage (i.e. earth or power) planes or signal planes. A plane 6 is an example of a voltage plane, which consists of a substantially uniform layer of conductive material that makes contact with some through-holes but is perforated to allow others to pass through it without making contact. The signal planes contain various conductive tracks, such as track 7 shown as an example making contact with the plating 5 of the hole 4. It will be realised that many other layers will be provided for a board that carries pin-grid array packages.
Plated through-holes, such as the hole 4, do not carry pins of a component. Instead such pins are carried by holes such as a hole 8 shown carrying the pins 3. These holes are free of plating on their internal walls.
The mouth of the hole 8 at the face of the board 1 remote from the component 2 is surrounded by a pad 9. The pad 9 is connected by a surface track 10 to a pad 11, surrounding the mouth of the hole 4 and connected to its plating 5. In this embodiment each other non-plated hole is similarly linked to a plated through-hole.
A layer 12 of solder resist is applied to cap all the plated through-holes but leaves the pad 9 and all other pads round non-plated holes exposed.
The bulk of the board is constructed from epoxy-glass in which are situated the conductive layers. The boundary of the epoxy-glass is the voltage plane 6, on the other side of which is a layer of polyimide-glass 13.
To mount a component, its pins are inserted in the non-plated holes and the face containing the pad 9 and similar pads is moved relative to a tin-lead solder wave, which leaves a a fillet 14 of solder connecting the pad 9 to the pin 3 and similarly connects the other pins to the board. Solder does not enter nonplated holes to any appreciable extent and is kept out of plated through-holes by the solder resist 12, which also acts as a thermal barrier.
If it is then desired to remove a component the board is suspended above a tin-lead solder wave, the solder of all the pins of the component melted and the component removed.
After the component has been removed any solder bridging the holes is gently blown away before it has solidified using air, which may be warmed. With the holes thus cleared a replacement component may then be inserted and soldered in place. If required the component at a given position may be changed a number of times. It will therefore be realised that economical repair or modification of the board is facilitated.
It is found that a pin grid array package may be unsoldered and removed in three to five seconds and with negligible damage to the board. This may be compared with the situation when the pins of the package are soldered in plated through-holes of a board that is constructed using epoxy-glass as the dielectric throughout. It is then found that it takes some 10 seconds to melt the solder, and even if the solder of each pin is melted individually and removed by suction it is found that damage occurs at a considerable number of holes. The damage consists usually of pads lifting round their peripheries and possibly of the joints between internal conductive layers and the hole plating fracturing.It occurs because the length of time the board is exposed to the temperature of molten tin-lead solder (220 C to 250on) coupled with the efficient path for conduction of heat afforded by the solder in the holes results in the temperature of the epoxy-glass material in the interior of the board rising above its transition temperature of 1 20 C. Above this temperature its rate of expansion rises rapidly and the expansion of the epoxy-glass material in the direction across the board is greater than the expansion of the conductive material. At the same time the adhesion between the conductive material (normally copper) and the epoxyglass material is much reduced.
The function of the polyimide-glass layer 1 3 will now be explained. Polyimide-glass material has a transition temperature of 260 C to 280 C. It therefore suffers minimal loss of adhesion to pads at the temperature of 220' to 250' of the solder wave, and the pads have good adhesion to the polyimide-glass layer. Consequently they do not lift to any appreciable extent even though they no longer have the anchorage previously provided by the internal plating. However, the bulk of the board is of epoxy-glass, which is cheaper than polyimide-glass and thus reduces the total cost of the board.
Copper-clad polyimide-glass laminate is available as a commercial item. This allows the board of Figure 1 to be manufactured in a simple manner. The necessary epoxy-glass laminates are prepared in the conventional manner used for the manufacture of multilayer boards. Similarly a polyimide-glass laminate is given the pattern of the voltage plane 6.
These laminates are assembled in a stack with the polyimide-glass laminate as one outer layer and having the plane 6 facing inwards.
The laminates are interleaved with sheets of pre-preg (partially cured epoxy-glass) and the whole bonded together by heating to complete the cure, which requires only the lower temperatures and shorter times appropriate to epoxy-glass rather than those required for polyimide-glass. It should be noted that the plane 6 is thus bonded to one of the sheets of pre-preg and no substantial regions of epoxyglass and polyimide-glass are in contact, thus overcoming problems which can occur if joints between these materials must be relied on.
Outer conductive patterns are then defined and holes to be plated are drilled. The board is then plated, following which non-plated holes are drilled and solder resist applied.
Figure 3 illustrates one possible disposition of holes for a pin grid array package having pins arranged in four concentric squares. Nonplated holes 20 for these pins similar to the hole 8 are in a region 21. Each of these holes is linked to an associated through-hole 22 similar to the hole 4 and either inside or outside the region 21. It will be appreciated that only a few of the holes have been shown in Figure 3. We prefer to connect each nonplated hole by a link to a plated through-hole in the interests of systematic design, but if desired tracks may run straight from one nonplated hole (i.e. pin) to another, for example on another component or an edge connector.
As examples of suitable dimensions the board may be 0.114 inches (2.896mm) thick, the polyimide layer 0.005 inches (0.127mm) thick, conductive layers 0.0014 inches (0.0356mm) thick and the solder resist 0.002 to 0.003 inches (0.0508 to 0.0762mm) thick. The pins may project 0.040 to 0.080 inches (1.016 to 2.032mm) beyond the surface of the board.
We have found that a composite board of epoxy-glass with an outer layer of polyimideglass as described is less subject to damage when a component is removed than an allepoxy-glass board, even if the pins are soldered in plated through-holes. It is then possible in certain applications, especially if the board is relatively thin, say up to 60 thou thick, to remove a component mounted in such a way by sucking solder from individual pins with no more than an acceptable amount of damage.
While the solder resist/thermal barrier gives added protection to the board integrity it may be omitted for applications where the reliability of the connections inside the hole is not at a premium.
Claims (7)
1. A multilayer printed circuit board including; alternate layers of epoxy-glass and conductive material; a polyimide-glass layer on one face of the circuit board; and conductive pads on the outer face of the polyimide-glass layer for connection to component connection pins; the arrangement being effective to reduce the risk of damage to the circuit board during removal and replacement of components mounted thereon.
2. A multilayer printed circuit board as claimed in Claim 1 including; a pattern of holes extending through the layers of the circuit board and arranged to receive the connection pins, at least some of the holes passing through said conductive pads.
3. A multilayer printed circuit board as claimed in Claim 1 or 2 in which a substantially complete layer of conductive material extends between the polyimide-glass layer and the adjacent epoxy-glass layer.
4. A method of manufacturing a multilayer printed circuit board assembly including the steps of; forming a stack by bonding together a plurality of epoxy-glass layers carrying conductive portions and an overlying layer of polyimide-glass having conductive areas including conductive pads on its outer face; locating a component having connection pins on the circuit board so that at least some of the connection pins engage said conductive pads; and soldering the pins to the pads.
5. A method of manufacturing a multilayer printed circuit assembly as claimed in Claim 4 including the further steps of; forming holes through the bonded layers to accommodate said connection pins, at least some of the holes passing through said conductive pads; locating the component on the circuit board so that the connection pins extend through the holes and the ends of the pins project beyond the conductive pads; and soldering the projecting ends of the pins to the pads.
6. A multilayer printed circuit board constructed as hereinbefore described with reference to the accompanying drawing.
7. A method of manufacturing a multilayer printed circuit board assembly as hereinbefore described with reference to the accompanying drawing.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB838322474A GB8322474D0 (en) | 1983-08-20 | 1983-08-20 | Printed circuit boards |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8421094D0 GB8421094D0 (en) | 1984-09-26 |
| GB2145574A true GB2145574A (en) | 1985-03-27 |
| GB2145574B GB2145574B (en) | 1986-04-09 |
Family
ID=10547638
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB838322474A Pending GB8322474D0 (en) | 1983-08-20 | 1983-08-20 | Printed circuit boards |
| GB08421094A Expired GB2145574B (en) | 1983-08-20 | 1984-08-20 | Multi-layer printed circuit boards |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB838322474A Pending GB8322474D0 (en) | 1983-08-20 | 1983-08-20 | Printed circuit boards |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPS6059799A (en) |
| AU (1) | AU571886B2 (en) |
| DE (1) | DE3428812A1 (en) |
| FR (1) | FR2550906B1 (en) |
| GB (2) | GB8322474D0 (en) |
| NL (1) | NL8402527A (en) |
| ZA (1) | ZA846089B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2207558B (en) * | 1987-07-11 | 1991-10-30 | Abdul Hamed | Printed circuit boards |
| GB2365630A (en) * | 2000-06-15 | 2002-02-20 | Murata Manufacturing Co | Multilayer circuit and method of manufacturing the same |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2551618B1 (en) * | 1983-09-02 | 1989-12-01 | Inf Milit Spatiale Aeronaut | METHOD FOR MANUFACTURING A PRINTED CIRCUIT WITH BURIED LAYERS AND PRINTED CIRCUIT OBTAINED BY SUCH A METHOD |
| DE102015111432A1 (en) * | 2015-07-15 | 2017-01-19 | Knorr-Bremse Systeme für Nutzfahrzeuge GmbH | Method for processing a mechatronic system for a commercial vehicle and a mechatronic system |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2650348A1 (en) * | 1976-11-03 | 1978-05-11 | Bosch Gmbh Robert | Electric component soldered on printed circuit board - using layer of nickel covered by gold to ensure strong soldered joint |
| BR8008696A (en) * | 1979-05-24 | 1981-04-14 | Fujitsu Ltd | MULTIPLE LAYER PRINTED CIRCUIT PANEL, HOLLOW, AND PROCESS FOR MANUFACTURING THE SAME |
| FR2476428A1 (en) * | 1980-02-15 | 1981-08-21 | Tech Electro Cie Indle | METHOD FOR FASTENING ELECTRONIC COMPONENTS ON A PRINTED CIRCUIT AND PRODUCT OBTAINED THEREBY |
| JPS5724775U (en) * | 1980-07-17 | 1982-02-08 |
-
1983
- 1983-08-20 GB GB838322474A patent/GB8322474D0/en active Pending
-
1984
- 1984-08-04 DE DE19843428812 patent/DE3428812A1/en not_active Withdrawn
- 1984-08-06 ZA ZA846089A patent/ZA846089B/en unknown
- 1984-08-17 AU AU32046/84A patent/AU571886B2/en not_active Ceased
- 1984-08-17 NL NL8402527A patent/NL8402527A/en not_active Application Discontinuation
- 1984-08-20 FR FR848412980A patent/FR2550906B1/en not_active Expired - Fee Related
- 1984-08-20 GB GB08421094A patent/GB2145574B/en not_active Expired
- 1984-08-20 JP JP59171699A patent/JPS6059799A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2207558B (en) * | 1987-07-11 | 1991-10-30 | Abdul Hamed | Printed circuit boards |
| GB2365630A (en) * | 2000-06-15 | 2002-02-20 | Murata Manufacturing Co | Multilayer circuit and method of manufacturing the same |
| GB2365630B (en) * | 2000-06-15 | 2002-12-24 | Murata Manufacturing Co | Multilayer circuit component and method for manufacturing the same |
| US6759115B2 (en) | 2000-06-15 | 2004-07-06 | Murata Manufacturing Co. Ltd | Multilayer circuit component and method for manufacturing the same |
| US7146719B2 (en) | 2000-06-15 | 2006-12-12 | Murata Manufacturing Co., Ltd. | Multilayer circuit component and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8421094D0 (en) | 1984-09-26 |
| FR2550906B1 (en) | 1992-09-04 |
| ZA846089B (en) | 1985-03-27 |
| GB8322474D0 (en) | 1983-09-21 |
| NL8402527A (en) | 1985-03-18 |
| JPS6059799A (en) | 1985-04-06 |
| GB2145574B (en) | 1986-04-09 |
| AU571886B2 (en) | 1988-04-28 |
| DE3428812A1 (en) | 1985-03-07 |
| FR2550906A1 (en) | 1985-02-22 |
| AU3204684A (en) | 1985-02-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20020820 |