GB2143399A - Digital video sync detection - Google Patents

Description

1 GB 2 143 399 A 1

SPECIFICATION

Digital video sync detection Background of the invention

The subject invention relates to improvements in video processing systems. The subject invention finds particular application in a slow scan digital video processor utilizing microprocessor techni- ques.

Prior art video signal processing systems for converting a video signal to digital format and storing frames of digital data are known. See U.S. Patent No. 4,148,070. Such video processors have typically used analog or a combination of analog and digital techniques to detect and regenerate sync signals required by the video format. It has appeared desirable to the inventors to devise a technique whereby the sync detection functions can be accom- plished in a microprocessor environment, avoiding as many analog functions as possible. Among the obstacles to implementing such a technique is the necessity to properly synchronize microprocessor operation to the incoming video signal. Without such synchronization improper storage of the video data will result.

It is therefore an object of the invention to provide a digital video sync detection technique for use with a microprocessor-based frame storage and trans- mission system. It is a further object of the invention to reliably synchronize microprocessor operation with incoming video sync signals.

The invention in its broadest aspect is defined in claim 1 below.

In the preferred practice of the invention, the incoming sync signals are converted to digital format and fed to a microprocessor, which is programmed to recognise the sync pattern. The processor tracks the digital sync signal bytesting logic levels assigned to the signal, and stops its own 105 operation prior to occurrence of a horizontal sync pulse. Processor operation is restarted upon occurr ence of the horizontal sync pulse, thereby synchro nizing processor operation to the incoming sync signal.

The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which:

Figure 1 illustrates a digital processor-based video processor; Figure 2 illustrates a standard format video signal; Figure 3 is a waveform diagram illustrating pro cessor cycle time compared to the blacker-than black transition in a standard format video signal; Figure 4 illustrates the video picture edge produced by improperly timed sampling of the video signal; Figure 5 is a circuit diagram of a sync separator circuit; Figure 6 is a flow chart illustrating the synchronization technique of the preferred embodiment; Figure 7 is a flow chart illustrating in more detail a portion of the flow of Figure 6; and Figure 8 is a flow chart illustrating in more detail a portion of the flow of Figure 6.

Detailed description of the preferred embodiment

A digital video processor is shown in Figure 1. It includes an A/D converter 11, a programmed control processor 13, a frame store 15 and a D/A converter 17. The preferred processor 13 is a microprocessor having a microinstruction execution time (referred to hereafter as'cycle'time) of 217 nanoseconds. Such a microprocessor is preferably configured from the commercially available 2900 series logic.

In the circuitry of Figure 1, operation is initiated by a'freeze'signal applied manually or automatically to the processor over a line 20. A frame of analog video signal, such as from a TV camera, is converted to digital information by the A/D 11, passed through a latch 25, and stored in the frame store 15 by the control processor 13. The A/D 11 is clocked and controlled over a control line 14, while the latch 25 is controlled over a line 16. The frame store 15 is controlled by the processor 13 over a control bus 31, which supplies control signals including a number of address bits, preferably stored by an incrementable address register in the control processor 31.

After a frame is stored in the frame store 15, the processor 13 may cause the frame to be outputted over an 8-bit parallel data bus 29, through a tri-state driver 21 to the D/A converter 17 in order to output an analog TV picture. Control information used in outputting a frame is transmitted over a blank/sync bus 27 to the D/A converter.

The TV picture in the frame store 15 actually contains 256 lines each having 256 points. Each point is represented by a digital number. The TV picture tube successively scans these points and controls their color as instructed by the digital number to form the composite picture. To control the scanning, vertical and horizontal sync pulses are used. The vertical sync brings the scanner (the 'spot') to the upper left corner of the TV picture. The scannerthen employs the output of the frame store 15 to scan the first line. At the end of the first line the scanner receives a horizontal sync signal which causes the scanner to drop to the next line.

A standard format video signal is shown in Figure 2. This signal transits through levels known as 'white' 32, 'black' 34 and 'blacker-than-black'36. The video signal successively includes (1) an equalizing pulse train 31, (2) a vertical sync pulse train 33, (3) a second equalizing pulse train 35, (4) a horizontal sync pulse train 37, (5) alternating analog video and horizontal sync pulses 39. The time interval between the last horizontal sync pulse and the beginning of the equalizing pulse train of the vertical sync pattern is 'H' (63.5 tts) for Field 1 and.5H (31.7 I.Ls) for Field 2.

In a digital video processor implementation, it proves desirable to provide the processor with the capability to recognize the format of standard video signals. It further proves desirable to synchronize the processor operation with the horizontal sync signals in order to properly time sampling of the video data which follows a horizontal sync pulse. Particularly, it is desirable to synchronize timing with the transition 42 to the 'blacker-than-black' level 36 of the horizontal sync pulse. One approach considered is that of using the processor to sample and test the level of 2 GB 2 143 399 A 2 the horizontal sync pulse. However, because the processor cycle typically does not coincide with the blacker-than-black transition, reliable synchroniza tion may not be achieved by this method.

This problem is illustrated in Figures 3 and 4. 70 Figure 3 shows the blacker-than-black transition or edge 42. The dots 41 indicate processor cycle points where the processor might test sampled values of a horizontal sync pulse 40. As shown, these sample points 41 leave considerable uncertainty in detection of the transition time. The result is that the edge of the stored video picture is not smooth, but is serrated in appearance, as shown in Figure 4.

In order to avoid this result and provide a wholly digital signal tracking apparatus, a sync separator circuit 19 and certain microprocessor techniques are employed. The sync separator circuit 19 is shown in detail in Figure 5. It functions to clip the inputvideo signal to the AID converter 11 below the blacker than-black level (e.g., line 12 in Figure 2), providing a rectangular pulse train.

In the sync separator circuit 19, the sync level 36 (Figure 2) of the input video signal is clamped to negative.6 volts by input circuitry including a capacitor 50, a diode 48 and a resistor 46. The level 34 is at negative.3 volts at this point. The clamped signal is inputted to an amplifier 43 (LM 318), which outputs to a comparator 45 (LM 361). The amplifier 43 is configured with an input resistor R,,, a resistor R, connected from output to inverting input, and capacitors Cl and C2 connected to respective supply voltages. A resistor R22 is connected between the output of amplifier43 and the noninverting input of amplifier45. This noninverting input is also con nected to a parallel combination of a diode D, and a capacitor C3, which are grounded at their respective opposite terminals. The inverting input of capacitor is connected to two resistors R2, R3 which are connected to respective supply levels of zero and five volts.

The resultant pulse supplied to the comparator 45 is an inverted and amplified version of the input to the amplifier 43 with levels 34 and 36 at + 1.5 and +3 volts respectively. The output SyncP of the compara tor 45 is the desired clipped pulse train with the zero volt pulse peak designated logic zero and the +5 volts designated logic one (e.g., Figure 3). The logic zero output corresponds to the 'biacker-than-black' level 36.

The clipped pulse train SyncP is supplied to a clock 11 generator 47 (AM 2925). Another input to the clock generator 47 comes from a stop control bit supplied by the processor 13 on a line 49.

In order forthe processor 13 to properly store a frame, it is necessary for it to track the sync signals, beginning with the leading vertical sync pattern 33. in the preferred embodiment, the processor 13 relies on knowledge of what this waveform should be at specific times. The processor 13 test Syncl? at various instants to determine whether it is 1" or"O". The logic value of SyncP over various intervals indicates what portion of the video signal is being received. This technique provides a great simplification, for example, over sampling the waveform and comparing an eight-bit sample to a stored value.

A flow diagram illustrating sync tracking in the preferred embodiment of the invention is shown in Figure 6. This flow will be discussed in conjunction with Figure 2, which illustrates a standard video format. The flow of Figure 6 illustrates storage of an interlaced picture (two fields). The routine shown can be readily adapted to the simpler case of storing only one field.

When a freeze signal is received by the processor, it enters the subroutine of Figure 6. The processor first performs a routine denoted 'Field V. This routine tests the logical value of the sync signal train (Figure 2) until it recognizes the beginning of the vertical sync pattern 31 for Field 1.

At the end of'Field V, a counter denoted COUNT3 is set equal to one, indicating the first field is to be stored. Then a routine denoted 'VERTSYNC' is performed. This routine tests the logical value of the sync pulse train until the last vertical sync pulse 30 is found and then waits 3H (190.5 s), the length of the equalizing pulse interval 35. Atthe end of VERT SYNC, a processor register COUNT 1 is set equal to 256 to serve as a line counter in connection with storage of the imminent video data. Setting of this register is indicated by block 52 of Figure 6.

At this point, the technique according to the invention for synchronizing sampling is undertaken. After Count 1 is set to 256, the processor 13 is stopped This is accomplished by provision of a micro instruction which applies a logic M" to the wait request input of the clock 47, shown as part of the sync separator circuit 19. The occurrence of the next sync pulse on line 44 restarts the clock 47 precisely at the transition of the sync pulse, thus synchronizing timing. From this transition point 42 (Figure 3), it is known that the video information will follow in 6.7 microseconds (31 cycles).

Thus, the processor 13 waits for 6.7 microseconds and then begins storing a line in the Field 1 memory.

After storage of the line, the line address register of the processor memory control is incremented by 1 to prepare for addressing the next line. COUNT 1 is also decremented by one. Then COUNT 1 is tested, and if it is not zero a loopback to point 53 results. The processor clock 47 is again stopped, restarted at the next sync transition 42 and a line stored. This pro6ess is repeated until all 256 lines of Field 1 are stored. Then COUNT3 is decremented to zero which results in a loop back to point 51 (Figure 6) to store the second field, Field 2. It may be noted that black lines are stored through interval 37 until video information appears after point 38 in Figure 2.

A detailed flow of routine Field 1 is shown in Figure 7. As shown, SyncP is first tested until a 1" is detected. This test occurs every 2 cycles. Syncl equal to one indicates a space between sync pulses has been found. The separation between sync pulses may be either of duration H (63.5 Ls) or.5H (31.7 [is).

Thus, after SyncP = 1 is detected, a counter COUNT 1 is set equal to 100. This counter is then decremented and SyncP again tested attest 55. Test 55 occurs every 2 cycles (every 434 nanoseconds in the preferred processor). If Syncl? is equal to 1 (a logic 1" value at comparator 45 output), COUNT 1 is again decremented. As long as SyncP is M" when 3 GB 2 143 399 A 3 tested at test 55, the loop entered at point 56 will be performed until COUNT 1 equals zero. However, if SyncP should be zero when test 55 is performed, Field 1 is entered at the start.

Thus, when COUNT 1 equals zero attest 57, the time interval between sync pulses was H (63.5 I.Ls). This is known because the processor has walked 200 cycles, about 70% of H, without detecting a sync pulse.

SyncP is then tested at a test 59 to locate the next sync pulse. When that sync pulse is detected, COUNT 1 is setto 32 and a loop 61, 63,65 is entered. If, in the loop 61, 63, 65 SyneP is tested 32 times without detecting a 1", Field 1 is exited. At this point, the beginning of the vertical sync pulse interval 33 has been found. This is Field 1 for EIA Standard RS-330.

If, in loop 61, 63, 65, Syncl? is found to be one, a test 67 of COUNT 1 is made. If COUNT 1 is less than 27, Field 1 is performed again. A horizontal sync pulse was found. If COUNT 1 is greater than 27, Field 1 is exited. An equalizing pulse was found. This is Field 1 for EIA Standard RS-1 70.

A detailed flow for VERT SYNC is shown in Figure 8. VT SYNC loops in a test 71 until SyneP equals zero (i.e., a sync pulse is detected; the processor doesn't know which one). COUNT 1 is then set to 107 and a loop 73,75,77 testing SyncP, is performed. If SyncP is zero for 107 counts, the program remains in the loop 73, 75, 77 and then exits to a test 79, which loops until SyncP equals one. When test 75 or test 79 is satisfied, the routine proceeds to set a counter denoted COUNT 2 to 32. At this point, COUNT 1 contains 107 minus the total number of blacker-than- black elements that the program has detected.

Next, COUNT 2 is decremented and Syncl? tested in a loop 80, 81, 83 to determine the length of the interval between sync pulses. If SyncP is detected unequal to'one'at anytime or COUNT 2 equals zero during loop 80, 81, 83; the routine proffleeds to test 85. If test 85 shows COUNT 2 is not zero, the routine is walking the vertical sync pulse interval. The routine re-enters at point 87 and continues subtracting from COUNT 1 the number of blacker-than-black elements that the program detects. If test 85 shows COUNT 2 equals zero, it means that the routine is walking a video line. In such case, COUNT 1 is tested at test 89. If COUNT 1 is not zero at least 89, VT SYNC is re- entered. If COUNT 1 equals zero at test 89, the routine has passed the last vertical sync pulse and then waits 3H and returns to the main subroutine of Figure 6.

The foregoing description provides a method by which a digital processor may track and synchronize itself to an incoming sync signal. The embodiment has been described in terms of NTSC television standards. Modification in accordance with other standards such as PAL (which has a quarter line offset rather than a half line offset in the relationship between line and picture frequencies) will be selfevident.

Claims (13)

CLAIMS:-

1. A method of synchronizing sampling in a video processor including a programmable, clock- driven digital processor, comprising the steps of stopping the clock to the digital processor prior to occurrence of a horizontal sync pulse, and starting the clock upon occurrence of the horizontal sync pulse. 75

2. The method of claim 1, wherein the clock is started upon detection of the first transition to blacker-than-black of the horizontal sync pulse.

3. A method according to claim 1 or2, comprising the step of generating a pulse train comprising pulses of the video sync signal which fall below a selected threshold and wherein the clock is started upon occurrence of a transition in the pulse train corresponding to horizontal sync pulse.

4. A method according to claim 3, wherein before stopping the clock, the digital video processor tracks the pulse train by testing for the presence over selected intervals of logical values assigned to the pulse train.

5. A method according to claim 4, wherein the transition in the horizontal sync pulse is detected only aftertracking of the pulse train has detected the presence of a vertical sync pulse pattern.

6. A method of synchronizing operation of a clocked, programmed digital video processor, corn- prising the steps of generating a pulse train comprising pulses of the video sync signal which fall below a selected threshold; assigning logic levels to the pulses in the pulse train; detecting a vertical sync pattern in the pulse train by testing the logical levels; detecting occurrence of the last pulse in the vertical sync pattern; stopping the clock to the processor after the detection of the said last pulse, thereby halting processor operation, and restarting the clock to the processor in substantial coincidence with detection of a transition of the first horizontal sync pulse.

7. A method according to claim 6, wherein before stopping said clock, a processor register is set to serve as a line counter for subsequent storage of video data.

8. A method according to claim 6 or7, wherein before Oetecting the vertical sync pattern, the step of detecting a horizontal sync pulse or equalizing pulse is performed.

9. A method according to claim 6, further includ ing the steps of repeatedly storing a line of video data following a detected horizontal sync pulse, stopping the clock, and restarting the clock upon a transition of the next horizontal sync pulse.

10. A method according to claim 9, wherein before first stopping the clock,, a processor register is set to serve as a line counter and wherein, after performing the step of storing aline of video data, the count in the processor register is decremented.

11. Apparatus for use in receiving and storing a video signal, comprising a control processor, clock means for clocking the processor and a second input triggerable to restart the clocking; a sync separator circuit for producing a pulse train from sync levels of the video signal and supplying the pulse train to the 4 GB 2 143 399 A 4 said second input and to the processor.

12. Apparatus according to claim 11, wherein the control processor has a control lead connected to the said first input and functions to stop the clock means 5 at selected times during receipt of the pulse train.

13. Apparatus according to claim 11 or 12, further including means for converting the video signal to a digital signal; and a frame store controlled by the control processor to store digital video information 10 contained in the digital signal.

Printed in the U K for HMSO, D8818935,12,84,7102. Published by The Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.

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