GB2039372A - Test apparatus for electrical control systems of internal combustion engines - Google Patents

Abstract

A test apparatus monitors a plurality of electric signals representing selected parameters of the electric control system and provides an indication as to which of the monitored signals malfunctioned and as to which signal was the first to malfunction. The electric signals are sampled and processed with a plurality of reference values by a sampling circuit (20) and a signal processing circuit (52-148), respectively. Two of the sampled signals 26, 28, two time duration signals and two comparison signals are tested with corresponding reference values and output signals are provided indicating the results of the testing. The sampled electric signals which malfunctioned or which indicate a fault are identified by a set of light emitting diodes (190-202). The first sampled electric signal to malfunction is indicated by a second set of light emitting diodes (230-236). <IMAGE>

Description

SPECIFICATION Test apparatus for electrical control systems of internal combustion engines This invention relates to test apparatus adapted for connection to the electric control system of an internal combuston engine and in particular, to test apparatus which monitors a plurality of electrical signals representing selected parameters of the electric control system.

Occasionally, motor vehicles controlled by an electronic fuel injection system will exhibit mysterious stalls and other malfunctions or failures on an intermittent basis. The vehicles may also experience a sudden surge or sag. The electrical signals of the electric control system of the vehicle if properly analyzed could indicate the cause of the malfunction or failure. It is therefore desirable to monitor certain preselected electric signals of the electric control system of the vehicle so as to pinpoint which of the signals indicates a malfunction while the vehicle is in operation.

Previous attempts have been made to analyze intermittent malfunctions by obsrving the sampled electric signal on an oscilloscope. If the oscilloscope operator was not watching the correct signal at the exact time that the malfunction occurred he would miss the fleeting evidence. Furthermore, at best, two signals can be observed with an oscilloscope with any degree of assurance that any malfunction would be observed. As a result, troubleshooting of an electric control system often took a shotgun approach where various components likely to cause the failure would be replaced with no assurance that the problem would be solved.

The U. S. Patent of Keely 3,834,361 discloses a failure detection device which monitors the current being drawn by a fuel control computer. Afailure detection circuit supplies information to the fuel control computer when a sensor supplying information has malfunctioned. The output pulses generate by the primary computer are analyzed to detect a computer failure. A failure detection circuit detects a failure of the primary computer to generate output pulses.

The U. S. Patent of Geul 3,732,491 discloses a device for measuring the time duration of the opening of an electronically controlled fuel injection valve by analyzing the electrical pulses which cause the injection valve to open.

The U. S. Patent of Pohl 3,961,240 discloses an electronic ignition test system which analyzes a signal representative of the ignition pulse by comparison with other pulses.

The U. S. Patent of Lane et al 3,920,284 discloses a control system which monitors wheel speed sensing circuits for sensor continuity and provides a control signal when an open circuit condition is detected.

Other electric control systems generally of the type to which this invention relates are disclosed by the U. S. Patents of Konrad et al 4,002,972, Lach 3,961,239, Hanson et al 3,972,230 and Williamson 3,383,592.

An object of the present invention is to provide a test apparatus adapted for connection to the electric control system of an internal combustion engine which monitors a plurality of electrical signals simultaneously and determines by various measurement techniques whether the signals are within operating tolerances and, if an intermittent problem occurs, will identify which signal indicates a fault or malfunction.

Another object of this invention is to provide a test apparatus adapted for connection to the electric control system of an internal combustion engine wherein faults are continually displayed to identify which signal caused the malfunction until the test apparatus is reset.

Afurtherobjectoftheinvention is to provide test apparatus adapted for connection to the electric control system of an internal combustion engine wherein the apparatus monitors speed sensor sig naps from a pair of trigger switches, injector group signals of an electronic control unit of the system, the input voltage signal to the electronic control unit, and the ignition-on voltage signal of the electronic control unit and wherein if any of the signals is interrupted or fails the area offailure is indicated and if two or more of these signals are interrupted or fail the apparatus indicates which was the first to fail.

Yet another object of the present invention is to provide a test apparatus adapted for connection to the electric control system of an internal combustion engine wherin a display continuously identifies which signals of the system malfunctioned and which signal was the first to malfunction until the apparatus is reset.

In carrying out the above objects and other objects of this invention a preferred embodiment of a test apparatus constructed according to the instant invention includes a sampling means including a like plurality of input means, each of the input means corresponding to a particular electric signal to be monitored, the sampling means sampling a plurality of electric signals. The test apparatus also includes a signal processing means connected to each of the input means for processing the sampled signals with a plurality of reference values, the signal processing means providing a like plurality of output signals indicating the results of the processing wherein each of the output signals contains information as to whether its corresponding sampled signal malfuctioned.The apparatus includes indicator means including a like plurality of circuit means, each of the circuit means being connected to the signal processing means for indicating unfavorable results of the processing from the output signals. Each of the circuit means includes a display means for identifying which of the electrical signal malfunctioned, display means identifying which signal malfunctioned for a desired period of time. The apparatus also includes second indicator means connected to the signal processing means for indicating for a desired period of time which one of selected ones of the electrical signals was the first to malfunction whereby the second indicator means provides a malfunction priority indication.

Further in carrying out the above objects and other objects of this invention a preferred method of carrying out this invention includes the steps of sampling a plurality of electric signals and processing the sampled signals with a plurality of reference values to provide a like plurality of output signals indicating the results of the processing. The method also includes the step of displaying unfavorable results of the processing from the output signals to identify which of the signals malfunctioned and which of the electric signals was the first to malfunction.

The objects, features, and advantages of the present invention are readily apparent from the following detailed description of the best mode taken in connection with the accompanying drawings.

In the drawings: Figure lisa block diagram of the test apparatus of the invention showing the monitored electrical input signals; Figure 2a is a circuit diagram of the power supply of the apparatus; Figure 2b is a circuit diagram of the ECU power test circuit of the apparatus; Figure 2c is a circuit diagram of the ignition voltage test circuit of the apparatus; Figure 3 is a circuit diagram of a measuring circuit of the apparatus; Figure 4 is a circuit diagram of a D to A converter circuit of the apparatus; Figure 5 is a circuit diagram of a compare circuit and a test circuit of the apparatus; Figure 6 is a circuit diagram of a indicator circuit of the apparatus; Figure 7 is a circuit diagram of a measuring circuit of the apparatus; Figure 8 is a circuit diagram of a measuring circuit of the apparatus;; Figure 9 is a circuit diagram of an indicator circuit of the apparatus; Figure 10 is a timing diagram of the circuit of Figure 7; Figure ii is also a timing diagram of the circuit of Figure 7; Figure 12 is a timing diagram of the circuit of Figure 7 at 4000 RPM; and Figure 13 is a timing diagram of the circuit of Figure 8.

Referring now to the drawings there is shown an illustrative embodiment of the invention in a test apparatus especially adapted for connection to the electric control system and, in particular, to a motor vehicle's electronic control unit (not shown).

The block diagram of Figure 1 shows a sampling means or a harness represented at 20 and including plurality of inputs 22,24, 26, 28,30,32, 34 and 36.

The harness 20 is adapted to electrically connect an adaptor of the electronic control unit to the remainder of the test apparatus to thereby allow the test apparatus to monitor selected signals of the electronic control unit.

The speed sensor signals, trigger &num;1 and trigger &num;2, appear on inputs 22 and 24, respectively. The ignition-on voltage or the ignition volts signal of the ECU appears on the input 26. The ECU power signal or the input voltage to the ECU appears on the input 28. The two injector group signals from the ECU, injector wave form #1 and injector wave form &num;2 appears on the inputs 30 and 32, respectively. The compliments of the first and second injector pulse signals Tpp &num;1 and Tp &num;2 appear on the inputs 34 and 36 respectively.

The test apparatus is powered by the automobile battery voltage Vbatt appearing on an input 38 to a 5.8 volt regulator power supply circuit generally indicated at 40 in Figure 1. The automobile battery voltage is taken from the cigarette lighter jack of the motor vehicle and is reduced and maintained by the circuit 40 and 5.8 volts to insure that the test apparatus operates satisfactorily as battery voltage varies.

Referring now to Figure 2a, the circuit 40 comprises a voltage regulator having an input resistor, R1, connected to the input 38 and a resistor, R2, connected to the input 38 in parallel with the resistor, R1.

The opposite end of the resistor, R1, is connected to a resistor, R3, which is connected to the collector of a pnp transistor, T1, the emitter of which is grounded.

The end of the resistor, R2, opposite the input 38 is connected to the base of transistor T1 one plate of a capacitor, C1, and the cathode of a 5.8 volt zener diode, D,,the other plate of the capacitor, C1, and the anode of the diode, D1, being grounded. The opposite end of the resistor, R1, is connected to the collector of an npn transistor, T2, which is connected at its emitter to ground through a resistor, R4 and has its base connected to the emitter oftransistorT1.

The emitter of the transistor, T2, supplies a 5.8 volt supply voltage, +V1, to the remainder of the test apparatus through an on-off switch SW1 which is a double-pole switch. In the event of a momentary loss of battery voltage appearing on the input 38 the test apparatus will continue operating from an internal 6 volt battery, B1, which is connected through a diode, D2, to the switch SW1 and parallel with the 5.8 volts from the emitter of the transistor, T2. A light emitting diode (LED) 42 is connected to the voltage, +V1, through a resistor, Rs, and is energized or lit when the switch SW1 is in its "on" position to indicate that the test apparatus is in its monitoring or "on" state.

Typical values for the above-described resistors are as follows: R1 = 10 ohms, R2 = l0kohms,R3=2 kohms, R4 = 10 kohms, and R5 = 108 ohms. The value of the capacitor C1 is typically 6.8 microfarads.

Transistor, T1, is identified by the number 2n3702 and transistor, T2, is identified by the number mje521.

Referring now to Figure 2b a compare and error detect circuit generally indicated at 44 is shown. The voltage used by the ECU to supply power to its internal circuitry is sampled by the input 28 of the circuit 44. The circuit 44 includes an operational amplifier 46 which is connected in the circuit 44 as a comparator. The input 28 is connected to the non-inverting input of the amplifier 46 through a trimmer resistor, R6. Also connected to the noninverting input of the amplifier 46 is a resistor, R7, which is grounded at its opposite end. The reference voltage, +Va, is connected to the inverting input of the amplifier 46 through a resistor, R8. A resistor, Rg, completes the voltage divider comprising the resistors R8 and Rg, the resistor Rg being also connected to the inverting input of the amplifier 46.

Typical values for the above-described resistors are: R6 = 38.8 kohms, R7 = 30 kohms, R8 = 50 kohms and Rg = 100 kohms.

As shown in Figure 2b, the comparator 46 tests whether the ECU power voltage appearing on the input 28 goes below 11 volts by going from a logical "high" state to a logical "low" state thereby otputting an ECU power low signal.

Referring now to Figure 2c there is shown a compare and error detect circuit generally indicated at 48. Voltage supplied to the vehicle's ignition system is monitored by the circuit 48. The ignition volt signal is connected to the non-inverting input of an operational amplifier 50 (which is also connected in the circuit 48 as a comparator) through a resistor, R10. A resistor, R11, completes the voltage divider comprising, R10 and R11 and is also connected to the non-inverting input of the operational amplifier 50.

The reference voltage, +V1, is connected to the inverting input of the amplifier 50 through a resisotr, R12. A zener diode, D3, is also connected to the inverting input of the amplifier 50 and holds the voltage at the inverting input of amplifier 50 to 3.9 volts.

Typical values of the resistors are: Rlo = 1.7 kohms, R11 = 3.9 kohms, and R12 = 1.5 kohms.

The amplifier 50 outputs an ignition power low signal when the ignition signal at the input 26 drops below 6 volts, the output of the amplifier 50 going from a logical "high" to a logical "low" state.

Referring again to Figure 1 and Figure 3, the trigger &num;1 and &num;2 signals are input to the set and reset inputs of a D flip-flop 52 through resistors, R13 and R14, respectively. A resistor, R15, is also connected to the set input of the flip-flop 52 and together with the registor, R13, define a voltage divider. A resistor, R16, is also connected to the reset input of the flip-flop 52 and together with the resistor, R14, define another voltage divider. The outputs of the flip-flop 52, at Q and Q are symmetrical and inverted.

The output voltages at, Q and Q, are input into two NAND gates 54 and 56, respectively. A 1 KHz clock 58, also shown in Figure 1, is connected as a second input to the NAND gates 54 and 56. The NAND gates 54 and 56 allow the 1 KHz clock signal to pass through as output signals, clock &num;1 and clock #2, as shown in Figure 3, when the outputs at 0 and 0 are logically high, respectively.

In general, the clock 58 provdes clock input signals to identical Counter, Latch and D to A Convertor circuits generally indicated at 60 and 62 only one of which need be discussed. As described hereinafter, like components in the circuit 60 will be given prime numbers corresponding to the numbers given the components in the circuit 62.

The signal, clock &num;2, appears on the input of a 12 stage ripple-carry binary counter 61. The output of the counter 61 increases in binary fashion as long as the pulses of signal, clock &num;2, are present at the input 63 of the counter 61.

The Q output of the flip-flop 52 is also connected to a monostable multivibrator or one shot 64 by an input 66. On the trailing edge of a pulse fromhthe one shot 64 outputs a latch pulse along a line 68 out to a pair of clocked strobe latches 70 and 72. The latch pulse strobes the information at the outputs 1 through 7 of the counter 61 into the latches 70 and 72 thereby storing the information therein. Only the 7 least significant bits of the counter 61 are present at the output of the latches 70 and 72.

At the end of the latch pulse a second one shot 76 outputs a reset pulse along a line 74 to the counter 61. The second one shot 76 is connected to the first one shot 64 in a conventional fashion along a line 78.

The reset pulse resets the counter 61 so that all of counter outputs are logically low. Because the clock has a frequency of 1 KHz the binary number contained within the counter 61 also equals the number of milliseconds between the leading and trailing ends of the pulses atO. If the pulses atO exceeds 128 milliseconds an error signal will appear on a line 80 which is connected to that output of the counter 61 which represents the number 128. The error signal is used to insure that a total loss of a trigger pulse will be detected as will be described in greater detail hereinafter.

Since the signals clock &num;1 and clock &num;2, go to identical circuits as previously mentioned, the output of the latches 70 and 72 will be identical to the output of the latches 70' and 72' if the trigger &num;1 signal and the trigger &num;2 signal have the same time relationship.

The values of resistors, R13 and R14, = 100 kohms; the values of the resistors, R15 and R16, = 500 kohms.

The resistors, R17 and R18, both have a value = 100 kohms. The capacitors, Cl2 and C3, both have a value of .01 microfarads and are connected with their respective connected resistors R17, R15tO one shots 64 and 76, respectively, in a conventional fashion.

The line 80 is connected to the 8th output bit of the counter 61 through an inverter 79 (which logically inverts the state of the 8th output bit of the counter 61) and through a diode 81 (whose cathode is connected the output of the inverter 79).

The outputs of the latches 70 and 72 are inputs to a digital to analog or D to A converter or circuit generally indicated at 82 in Figure 4. The D to A converter 82 comprises an R-2R network feeding the inverting input of an operational amplifier 84. The outputs of the latches 70 and 72 are inputs to the converter 82 as indicated by the bit numbers 1 through 64. The output voltage, E0, of the converter 82 decreases proprotionately as the voltage appearing at the inverting input of the amplifier 84, Ej, increases thereby representing an increasing binary number appearing at the latch outputs. The coverter 82 includes a resistor, R19, connected between the inverting input and the output of the amplifier 84. A capacitor, C4, is connected between the inverting input of the amplifier 84 and ground. A voltage divider network comprising resistors, R20 and R21 divide down the reference voltage, +V1, the output of the network biasing the non-inverting input of the amplifier 84.

The value of each resistor, R, in the circuit 82 = 10 kohms therefore the value of each resistor, 2R, = 20 kohms. The value of resistor, R19, = 8 kohms. The value of resistors, R20 and R21, is 7.8 kohms and 10 kohms, respectively. The value of the capacitor, C4, is.47 Microfarads.

Referring again to Figure 3, when there are trigger pulses present at the inputs 22 and 24 and the engine RPM is substantially constant the output voltages represented by Eo &num;2 and Eo &num;1 of the D to A converters 82 and 82', respectively, should be equal.

As the engine RPM changes gradually, as during an acceleration or deceleration the voltage signals Eo &num;2 and Eo &num;1 will each step up or down slowly with the RPM change. If one of the trigger pulses is missing at either one of the inputs 22 or 24 the output voltage, Eo &num;2 or Eo &num;1, of its corresponding D to A converter 82 or 82' will change drastically.

Referring now to Figure 5, the output voltages of the circuits 62 and 60, Eo &num;2 and Eo #1, respectively, appear as inputs to a compare and error detect circuit generally indicated at 86. The circuit 86 includes a pair of operational amplifiers 88 and 90 connected as difference amplifiers in the circuit 86.

The amplifiers 88 and 90 are typically set to a gain of 5. The voltage signal, Eo &num;1, appears at the inverting input of the amplifier 88 through a resistor R22. A resistor, R23, is connected from the inverting input to the output of the amplifier 88, the value of the resistor R23 determining the gain of the amplifier 88.

The voltage signal, Eo &num;2, appears at the noninverting input of the amplifier 88 through a resistor, R24, which together with a resistor, R2 5, form a voltage divider network for dividing down the voltage, Eo &num;2, at the non-inverting input of the amplifier 88.

In a similar fashion, the voltage signal, Eo &num;2, appears at the inverting input of the amplifier 90 through a resistor, R26. A resistor, R27, is connected to the inverting input of the amplifier 90 and to the output of the amplifier 90. The voltage signal, Eo &num;1, appears at the non-inverting input of the amplifier 90 through a resistor, R28, which together with a resistor, R29, form a voltage divider for dividing down the voltage, Eo #1, at the non-inverting input of the amplifier 90.

The output of the amplifier 88 is connected to the inverting input of an operational amplifier 92 connected in the circuit 86 as a comparator through a resistor, R30. Voltage reference, +V1, is connected to the non-inverting input of the amplifier 92 through a resistor, R31,which together with a resistor, R32, also connected at the non-inverting input of the amplifier 92, forms a voltage divider.

The output of the amplifier 90 is connected to the inverting input of an operational amplifier 94 through a resistor, R33. The non-inverting input of the amplifier 94 is connected to the non-inverting input of amplifier 92 and are consequently biased by the same voltage.

The outputs of the amplifiers 88 and 90 remain in a logical low state if there is no difference between the Eo &num;1 and the Eo &num;2 signals. If there is a difference between the Eo &num;1 signal and the Eo &num;2 signal this difference will cause either one of the amplifiers 92 or 94 to go to a logical low state when this difference signal at their inverting inputs represents a time period greater than 18 milli-seconds. For example, if the Eo #1 signal is less then Eo &num;2 signal so as to represent a time difference between any two trigger pulses greater than 18 milliseconds the amplifier 92 will go to the logical low state.Conversely, if the Eo &num;2 signal is some less than Eo &num;1 signal so as to represent a time difference between any two trigger pulses greater than 18 milliseconds the amplifier 94 will go to a logical low state.

The chosen time of 18 milliseconds allows the circuit 86 to operate satisfactorily at high RPM's. A missing trigger pulse at a high RPM of, for example, 4,000 RPM will result in an error time of 45 milliseconds which is much longer than the normal tested for 15 millisecond time period. At lower RPM error time is larger.

As previously mentioned, the two difference amplifiers 88 and 90 and the two comparator amplifiers 92 and 94 are required because either of the two trigger pulses may be missing. Normal accelerations and decerlations do not result in time differences greater than 10 milliseconds thereby making the circuit 86 immune to normal automobile operations.

The outputs of the amplifiers 92 and 94 are connected to the inputs of a NAND gate 96 through diodes 98 and 100, respectively. The inputs of the NAND gates 96 are normally held high by the reference voltage, +V1, through resistors, R34 and R35. When the output of one of the biased amplifiers 92 or 94 goes to its logical low state the output of the NAND gate 96 goes to a logical high state which appears at the inputs of a NAND gate 102. The NAND gate 102 is connected as an inverter and therefore its output will go to a logical low state when the output of the NAND gate 96 goes to its logical high state.

When the output of the amplifier 92 goes to its logical low state a missing &num;1 pulse signal appears along a lead 104 of the circuit 86 and, consequently, a pulse missing signal appears at the output of the NANDgate 102 along a lead 106. When the output of the amplifier 94 goes to its logical low state a missing &num;2 pulse signal appears along a lead 108 of the circuit 86 and, consequently, a pulse missing signal appears at the output of the NAND gate 102 along the lead 106 which indicates that one of the trigger pulses signals is missing.

The output of the amplifier 92 is logically OR'ed with the previously mentioned 128 millisecond signal for the &num;1 trigger by wiring the lead 104 and the lead 80' together at a point 110. In the same fashion the output of the amplifier 94 is logically OR'ed with the 128 millisecond signal for the &num;2 trigger by wiring the lead 108 and the lead 80 together at a point 112. These connections at the points 110, 112 insure that an error will be detected if the trigger pulses are totally stopped.

In the circuit 86, the resistors R22, R24, R26, R28, R30 and R33typically = 10 kohms; resistors R23, R25, R27, R29, R34, and R35 typically = 50 kohms; and resistors, R31 and R32 = 2.7 kohms and 3 kohms, respectively.

Referring now to Figure 7, the #1 injector wave form and the &num;2 injector wave form as shown in Figure 10 appear on the set and reset inputs of a D flip-flop 114 through resistors, R36 and R37, and rectifying diodes 116 and 118, respectively. Also connected to the set and reset inputs of the flip-fiop 114 are resistors, R38 and R39, respectively, which together with their respective resistors, R36 and R37, define voltage dividers at the set and reset inputs of the flip-flop 114.The signals at the 0 and8outputs of the flip-flop 114 are symmetrical and inverted and appear at the inputs to two NAND gates 120 and 122, respectively, which allow the 1 KHz clock pulses to pass there through during the time when the outputs, 0 and are logically high as shown in Figure 10.

The NAND gates 120 and 122 are components of Counter, Latch and D to A Convertor circuits generally indicated at 124 and 126, respectively. The circuit 124 and 126 have the same components and operate in the same fashion as the circuits 60 and 62, respectively.

Furthermore, a Compare and Error Detect circuit generally indicated at 128, which is connected to the output leads 142 and 140 of the circuits 124 and 126 also has the same components and operates in the same fashion as the circuit 86. The only difference in processing the injector &num;1 and &num;2 wave forms and in processing the trigger &num;1 and &num;2 pulse signals is the fact that the diodes 116 and 118 are connected at the set and reset inputs of the flip-flop 14, respectively, in order to rectify the injector &num;1 and &num;2 wave forms (shown in Figure 10 and Figure 12).

The resistor, R36, has the same value as the resistor, R13; the resistor, R37, has the same value as the resistor, R14; the resistor, R38, has the same value as resistor, R15; and the resistor, R39, has the same value as resistor, R16.

The circuits 124 and 126 will not be described since the components are the same and are connected in the same fashion as the components of circuit 62 and 60, respectively. However, the wave forms and signals resulting from the operation of the components of the circuit 124 and 126 will be described in detail hereinafter with reference to Figures 10,11 and 12.

Referring first to Figure 10, the first and second injector wave forms are shown as they appear at the inputs 30 and 32. The output signals from the Q and 0 outputs of the flip-flop 114 which result from the first and second injector wave forms are also shown.

The outputs, 0 and, are symmetrical and inverted.

Appearing on the outputs of the NAND gates 120 and 122 are the clock &num;1 signal and the clock &num;2 signal, respectively, the 1 KHz clock signal being allowed to pass during the time its corresponding signals from 0 andnare high.

Referring now to Figure 11, the trailing edge of the 0 output signal of the flip-flop 114 causes a one shot 130, corresponding to the one shot 64', to send a latch pulse to two clocked latches 132 and 134 corresponding to the latches 70' and 72', respectively, to latch the contents of a counter 138 into the latches 132 and 134. At the end of the latch pulse a reset pulse is generated by a one shot 136 which corresponds to the one shot 76' which reset pulse resets and counter 138. The counter 138 counts the clock pulses of the clock &num;1 signal shown in Figure 10.As previously described in the description of the circuits 60 and 62, the output clock &num;1 and clock &num;2 signals of the circuit 124 and 126 go to identical Counter and Latch circuits which will result in identical outputs from the corresponding latches if the injection pulse wave forms &num;1 and &num;2 have the same time relationship.

Referring now to Figure 12, if the injector &num;2 signal wave form has a pulse missing at, for example, 4,000 RPM the biased comparator 94 of the circuit 128 will indicate an error or missing pulses since the time difference between any two injector pulses is greater than 18 milliseconds. In this case a missing pulse at 4,000 RPM will result in an error time of 45 milliseconds which is much longer than the normal 15 millisecond time period. As previously mentioned in the description of the identical circuit 86, at lower RPM's the error time is larger.

Again, the two difference amplifiers 88 and 90 and the two comparator amplifiers 92 and 94 of the circuit 128 are required because either of the injector pulses may be missing. Normal accelerations and decelerations do not result in time differences greater than 10 milliseconds making the circuit 128 immune to normal vehicle operation. When an error situation is detected the output of one of te comparator amplifiers 92 and 94 of the circuit 128 goes to a logical low state causing the output of the NAND gate 96 to go to a logical high state. The output of the NAND gate 102 will go to a low logical state to indicate an error in operation i.e. a missing injector pulse.

The inputs to the NAND gate 96 of the circuit 128 are also connected to leads 140 and 142 of the circuits 126 and 124, respectively, to logically OR the signals thereon together. The signals on the leads 140 and 142 are the 128 millisecond &num;2 injector and &num;1 injector signals, respectively. Again, this is to insure that an error is detected if the injector pulses stop totally.

Referring now to Figures 1 and 8, the comple- ments of an injector pulse &num;1 signal, Tp &num;1, and injector pulse &num;2 signal, Tp &num;2, are logically OR'ed by an OR gate 144, the result of the logical OR'ing appearing on an input 146 is applied to a Long Pulse Injection circuit generally indicated at 148. Each of the signals, Tp &num;1 and Tp &num;2, have a width corresponding to the width, W, of a typical injector wave form as shown in Figure 10. As shown logically OR'ed in Figure 13, the Tp &num;1 singal and the Tp &num;2 signal are both rectangular pulses having the same width, W, as the width of the injector wave form.

The circuit 148 processes the Tp &num;1 signal as logically OR'ed with the Tp &num;2 signal in order to detect an abnormally long injector pulse. The circuit 148 measures the duration of the signals,Tp &num;1 AND Tp #2 todetermine if during normal driving conditins the duratons are over 13 milliseconds. Such a condition would give a surge to the vehicle's driveability. During start and warm-up the pulses typically exceed the 13 milliseconds and the measurement should be ignored during these conditions.

The circuit 148 includes a pair of NAND gates 150 and 152 the first NAND gate 150 acting as an inverter in the circuit 148. The output of the NAND gate 150 is connected to one input of the NAND gate 152, the other input of the NAND gate 152 being connected to the 1 KHz clock 58. Gated clock signals appear at the output of the NAND gate 152 as shown in Figure 13.

The output of the NAND gate 152 is connected to the input of a binary counter 154 which counts the number gated clock signal pulses, the output of the counter 154 indicating the number in binary form.

The first, fourth and eighth bits of the counter 154 are applied to the inputs of a three-input NAND gate 156 the output of which will go to a logical low state to provide a long pulse signal when all the input signals are in a logical high state thereby indicating that one of the injector pulses exceeds 13 milliseconds.

The circuit 148 also includes a monostable multivibrator or a one-slot 158 whose input is connected to the output of the NAND gate 150. A reset pulse appears on the output of the one-shot 158 which is applied to the reset input of the counter 154 on the trailing edge of an injector pulse signal from the NAND gate 150. The one-shot 158 is biased by the reference voltage, +V1, through a resistor, R40. A capacitor, Cs, is connected at the opposite end of the resistor, R40, and across two of the inputs of the one-shot 158 in a conventional manner. The counter 154 is reset by the one-shot 158 so that the counter 154 is able to count the followin gated clock pulses.

The resistor, R40, and the capacitor, C5, = 100 kohms and .01 microfarad, respectively.

Referring now to Figure 1 and Figure 9, an indicator means or a fault indicator circuit generally indicated at 160 is shown. Any or all of the seven detected faults are simultaneously displayed by the fault indicator circuit 160. The seven detected faults are; missing &num;1 trigger signal, the missing &num;2 trigger signal, missing &num;1 injector signal, missing &num;2 injector signal, ignition power low signal, ECU power low signal and long pulse signal.

The output or fault signals are inverted by their respective inverters 162, 164, 166, 168, 170, 172, and 174. Each inverted fault signal is processed by its own RC network to generate a positive voltage spike.

The RC networks comprise resistor-capacitor pairs, R41 and C6, R42 and C7, R43 and C8, R44 and Cg, R45 and C1O, R46 and C11, and R47 and C12.

The circuit 160 also includes seven R/S latches comprising latches 176, 178, 180, 182, 184, 186 and 188. Each of the latches 176 - 188 has its set input connected to its corresponding RC network. The positive voltage spikes developed by the RC networks set the outputs of their corresponding RIS latches to logical high states.

The circuit 160 also includes a plurality of driver transistors T3, T4, T5, T6, T7, T8 and Tg corresponding to the latches 176 - 188. When the output of any of the latches 176 - 188 is in its logical high state its corresponding driver transistor, T3 - Tg, is "turned on" through its respective base resistor, R48 - R54.

The circuit 160 also includes a like plurality of light emitting diodes (LED's) 190, 192, 194, 196, 198,200, and 202. When a particular transistor T3 - Tg is "turned on" its corresponding LED, 190 - 202, is energized by the reference voltage, eV1 through its respective resistor, R55 - R6,. Any LED 190 - 202 that is energized will remain energized until a reset switch or button 204 is pressed thereby resetting the latches 176 - 188 along a common reset lead which presents the reference voltage, +V1, to each reset input of the latches 176, - 188. A grounding resistor R62 is connected to the switch 204 and the reset inputs of the latches 176 - 188 in a conventional fashion. In this way, the circuit 160 allows any and all of the faults to be displayed simultaneously.

Each of the capacitors C6 through C12 = .001 microfarads; each of the resistors R41 - R47 = 100 kohms; each of the resistors, R48 - R54 = 5 kohms; each of the transistors T3 - T9 comprise npn 2n341 5 transistors; each of the resistors R55 - R61 = 100 ohms; and the resistor R62 = 5 kohms.

Referring now to Figure 1 and Figure 6, a second indicator means or a first error detection circuit generally indicated at 206 is shown. Four faults including trigger missing, injector missing, ignition power low and ECU power low may be displayed by the circuit 206. In general, the circuit 206 displays the first fault that occurs, which fault will lock out any other subsequent faults from being displayed.

The circuit 206 includes NOR gates 208,210,212, and 214 each having as one of its inputs one of the fault signals. Each of the other inputs of the NOR gates 208 - 214 are connected to the 0 output of a D flip-flop 216 which is reset by the reset swtich 204 thereby causing the 0 output to go to its logical low state which, in turn, allows any fault signal to change the output of its corresponding NOR gate, 208 - 214.

The outputs of the NOR gates 208 - 214 are connected to the inputs of a NAND gate 218. The output of the NAND gate 218 is logically low if all of its inputs are logically high thereby indicating that none of the input signals show a fault condition. If one of the input fault signals goes logically low, thereby indicating a fault, the output of the NAND gate 28 goes to a logical high state thereby activating a monstable multivibrator or one-shot 220 whose input is conncted to the output of the NAND gate 208. The output of the one-shot 220 is connected to and sets the flip-flop 216 so that the Q output goes to a logical high state thereby disabling the NOR gates 208-214.

The circuit 206 also includes a like plurality of RIS latches 222, 224, 226, and 228 connected at their set inputs to the output of their corresponding NOR gate, 208 - 214. When one of outputs of the NOR gates 208 - 214 goes to its logical high state is sets its corresponding R/S latch 222 - 228.

The circuit 206 also includes a like plurality of driver transistors T,0, T1 , T12 and Ta3 the bases of which are connected to the outputs of their corresponding latch 222 - 228 through their corresponding base resistors R63, R64, R65 and R66. The logical high output of one of the latches 222 - 228 will "turn on" its corresponding driver transistors Tlo - T13.

The circuit 206 also includes a like plurality of LED's 230,232, 234, and 236, the cathodes of which are connected to the collectors of their corresponding transistors T1O - T13 through collector resistors, R67, R68, R69 and R70. When one of the transistors T10 - T13 is "turned on" its corresponding LED, 230 - 236 is energized by the reference voltage, +V1, which is connected at the anodes of the LED's 230 - 236.

Each of the R/S latches 222 - 228 is reset by a monostable flip-flop or one-shot 238. A reset pulse appears at the output of the one-shot 238 when the reset switch 204 is closed, the reset switch 204 being connected to the input of the one-shot 238 in a conventional fashion.

The one-shots, 220 and 238, have connected thereto, in conventional fashion, RC networks including resistors, R67, and R66, and capacitors, C13 and C14, respectively. An RC network including a resistor, R59, and capacitor, C15, iS connected to the output of the one-shot 220 also in a conventional fashion to provide a time delay. Connected to the reset input of the flip-flop 216 is a biasing resistor, R70.

In the event of a trigger missing fault, an injection missing fault will also be present. Typically, it will not be known whether the trigger missing fault or the injection missing fault occurred first. The first fault detection circuit 206 as previously described will show both the trigger and injector missing pulse signals as occurring first. One solution to this problem is to make the .47 millifarad capacitors of the D to A convertor circuits in the circuits, 124 and 126, to be twice as large as the corresponding capacitors in the D to A convertor circuits in the circuit, 60 and 62.

The transistors T1O -T13 comprise of npn 2n3415 transistors; the value of resistors R63 - R64 = 5 kohms; the value of the resistors R67 - R70 = 180 ohms; the value of the resistors R67 and R68 = 100 kohms; the value of the capacitors C14 and C13 = .001 microfarads; the value of the resistor R69 = 50 kohms; the value of the capacitor C15 = 75 picofarads; and the value of the resistor, R70 = 100 kohms.

In general, the test apparatus operates by first sampling selected electric signals which represent certain parameters of the engine control system of the electronic control unit (ECU) on its inputs, 22 - 36.

The sampled electric signals are processed by the test apparatus by measuring the time duration of six of the sample signals in the circuits 60,62, 126, 124, and 148. Four of the measured signals are compared two by two in the circuits 86 and 128. Two of the sampled inputs signals are tested by the circuits 48 and 44 which provide corresponding output signals.

The circuit 148 not only measures the two sampled input signals but also tests them and provides an output signal indicating the result of the tests. The circuits 86 and 128 not only compare the measured signals but also test the resulting compared signals and provide corresponding output signals indicating the results of the tests.

The output signals corresponding to the sampled input signals are continuously and separately displayed by the circuit 160 to indicate unfavorable results of the processing which includes the aforementioned testing, measuring, the comparing until the circuit 160 is reset by the common reset switch 204.

Each of the circuits 86 and 128 also logically combine two of the output signals, the results of the combinations appearing at the inputs of the circuit 206 along with the output signals from the circuits 44 and 48. The circuit 206 displays which one of its input signals was the first to malfunction until reset by the common reset switch 204.

While the invention has been described specifically with reference to preferred embodiments thereof, various changes and modifications may be made all within the full and intended scope of the claims which follow.

Claims (7)

1. A test apparatus adapted for connection to the electronic control system of an internal combustion engine for monitoring a plurality of electric signals representing certain parameters of the electronic control system and for providing an indication as to which of the monitored signals malfunctions and as to which signal was the first to malfunction, characterized in that said apparatus comprises: sampling means including a like plurality of input means, each of said input means corresponding to a particular electric signal, for sampling the plurality of electric signals; signal processing means connected to each of said input means for processing said sampled signals with a plurality of reference values, said signal processing means providing a like plurality of output signals indicating the results of said processing, each of said output signals containing information as to whether its corresponding sampled signal malfunctioned; indicator means including a like plurality of circuit means, each of said circuit means connected to said signal processing means, for indicating unfavorable results of said processing from said output signals, each of said circuit means including a display means for identifying which of said electrical signals malfunctioned, the display means identifying which signals malfunctioned for a desired period of time, and second indicator means connected to said signal processing means for indicating for a desired period of time which one of selected ones of said electrical signals was the first to malfunction, whereby the second indicator means provides a malfunction priority indication.

2. An apparatus as claimed in claim 1, wherein said signal processing means includes measuring means for measuring the time duration of at least two of said sampled signals and providing corresponding time duration signals.

3. An apparatus as claimed in claim 2, wherein said signal processing means includes comparing means for comparing two time duration signals and providing a comparison signal indicating the result of said comparison.

4. An apparatus as claimed in claim 3, wherein said measuring means measures the time duration of at least three of said sampled signals, and wherein said signal processing means includes testing means for testing at least one sampled signal, one time duration signal, and said comparison signal with corresponding reference values, said testing means providing said corresponding output signals indicating the results of said testing.

5. An apparatus as claimed in claim 1 or claim 4, wherein there is provided logic circuit means connected to said second indicator means and said signal processing means for logically combining at least two output signals from said signal processing means, said second indicator means providing said malfunction priority indication from said logical combination.

6. An apparatus as claimed in claim 5, wherein there is provided reset means connected to said first and second indicator means for simultaneously removing said indications on said first and second indicator means.

7. An test apparatus adapted for connection to the electronic control system of an internal combustion engine constructed and adapted to operate substantially as herein described with reference to and as illustrated in the accompanying drawings.