GB2039186A

GB2039186A - Selfoscillating inverter

Info

Publication number: GB2039186A
Application number: GB7944087A
Authority: GB
Original assignee: Nilssen O K
Current assignee: Nilssen O K
Priority date: 1978-12-28
Filing date: 1979-12-21
Publication date: 1980-07-30
Also published as: DE2952654A1; FR2445649A1; JPS5592579A

Abstract

In a self oscillating push pull inverter, the switching on and off of the transistors is precisely controlled to minimize power losses due to common-mode conduction or due to transient conditions that occur in the process of turning a transistor on or off. Two current feed-back transformers (29, 33) are employed in the transistor base drives; one being saturable (29) for providing a positive feed-back, and the other being non-saturable (33) for providing a subtractive feed-back to ensure rapid transistor turn off. <IMAGE>

Description

SPECIFICATION High efficiency inverter and ballast circuits FIELD OF THE INVENTION This invention relates to the field of electrical energy conversion systems and more particularly to electrical inverter circuits utilizing a solid state active element oscillator of the multivibrator type to convert DC voltage into AC voltage.

Inverter circuits, as considered herein, are designed to convert a DC input voltage into high frequency alternating output voltage. The push-pull types of inverter circuits are recognized as the most efficient as a class for this purpose. However, even these circuits are plagued with a number of identifiable inefficiencies. The most significant of these is the energy loss that occurs due to common-mode conduction. This occurs when both transistors conduct simultaneously.

The simultaneous conduction in turn is the result of an inherent and unavoidable delay associated with the turn-off action of applicable transistors. Such transistors normally do not have a corresponding delay associated with the turn-on action. Attempts have been made to correct this problem by selecting transistors with the lowest possible turn-off delay but this approach has required the use of very costly transistors.

A second major cause of energy loss in such a circuit is the power dissipation that occurs within each transistor during its turn-off transition. To minimize this loss, it is important to operate each transistor at near it maximum switching speed. However, it is even more important to prevent the collector voltage from rising significantly before the transistor has been fully turned off.

A third significant cause of energy dissipation results from turning on a transistor before its collector voltage has been reduced to its minimum level. This reduction of collector voltage occurs after the other transistor has been turned off, and as a result of its rising collector voltage.

Another cause of energy loss results from power dissipation within each transistor while it is conducting. To minimize this loss, it is necessary to provide adequate base drive corresponding to the collector current flowing at any given time. However, if this base drive is in excess of what is required to control the transistor, it can in itself become a cause of unnecessary power loss.

A great deal of design work on push-pull inverter circuits has been performed by others and reported in the patent art. Examples of such circuits are described in the U.S. patent to Jensen No. 2,997,664 entitled "Saturable Core Transistor Oscillator"; the U.S. patent of Wellford No.

3,248,640 entitled "Synchronizing Circuit"; the U.S. patent to Mehwald No. 3,324,411 entitled "Transistor Inverter with Inverse Feed-Back Frequency Stabilization Control"; the U.S.

patent to Bishop et al, No. 3,461,405 entitled "Driven Inverter Dead-Time Circuit"; the U.S.

patent to Paget, No. 3,579,026 entitled "Lamp Ballast"; the U.S. patent to Low, No.

3,663,944 entitled "Inverter Oscillator with Voltage Feed-Back"; the U.S. patent to Cox, No.

3,691,450 entitled "Power Inverter Oscillator Circuit"; the U.S. patent to Hook, No.

3,913,036 entitled "High Power High Frequency Saturable Core Multivibrator Power Supply"; and the U.S. patent to Ghiringhelli, No. 4,016,477 entitled "Novel Multipath Leakage Transformer and Inverter Ballast". The above identified U.S. patents have recognized some of the causes of power loss within a multivibrator inverter circuit and have proposed solutions for partially correcting for these losses. However, none have recognized all of the causes of such power loss as identified herein not have they suggested solutions for eliminating such power losses within an economical and operationally effective frame of reference. Some also employ independent oscillator or drive circuits which add to the total cost of the inverter and may be wasteful of energy in and of themselves.

Another approach to the solution of most of the identified problems has been described in my pending U.S. patent application entitled "High Efficiency Push-Pull Inverters", filed March 20, 1978, and assigned Serial Number 890,586. This invention employs a saturable inductor across the base-emitter junction of each transistor for providing, when saturated, a near-short circuit path for the rapid evacuation of the charge carriers stored in the junction, and thereby ensures the rapid turn-off of the respective transistor.

DISCLOSURE OF THE INVENTION It is an object of the present invention to provide an improved self-oscillating, push-pull inverter circuit that is both efficient in operation and economical to manufacture. This invention is particularly advantageous in applications where the available DC supply voltage is higher than 50 volts as would be the case for rectified voltage from a conventional power line source.

It is another object to provide an improved push-pull inverter circuit in which energy loss due to common-mode conduction of the switching transistors is substantially eliminated.

It is still another object to provide an improved inverter circuit of this general type in which energy loss within each transistor during its turn off transistion is minimized. In this regard, it is important to prevent the collector voltage from rising significantly before the transistor has been turned off completely.

It is still another object to provide an improved inverter circuit effective to minimize energy dissipation which results from turning on a transistor before its collector voltage has been reduced to its minimum level.

It is still another object to provide an improved inverter circuit in which an efficient base drive is provided to minimize power dissipation within each transistor while it is conducting. In this regard the base drive is adequate for this intended purpose without being excessive. This prevents the base drive from becoming a source of energy dissipation in and of itself.

According to one aspect of the invention there is provided an inverter circuit with an output connected to a load and having a pair of switching transistors with base-emitter junctions and adapted to convert DC voltage supplied from a DC source having positive and negative terminals respectively connected therewith into an AC output voltage, comprising: first drive circuit means connected between the base-emitter junctions of the transistors and operable to provide intermittent positive feedback signals for causing the alternating conduction of the transistors; and second drive circuit means also connected between the base-emitter junctions of the transistors and operable to provide intermittent subtractive feedback signals for rapidly turning off a conducting transistor whereby an alternating current is caused to flow through the load.

BRIEF DESCRIPTION OF THE DRAWINGS An embodiment of an inverter circuit according to the invention will now be described by way of example with reference to the accompanying drawings wherein: Figure 1 is a schematic diagram of a preferred embodiment of the inverter circuit of the present invention; Figure 2 are characteristic wave form diagrams of the collector voltage, base voltage and collector current for both of the switching transistors of Fig. 1; Figure 3 is a circuit diagram of a modified inverter circuit adapted to operate at higher DC potentials; Figure 4 is a schematic diagram of the inverter circuit of Fig. 1 specifically adapted as a ballast for fluorescent lamps; and Figure 4A is a schematic diagram of a bridge rectifier adapted for use with the circuit of Fig.

4.

BEST MODE OF CARRYING OUT THE INVENTION The improved high efficiency inverter circuit of the present invention is illustrated schematically in Fig. 1 and is designated generally by the numeral 1 0. The circuit 10 comprises a main transformer 11, a pair of relatively high-power switching transistors 1 2 and 13, a saturable current transformer 14 and a non-saturable current transformer 15. The main transformer 11 has a primary winding lip and a secondary winding ills. The secondary winding 11s is connected to deliver a high frequency alternating output voltage to a pair of terminals 1 7 and 18. The transistor 12 has a base 12b, a collector 1 2c and an emitter 12e.Similarly, the transistor 1 3 has a base 13b, collector 1 3c and emitter 13e.

The inverter circuit 10 also comprises a resistor 19, a capacitor 20 and diodes 22, 23, 24, and 25. The transformer 14 has windings 26, 27 and 28 wound on a torroidal magnetic core 29. Similarly, the transformer 15 has windings 30,31 and 32 wound on a torroidal magnetic core 33. The primary winding 11 p has a center tap 34 connected to a terminal 35 which is connected to a positive source of DC voltage or B + . Similarly, the transformer 1 5 winding 32 has a center tap 36 connected to a negative terminal 37 or B - .The center tap 34 on the transformer 11 is connected by a lead 38 to one end of the resistor 19, and the other end of resistor 1 9 is connected by means of the lead 39 to the base 1 2b of transistor 1 2. The lead 39 is also connected to one end of winding 28 of transformer 1 5 and to a cathode 22c of diode 22, and to an anode 24a of the diode 24. The other end of winding 28 is connected by a lead 40 to the base 13b, to a cathode 23c of diode 23 and to an anode 25a of diode 25. The two ends of winding 32 of transformer 1 5 are connected to cathodes 24c and 25c. The emitter 1 2e of transistor 1 2 is connected by means of a lead 42 to an anode 22a of diode 22 and to the Bterminal 37.Similarly, the emitter 1 3e of transistor 1 3 is connected by means of a lead 43 to an anode 23a of diode 23 and to the B-terminal 37.

One end of the primary winding 11p of transformer 11 is connected by means of a lead 44 to one end of the winding 26 of transformer 14. Similarly, the other end of the winding lip of transformer 11 is connected by means of a lead 45 to one end of the winding 27 on the transformer 14. The other ends of the windings 26 and 27 are connected by means of lead 46 and 47 to the windings 30 and 31, respectively, of the transformer 15. The other end of winding 30 is connected by means of the lead 48 to the collector 1 2c of transistor 12, and the other end of winding 31 is connected by means of a lead 49 to the collector 1 3c of transistor 13. The capacitor 20 is connected between the leads 48 and 49.

The operation of the inverter circuit of Fig. 1 may be described in conjunction with the wave form diagrams of Fig. 2. A positive starting bias signal is provided from B + through resistor 1 9 and lead 39 and through winding 28 and lead 40 to the bases 1 2b and 13b, respectively. This bias current is effective to trigger one or the other of the transistors 1 2 and 1 3 into conduction.

Assume that transistor 12 is the conducting transistor at the time t,; the base voltage Eb has been driven to a positive state, and the collector current lc rises. The collector voltage Ec is substantially zero or only slightly positive while the transistor 1 2 is conducting. Current from B + flows through the main transformer winding 11 p and lead 44 through winding 26 of transformer 14, through winding 30 of transformer 15, and through lead 48, collector 12c, emitter 1 2e and led 42 to B -. The current flowing through winding 26 produces a changing flux in the core 29 of transformer 1 4. So long as this core 29 is not saturated, the winding 28 provides a positive feed-back to the base 12b.The current path from one end of the winding 28 is through lead 39, base 12b, emitter 12e, and lead 42 to B - . A return current path to winding 28 is provided from B - through lead 43 diode 23 and lead 40 to the other end of winding 28.

At some time t2 core 29 becomes saturated and positive feedback to the base 1 2b ceases.

The winding 28 in effect becomes a short circuit between the bases 1 2b and 13b. Until the core 29 saturates, the transformer 14 provides the dominat feed-back to the base drive circuit.

However, when the transfomer core 29 does saturate, the transformer 1 5 then provides the dominant feedback control. The transformer 1 5 is designated so that the core 33 is not saturated by the same conditions that cause the transformer 14 to saturate. The winding 32 of transformer 1 5 provides a subtractive feedback through the diode 24 to the base 12b.The implication of this performance is that as soon as the transformer 1 4 saturates the base drive current reverses, thereby rapidly evacuating the stored charge carriers from the base emitter junction of transformer 1 2. As soon as the base emitter junction of transistor 1 2 is evacuated of carriers, the current taken by winding 32 of transformer 1 5 starts flowing through the diodes 22 and 24 and center tap 36 to B - It should be noted that the subtractive feedback which causes the rapid evacuation of the charge carriers from the base emitter junction of transistor 1 2 prevents any positive voltage transients on the base 1 3b of the opposite transistor 1 3. The saturated core 29 of transformer 14 in effect provides a short circuit through the windings 28 between the bases 1 2b and 1 3b so that both remain negative.Due to the unidirectionally subtractive current from transformer 15, both base voltages will stay at a negative voltage for as long as current flows through winding 32 of transformer 15, which is for as long as collector current lc continues to flow. The implication of this is that it does not matter that the transistors 1 2 and 1 3 may have significant turn-off delays. The non-conducting transistor simply cannot be turned on until current has stopped flowing through the opposite transistor.

The capacitor 20 connected between the collectors 12c and 1 3c serves to restrain the rate of rise until time t4 of the collector voltage Ec after the conducting transistor 1 2 is turned off. As a result, the transistor 1 2 is turned off completely before its collector voltage rises to any significant level. This greatly minimizes power dissipation in the transistor during the turn-off transition. It should be noted that the capacitor 20 also bridges the windings 30 and 31 of the transformer 1 5 and provides a path for continuity of current flow through the current feedback transformers 14 and 15.

The main transformer 11 contains some amount of leakage inductance. This inductance in effect provides inertia to the current flow so that the collector voltage Ec on the transistor 1 2 that is being turned off could rise to a very high level. However, the ultimate voltage that can be reached by the collector of the off-transistor cannot be more than twice the magnitude of B + From the nature of the circuit, it may be noted that when the collector voltage Ec of one transistor has risen to a magnitude of twice B +, the voltage on the collector of the other transistor has fallen to zero. Also, the collector voltage cannot rise beyond twice the magnitude of B + because the other transistor 13, in combination with its base to emitter diode, acts as a clamp.

In order to eliminate the turn-on losses entirely, the off-transistor should not be turned on until after its collector voltage has reached zero. This is precisely what is accomplished by the base drive circuits in the operation of the transformers 14 and 1 5.

The operation of transistor 1 3 can be described by reference to the lower or second set of wave form diagrams of Fig. 2, which are substantially identical to the upper set shown for transistor 12---only displaced in time. Between time t3 and t4 the collector voltage E0 of transistor 1 3 decreases to slightly below zero. The rate of decline corresponds to the rate of rise of the collector voltage of the now "off" transistor 1 2. This rate of change is restrained by the charging of the capacitor 20, and continues until claimping takes place. At time t4, a negative current lc begins to flow between the base 1 3b and collector 1 3c and continues until time t5.

The path for this current flow is from B - through diode 23, the base-collector junction of transistor 13, windings 31 and 27, and winding 11 p of transformer 11 to B + . This results in a return of energy to the power supply, during this time span. The transistor 1 3 and diode 23 in this mode function as a clamp to limit the magnitude of the voltage of the collector 1 2c of transistor 1 2.

At time t5, the base 1 3b is driven positive and transistor 1 3 begins to conduct in a positive direction. The path for this current flow lc is from B + through the right half of winding 11 p, through windings 27 and 31, collector 13c, and emitter 1 3e to B - . A positive feedback is provided from winding 28 of transformer 14 to the base 13b. The current lc continues to flow until time t7, shortly after the transformer 14 saturates at time t6, and positive feedback to the base 1 3b ceases. At this time, the transformer 1 5 takes over and supplies a subtractive feedback to the base 1 3b rapidly evacuating its charge carriers.The transistor 1 3 is turned off and its collector voltage begins to rise until time t8, completing the cycle of operation.

The alternate conduction of each transistor 1 2 and 1 3 produces current flow through winding 11p of transformer 11 in opposite directions. This alternating current in winding 11p is transformed into a high-frequency AC voltage at the secondary winding 11s which is supplied to the output terminals 1 7 and 1 8.

Referring now to Fig. 3, the circuit therein illustrated is capable of operating at higher DC potentials for a given voltage limit on the transistors than is the circuit of Fig. 1, although the principles of switching control are substantially the same. The inverter circuit of Fig. 3 is designated generally by the numeral 110 and comprises the main transformer 111, switching transistors 11 2 and 113, a not-saturable current transformer 11 4 and a saturable current transformer 11 5. The circuit 110 also includes a pair of capacitors 11 6 and 11 7 connected in series between a B + terminal 118 and a B - terminal 11 9. The circuit 110 also includes a capacitor 120, a resistor 121 (or other bias means) and diodes 122 and 123, 124, 125, 126 and 127. The transformer 114 has windings 130, 131, and 1 32 wound on a toroidal core 133. Transformer 11 5 has windings 134, 135, and 1 36 wound on a toroidal core 1 37. The collector of transistor 11 2 is connected by means of a lead 140 to the B + terminal 11 8. The emitter of transistor 112 is connected to the collector of transistor 11 3 by a lead 141. The emitter of transistor 11 3 is connected to a lead 142 which is connected to the B - terminal 119.The transistors 11 2 and 11 3 are effectively connected in series between the B + and B terminals and their operation is controlled by the base drive circuit which includes the transformers 114 and 11 5 so as to deliver a high frequency alternating voltage output to the secondary 11 Is of transformer 111.The transistors 112 and 11 3 in this embodiment must be capable of withstanding a DC voltage equal to B + whereas transistors 1 2 and 1 3 of Fig. 1 must be capable of withstanding twice B + One of the primary winding 111 p of transformer 111 is connected to a junction 145 between the capacitors 11 6 and 11 7. The same end of winding 111p is connected to one end of the resistor 121. The other end of resistor 1 21 is connected by a lead 146 to the anode of diode 125 and to one end of winding 1 32 on the transformer 114.The other end of winding 1 32 is connected to a lead 147 which in turn is connected to one end of the winding 1 36 on the transformer 115 and to the cathode of diode 127. The other end of winding 1 36 is connected by means of lead 148 to the cathode of diode 1 23 and to the base of transistor 11 3.

The other end of winding 111 p of transformer 111 is connected by means of a lead 1 50 to one end of the winding 1 31 on transformer 114. The other end of windings 1 31 is connected by a lead 1 51 to one end of winding 1 35 on the transformer 11 5. The other end of winding 135 is connected to lead 141. The lead 141 is connected to the emitter of transistor 112, the collector of transistor 11 3, the cathode of diode 124, the anode of diode 122, and the anode of diode 1 26 and to one side of the capacitor 1 20. The other side of the capacitor 1 20 is connected to the B - lead 142.One end of the winding 1 30 of transformer 14 is connected by a lead 1 55 to the base of transistor 112, to the cathode of transistor 122, and to one end of winding 1 34 of the transformer 11 5. The other end of winding 1 30 is connected to the anode of diode 124. The other end of winding 1 34 of transformer 11 5 is connected to the cathode of diode 126.

In operation, the circuit of Fig. 3 functions as follows: The total DC potential between the terminals 11 8 and 11 9 is applied across the capacitors 11 6 and 117, the junction 145 generally being at one-half of the total DC potential; although it is to be understood that the series connection of capacitors 11 6 and 11 7 could be a voltage divider of some comparable type. The capacitors 11 6 and 117 block the passage of DC but readily permit the passage of alternating current. A DC bias is applied from junction 145 through the resistors 121, lead 146, winding 132, lead 147, winding 136, and lead 148 to the base of transistor 11 3. The transistor 11 3 is triggered into conduction and and current flows from the junction 145 through the primary winding 11 lip, lead 150, winding 131, lead 151, winding 135, and lead 141 to the collector of transistor 11 3, and through the emitter of transistor 113 to B - . A return path is provided through the capacitor 117 to the junction 145. The current flowing through winding 135, together with the effect reflected by winding 136, magnetizes the core 137 in one direction.Until this core 1 37 is saturated, the transformer 11 5 provides a dominant positive feedback through winding 1 36 to the base of transistor 11 3 to maintain this transistor in a state of conduction. At some point in time, the core 1 37 of transformer 11 5 saturates and positive feedback to the base of transistor 11 3 ceases.At this point, the output of winding 1 32 of transformer 114 becomes the dominant control and delivers a subtractive feedback for the rapid evacuation of charge carriers from the base of transistor 11 3. The path for this current being through the windings 1 36 and 132, diode 1 25 and partially through diode 1 27 to B - until the charge carriers are evacuated. Thereafter, the return path is totally through diode 1 27. The principal function of the transformer winding 1 32 therefore is to maintain the voltage on the cathode of this diode 1 27 negative throughout both feedback cycles.The transformer 11 5 also provides a positive feedback from winding 1 34 to the base of transistor 11 2 to trigger this transistor into conduction. In this latter case, current now flows from B + through lead 140, the collector of transistor 112 and the emitter of 112 to the lead 141, and through the windings 135 and 131, the primary winding 111p to the junction 145. The return path to B + is provided from the junction 145 through the capacitor 11 6. The direction of current flow through the windings 131 and 111 p during this half cycle is in the opposite direction from that first described when transistor 11 3 was conducting so that an alternating voltage output is provided at the secondary 111s of the transformer 111.The winding 1 30 of transformer 11 5 continues to provide a positive feedback to the base of the transistor 11 2 to maintain it in conduction. When core 1 37 becomes saturated, this feedback ceases. Transformer 114 which is not saturated now provides a subtractive feedback to force evacuation of charge carriers from the base of transistor 11 2 through winding 1 30 and diode 1 24 to the emitter connection 141.

When the transistor 11 2 is cut off, the transistor 11 3 is triggered into conduction by a signal from winding 1 36 as previously described.

The circuit 110 thus provides an effective means for controlling the conduction of transistors 112 and 11 3 to provide a high frequency AC voltage output at the secondary Ills of transformer 111. The sequential operation of the saturable transformer 11 5 and non-saturable transformer 11 4 ensures that the non-conducting transistor 11 2 or 11 3 is not switched on until the conducting transistor is switched completely off. The capacitor 1 20 connected across the collector and emitter junction of transistor 11 3 restrains the rate of rise in voltage at the collector of transistor 11 3 during these transient stages.

When transistor 11 3 is turned off, the voltage at its collector begins to rise due to the current flowing from the junction 145 through transformer winding 111 p and through winding 1 35.

Further due to the inertia effect of the leakage inductance of transformer 111, the collector voltage continues to rise until it is clamped. A current path is then established from the collector of 11 3 through diode 1 22 and the base-collector junction of transistor 11 2 to B + . This negative current continues to flow until the energy stored in the leakage inductance of transformer 111 is discharged and returned to the power supply. This current also conditions the transistor 11 2 so that for a brief period it can conduct in the positive direction.

The circuit of Fig. 1 can utilize inexpensive and readily available transistors and with such transistors can operate at B + voltages as high as 300 volts. In the circuit of Fig. 3 DC voltages as high as 600 volts can be accommodated. This would correspond to root mean square voltages from the power line as high as 420 volts, if the power line voltage is directly rectified and used as a B + supply.

Referring now to Fig. 4, there is illustrated a circuit diagram of an inverter circuit similar to that of Fig. 1 but specifically adapted for use as a ballast for two 40 watt fluorescent lamps 201 and 202. The circuit as a whole is designated by the numeral 210 and comprises a transformer 211, having a primary winding 211 p. Secondary windings 203, 204 and 205 are provided for the filaments of the lamps 201 and 202. A current limiting inductor 206 is connected in series with the lamps 201 and 202 across the primary winding 211p.

The circuit 210 also comprises switching transistors 21 2 and 213, a saturable transformer 214, a non-saturable transformer 215, a resistor 21 9 and capacitor 220. The circuit 210 also contains diodes 222, 223, 224 and 225. The transformer 214 has windings 226, 227 and 228 on a toroidal magnetic core 229. Similarly, the transformer 215 has windings 230, 231 and 232 on a toroidal magnetic core 233. A center tap 235 of the primary winding 211 p of the main transformer 211 is connected to a B + terminal; and a center tap 237 of the winding 232 of transformer 215 is connected to a B - terminal.

A rectified DC voltage supply may be provided from a conventional AC source as shown in Fig. 4A. A pair of AC terminals 250 and 251 may be connected to a conventional 120 volt 60 hertz source across a bridge network 252. The bridge network 252 comprises 4 diodes 253, 254, 255 and 256 connected as shown. An electrolytic capacitor 257 can be connected across the output of the bridge network 252 to provide a filtered DC voltage to the B + and B terminals. The components utilized in the circuit 210 may be of the types and values as indicated in the accompanying table.

TABLE I Lamps 201 and 202 40 w R. S. Fluorescent Inductor 206 F41814 Cup Core Transformer 211 F4221 3 Cup Cores Transistors 212 and 213 FT49 Resistor 21 9 67 KQ Capacitor 220 1200 pf.

Diodes 222-225 IN 4001 Core 229 W40401 DC Core 233 W40402 DC The complete embodiment of the ballast circuit of Fig. 4, utilizing the components as indicated results in an efficient device that is small, light-weight, and compact. The ballast circuit constructed as indicated may have one-tenth or less of the total weight of a conventional ballast and may occupy a volume of one-sixth or less of that of the conventional ballast circuit. The circuit 210 functions in substantially the same manner as the inverter circuit described in Fig. 1 except that a relatively high frequency AC voltage is developed directly across the primary winding on the main transformer rather than across a secondary winding.

The circuits of the preferred embodiments have been described herein as utilizing NPN switching transistors. It is to be understood that the principles involved are equally applicable to comparable circuits utilizing PN P transistors.

Glossary of Terminology 1. Leakage inductance, as defined herein, shall mean an effective shunt of parallel inductance as typically obtained by providing an air gap in the magnetic path of the transformer.

2. The collector-emitter saturation voltage is a condition where there is adequate base current to correspond to the collector current so that additional base current will not substantially decrease the collector-emitter voltage. The collector voltage, as described herein, is referenced to the emitter.

It is to be understood that the embodiments shown and described are by way of example only and that many changes may be made thereto without departing from the scope of the invention as defined in the claims. The invention is not to be considered as limited to the embodiments shown and described except insofar as the claims may be so limited.

Claims

1. An inverter circuit with an output connected to a load and having a pair of switching transistors with base-emitter junctions and adapted to convert DC voltage supplied from a DC source having positive and negative terminals respectively connected therewith into an AC output voltage, comprising: first drive circuit means connected between the base-emitter junctions of the transistors and operable to provide intermittent positive feedback signals for causing the alternating conduction of the transistors; and second drive circuit means also connected between the base-emitter junctions of the transistors and operable to provide intermittent subtractive feedback signals for rapidly turning off a conducting transistor whereby an alternating current is caused to flow through the load.

2. The inverter circuit of Claim 1 wherein: said first drive circuit means includes a saturable current transformer with a magnetic core.

3. The inverter circuit of Claim 2 wherein: said current transformer is effective to deliver a positive feedback signal until such time as said core becomes saturated.

4. The inverter circuit of Claim 1 wherein: said second drive circuit means includes a non-saturable current transformer.

5. The inverter circuit of Claim 4 wherein: said non-saturable transformer delivers said subtractive feedback signal after said core of said first drive circuit means becomes saturated.

6. The inverter circuit of Claim 5 wherein: said current transformer of the first drive circuit is connected to the base-emitter junction of each of said transistors, and said current transformer of the second drive circuit is also connected to a base-emitter junction of each of said transistors.

7. The inverter circuit of Claim 5 including: a power output transformer having a winding with a center-tap connected to the positive terminal of the DC source; and said second current transformer has a winding with a center-tap connected to the negative terminal of the DC source.

8. The inverter circuit of Claim 1 wherein: said circuit is self-oscilliating for controlling the conduction of the switching transistors.

9. The inverter circuit of Claim 1 wherein: each of the switching transistors has a collector element; and a capacitor is connected between said collector elements.

10. The inverter circuit of Claim 1 including: a power output transformer with some shunt leakage inductance; and means for connecting the power output transformer to the collectors of the transistors.

11. An inverter circuit connected to a load and having a pair of switching transistors connected in series across a source of DC voltage, with each transistor having a base-emitter junction, and adapted to convert DC voltage supplied from the DC source into an AC output voltage comprising: first drive circuit means conected between the base-emitter junction of the transistors and operable to provide intermittent positive feedback signal for causing the alternating conduction of the transistors; and second drive circuit means also connected between the base-emitter junction of the transistors and operable to provide intermittent subtractive feedback signals for rapidly turning off a conducting transistor whereby an alternating current is caused to flow through the load.

1 2. The inverter circuit of Claim 11 including: a voltage divider connected across said DC source and operable to provide a divided DC voltage to said drive circuit means.

1 3. The inverter circuit of Claim 1 2 wherein: said voltage divider is a series connection of at least two capacitors.

14. The inverter circuit of Claim 1 2 including: a power output transformer connected between the transistors and said voltage divider and operable to deliver an AC output voltage to the load produced by the alternating conduction of the transistors.

1 5. An electrical inverter circuit having a pair of alternately conducting switching transistors, each with a collector and base-emitter junction and adapted to convert a unidirectional input voltage into an alternating output voltage comprising: drive control means effective to provide subtractive bias means to the base-emitter junctions of both transistors during periods when their collector-emitter voltages are significantly greater than the transistor collector-emitter saturation voltages.

1 6. The inverter circuit of Claim 1 5 including: an output transformer connected to the collectors of the transistors and having a significant shunt leakage inductance effective to produce a large voltage swings at the collectors of the transistors.

17. The inverter circuit of Claim 1 6 including: a capacitor effectively connected in parallel with said transformer and effective to limit the rate of voltage rise and decline at the collectors of the transistors.

1 8. The inverter circuit of Claim 1 7 wherein: said drive control means includes positive feedback means whereby the inverter circuit is selfoscillating.

1 9. The inverter circuit of Claim 1 8 wherein: said positive feedback means includes a saturable transformer connected between said output transformer and the base-emitter junctions of the transistors.

20. The inverter circuit of Claim 19 wherein: said saturable transformer is a current transformer.

21. The inverter circuit of Claim 15 wherein: said subtractive bias means includes a non-saturable current transformer.

22. An electrical inverter circuit containing a pair of alternately conducting switching transistors, each having a collector, base and emitter, and adapted to convert a unidirectional input voltage into an alternating output voltage, and with each transistor having a cyclical emitter-collector voltage waveform characterized by four distinct periods within each cycle, namely: a period when the magnitude is low and substantially constant, a period when it increases rapidly, a period when it is high and substantially constant, and a period when it decreases rapidly and including: drive control means connected to the base-emitter junction of each transistor and operable to maintain each reversely biased during all periods other than the period when its voltage is low and substantially constant.

23. The inverter circuit of Claim 22 wherein: said drive control means biases the base-emitter junction forwardly during the period when its voltage is low and substantially constant.

24. An electrical inverter circuit containing a pair of alternately conducting switching transistors, each having a base-emitter junction and a collector-emitter junction, and adapted to convert a unidirectional input voltage into a alternating output voltage, comprising: reverse bias means connected to the base-emitter junction of each transistor and operable to maintain each transistor reversely biased whenever its collector-emitter voltage is substantially greater than its collector-emitter saturation voltage.

25. An electrical inverter circuit containing a pair of alternately conducting switching transistors, each having a collector and base-emitter junction, and adapted to convert a unidirectional input voltage into a cyclical, trapezoidal shaped, alternating output voltage comprising: control means connected to said transistors and operable to effect alternating preriodic conduction thereof, said control means supplying to the base-emitter junction of each transistor a control signal effective to turn on a transistor only after its collector voltage has dropped substantially to its lowest level prior to application of the control signal thereto.

26. The electrical inverter circuit of Claim 25 wherein: said control means is operable to turn off a transistor by reversing the control signal supplied to said base-emitter junction.

27. The electrical inverter circuit of Claim 26 wherein: said base-emitter junction has stored charge carriers while conducting, and said control means is effective to turn off a transistor by the forced evacuation of charge carriers from said base-emitter junction.

28. The inverter circuit of Claim 25 wherein: said drive control means includes a current feedback transformer having at least one primary winding and a secondary winding for supplying said control signals.

29. The inverter circuit of Claim 28 including: a power output transformer having some shunt leakage inductance for deliverying the alternating output voltage; a capacitor connected between the collectors of the transistors; and said current feedback transformer primary winding being connected between said output transformer and said capacitor.

30. The inverter circuit of Claim 29 wherein: said output transformer stores sufficient inductive energy in its leakage inductance to cause the voltage at the collector of the first non-conducting transistor to rise to a level twice the magnitude of the unidirectional input voltage.

31. The inverter circuit of Claim 25 wherein: said control means is self-oscillating.

32. The inverter circuit of Claim 25 including: a shunting diode connected across the base-emitter junction of each transistor.

3. The inverter circuit of Claim 32 wherein: a first diode shunting the base-emitter junction of a first one of said transistors is operable to function as a clamp so as to limit the voltage rise at the collector the second one of said transistors to twice the magnitude of the unidirectional input voltage.

34. The inverter of Claim 33 including: a shunting diode connected across the collector-emitter terminals of each transistor.

35. A push-pull electrical inverter circuit having a pair of alternately conducting switching transistors, each having a control input element, and adapted to convert a unidirectional input voltage into an alternating output voltage comprising: first drive control means including saturable current feedback means for supplying control signals of one polarity to the control input element of each transistor; and second drive control means including non-saturable current feedback means for supplying subtractive control signals of another polarity opposite to said one polarity to the control input element of each transistor after said first saturable feedback means has saturated whereby a conducting transistor is rapidly and efficiently turned off.

36. An inverter circuit substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

36. An electrical inverter circuit having a pair of switching transistors, each with a control input element, and adapted to convert a unidirectional input voltage supplied from a source having a pair of input terminals into an alternating output voltage comprising: a series connection of the two transistors between the input terminals; first saturable feedback means connected to the control input elements of the transistors for supplying positive control signals; and second non-saturable feedback means also connected to the control input elements of the transistors for supplying subtractive control signals for alternately turning off a transistor.