GB2037048A - Liquid crystal game and training display apparatus - Google Patents

Abstract

An LCD game or training device utilizes a microprocessor 27 to control the display 21. Programmed microprocessor 27 signals a driver circuit 25 which applies a series of "on" and "off" voltages to the various rows and columns; it receives signals from manual controls 31, used in the game or training, and generates signals that turn certain segments of the matrix "on'' or "off" by addressing particular rows and columns within designated time intervals. More than one line and column may be addressed within any one time interval, depending on the image to be displayed, the sequence being varied by the microprocessor according to coincidence and movement of the pattern. Thereby, moving patterns are allocated more time than fixed to enhance their contrast. <IMAGE>

Description

SPECIFICATION LCD game and training display apparatus The present invention relates generally to matrix display devices that are electronically addressed by multiplex scanning techniques.

Liquid crystal displays are known to possess certain advantages and other display technologies. For example, the voltage and current requirements of an LCD are so low that it may be driven directly from complementary MOS circuitry. An LCD becomes not less, but more legible in direct sunlight; the brighter the sun, the better the display. The display, when organized in matrix form, can produce graphic symbols and designs just as readily as the more usual alphanumeric characters. LCDs provide long battery life for portable equipment. However, even though LCDs would seem a natural choice for large-area multiple character applications, there is one big obstacle. The cost of driving and terminating LCDs made up of six or more characters is considerable.Although multiplexed LCD displays exist in which more than six characters are displayed, such displays are only multiplexed to three levels.

Multiplexing techniques which would reduce the leads required and simplify the driver circuitry have been tried. However, few LCDs can be utilized with a multiplexing scheme. The complex characteristics of the LCD electro-optic response has to be taken into account to determine if it is suitable for multiplexing. Once an LCD is determined to be suitable for multiplexing, a particular multiplexing scheme must be chosen. Optimumly, the system is best designed when both the display and driver are considered together.

In a matrix-addressed LCD, each segment of the matrix plus its associated backplane is electrically equivalent to a lossy non-linear voltage dependent capacitor. The entire matrix array may be represented schematically as rows and columns interconnected by capacitors at each intersection. The representation of the matrix as rows and columns shall not be considered limiting, for other configurations are possible, such as polar, alphanumeric, or specific graphic symbols, for example. A series of select pulses drives each row, while a series of data pulses, which are either in phase or out of phase with the select pulses, drives each column.

In a matrix multiplexed addressed LCD display, simultaneously applying a select signal and a data signal determines the select or non-select status of any particular segment.

For a four-row, four-column LCD matrix, which is one-quarter multiplexed, the frame period Tf of the select waveform is divided into four equally spaced intervals corresponding to the time segments in which each row is addressed. Essentially, the matrix is addressed by multiplexing n rows with a select voltage and presenting data information with a data voltage. At the intersection of a row and column, the voltage that appears across an LCD segment is the difference between the select and the data voltages. On the average, for a period Tt a segment will be "on" if the voltage during the entire scan interval of all four rows is the row select voltage minus the minus of the data voltage, and "off" if the voltage is the row select voltage minus the data voltage.For the rest of the time period, the particular segment sees only the data voltage.

Because LCDs are sensitive to the root mean square voltage between their row and column conductors, they are very analogous to incandescent lamps in that their brightness is independent of the wave shape, so long as the RMS value of the applied voltage remains constant. In considering whether an LCD is suitable for multiplexing, the display's optical response, as a function of applied voltage, must be evaluated. Because LCDs are light modifers, as opposed to light emitters, the appropriate measure of optical response is either contrast or contrast ratio. Contrast is a measure of the amount of light that is reflected or transmitted by the symbol, whereas contrast ratio is the ratio of the energized to the unenergized image brightness.

Utilizing the contrast ratio definition, the threshold ratio may be defined as the RMS voltage necessary to turn "on" a segment divided by the voltage that will not turn on a segment. Once this ratio is known, the maximum number of lines or rows that can be multiplexed can be determined for a certain LCD. The number of rows that can be multiplexed while still maintaining an acceptable viewing contrast between the "on" and "off" segments will vary depending on the application. Nevertheless, the results obtained when more than eight lines are multiplexed may be entirely unacceptable.

Therefore, the multiplexing schemes utilized in the prior art are unable to provide an LCD display that has a relatively large number of rows. This size limitation has prevented use of the LCD matrix where larger displays were needed. Besides this size limitation, prior art multiplexing schemes for addressing a matrix of LCDs generally utilize driving circuitry that is expensive and cumbersome.

An object of this invention is to provide a game or training apparatus having a large LCD screen composed of a large number of rows for display of patterns and alphanumeric characters.

Another object of this invention is to provide a portable game or training apparatus having a display for displaying image patterns therein that can be easily changed and manipulated.

A further object of this invention is to provide a portable game and training appa ratus that utilizes a large liquid crystal display that is constructed as a segment matrix of rows and columns, the rows and columns being addressed under the control of a micro processor to provide improved contrast be tween "on" and "off" segments and de creased transition times.

These objects and other desirable features of the present invention are accomplished as follows. A segmented matrix organized liquid crystal display having a large number of rows (16, for example) is used as the display for the game or training apparatus. The display is driven by circuitry that multiplexes the rows at a level considerably less than the number of rows. The display is driven by a driver circuit that actuates switches to apply the correct series of "off" and "on" pulses to the rows and columns of the matrix. The microproces sor determines the images to be displayed and provides the driver circuit with signals that define the voltages that are to be placed on the rows and columns of the display.The microprocessor causes the rows and columns to be addressed in a multiplexed cycle that includes addressing more than one row and column within any one time frame, depending on the image to be displayed. The allocation of time slots in the multiplex addressing cycle can be dynamically revised to facilitate move ment of a certain pattern on the display. The microprocessor responds to operator-manipu lated controls for changing or moving the image displayed and dynamically allocates time slots to the various images being dis played as needed to maintain a high contrast ratio between the "on" and "off" segments and to decrease the transition time between the "on" and "off" state of a segment.

Figure 1 is a block diagram of a display system embodying the present invention; Figure 2 is a wave diagram illustrating signals applied to an LCD matrix according to thepriorart; Figure 3 is a graphic illustration of an LCD display; Figure 4 is an illustration of two modes of waveforms that are applied to an LCD display; Figure 5 is a waveform illustrating the signals applied to an LGD display embodying the present invention; Figure 6 is a graphic .illustration of an LCD display; Figure 7.is a block diagram of a -referned embodiment of a driver circuit; Figure 8 is a block diagram of an alternate preferred embodiment of a driver circuit;; Figure 9 is a schematic block diagram illustrating a.preferred embodiment of the voltage generating ;circuit -used in the driver circuits of Figs. 7;and 8 Figure 10 is a graphic illustration of an LCD display embodying the present invention; Figure 11 is an abstract illustration of the row and column addressing scheme embodying the present invention; Figure 12 is an abstract illustration of an alternate row and column addressing scheme embodying the present invention; Figure 13 is an abstract illustration of yet another alternate row and column addressing scheme embodying the present invention; Figure 14 is a flow chart illustrating the procedure followed by a microprocessor in moving a ball pattern illustrated on an LCD display;; Figure 15 is a flow chart illustrating the procedure followed by a microprocessor in moving a ball and paddle pattern on the display, and the steps taken upon incidence of the ball and paddle patterns on the display.

Fig. 1 is a block diagram illustration of an LCD display system 21 for a game or educational device. The LCD display system 21 comprises a liquid crystal matrix display 23 that is driven by a row and column driver 25, which provides a plurality of select control signals over lines 43 to the row conductors of the matrix 23, and a plurality of data signals over lines 45 to the column conductors of the matrix 23.

The row and column driver circuit 25 is controlled by microprocessor 27 which may, for example, be an Intel 8021 or similar microprocessor. The microprocessor sends data and control signals to driver 25 over bus 41. The microprocessor 27 and the row and column driver 25 receive power from a power source 29 over lines 37 and 39, respectively.

The voltage power source 29 has a capability of having the driver voltage for the microprocessor chip 27, and the voltage levels for the liquid crystal display matrix 23 adjusted as required.

A manually-manipulatable control device 31 transmits signals to the microprocessor 27 by way of pushbuttons or a variable potentiometer 33. The control 31 may also include an "on" and "off" switch, for example. Not shown in the drawings is a bender monomorph device which is actuated by the microprocessor to make a noise in response to incidence of a moving pattern, such as a ball with a paddle, or other pattern being displayed.

As was explained in the above section, liquid crystal displays can be addresed by a multiplexing scheme However, the shortcoming is that displays having a large number of rows cannot be driven in this manner because of the electro-optic response characteristics of the LCDs. Referring to Figs. 2 and 3, the prior art arrangement for driving a four-segment by four-segment liquid crystal display is illustrated. Fig 3 shows a four-column 81 by four-row 83 segment liquid crystal display, w.herein the segments 85, 87, 89, 91 and 93 of the 1 segment display is being driven "on" as the result of the multiplexing addressing scheme illustrated by the voltage waveforms for the columns and rows in Fig.

2.

As can be seen from Fig. 2, the one time frame is divided into four equal time periods, T1, T2, T3 and T4. Several time frames are illustrated as time sece 47. The voltage levels applied to the column and to the row conductors of the LCD matrix are a plus voltage, a zero voltage, or a minus voltage.

Each of the rows 49 is turned on or selected by a plus v3 e level in a different time period in each time frame. Thus, row 1 is selected by voltage 53 in time period Tt. Row 2 is selected by voltage 59 in period T2. Row 3 is selected by voltanuenge level 61 in time period T3. Row 4 is selected by voltage level 63 in time period T4. This completes one time frame and a single scan of rows from top to bottom of the LCD display in Fig. 3.

In time period T, of the next time frame, row 1, for example, is selected by a minus voltage level 55. A minus voltage level is utilized to select row 1 in the following time frame so as to impress AC across the LCD segments. In a subsequent time frame at T, the voltage 57 is again reversed. The reveral of voltages impresses AC across the crystals and prevents degradation of the crystal. For the pattern of segments activated in Fig. 3 that is, segments 85, 87, 89, 90, 91 and 93, the column voltages 67 must be as shown for columns 104. Segment 85, which is column 1 of row 1, must have voltage 53 applied to its row conductor and minus voltage 69 to its column conductor in time period T,. In column 2, the minus voltage 75 is applied to the column conductor at the same time row 2 is selected by voltage 59 at T2.At time period T2, minus voltage 77 is applied to the column conductor at the same time that voltage 61 selects row 3, thereby turning "on" segment 89. The minus voltage segments 77 and 79 span time periods T3 and T4, thereby causing segments 89 and 91 to turn on at time T3 and segments 90 and 93 to be activated when row 4 is selected by positive voltage 63 being applied to the conductor of row 4.

This sequential multiplexing scheme provides an acceptable appearance as long as the number of rows of the LCD matrix is not large. If a large number of rows are utilized, the RMS value of the voltages applied to each segment to be activated, which is the difference between the positive row voltage and the negative column voltage, is insufficient to provide an acceptable viewing contrast. Therefore, the sequential multiplexing scheme illustrated in Fig. 2 is limited to rather small LCD matrix displays.

Referring now to Fig. 4, the row and column voltage ratios applied across the segments of the LCD matrix of the present invention is shown for two different modes, a positive mode and a negative mode. These two different modes are utilized to provide the LCD crystals with AC. In other words, the control signals are switched between the position mode relationship 95 and the negative mode relationship 105 periodically at a rate that is sufficient to prevent LCD degradation.

As can be seen in the positive mode relationship 95, a three voltage level system 97, having voltages V0 (zero volts), V1, V2, and V3, is provided for the rows and a three level voltage system 101 is provided for the columns. The positive going voltage level 99 represents the "on" state for a row. The V, voltage level represents the "off" state. The negative going voltage level 103 represents the "on" state for the columns and the voltage level V2 represents the "off" state for the columns.

The negative mode of operation 105 is the exact opposite in that the rows receive negative going V2 to V0 pulse 107 for an "on" state, and the columns receive a positive going V, to V3 pulse 109 for an "on" state. A V2 level on the row conductors 105 is "off" for that row, and a V, voltage on a column conductor is "off" for that column.

Refer now to Figs. 5 and 6 which illustrate the multiplex scanning technique of the present invention. Fig. 5 illustrates the waveforms 114, 1 23 applied to the row conductors 1 37 and the column conductors 1 35 to provide the display on the 4 X 4 matrix 1 35 of Fig. 6. As can be seen from the time period sequence 111 of the scanning cycle, each time frame consists only of three time periods, T1, T2 and T3 for a 4 X 4 matrix. Whereas, the prior art utilized four time periods, one for each row of the matrix display.

In time period T1, row 1 is turned "on" by applying a voltage level 11 5 to it. Column 1 is turned "on" by applying the voltage level 125 to it. Rows 2, 3 and 4 have "off" voltages applied to their conductors, and columns 2, 3 and 4 have "off" voltages applied to their conductors in time period T,. At time period T1, then, segment 1 39 is turned "on".

At time period T2, row 2 has an "on" voltage 11 7 applied to it. Rows 1, 3 and 4 have "off" voltages applied to it. Column 2 has an "on" voltage 1 27 applied to it, whereas columns 1, 3 and 4 have "off" voltages applied to it. At time T2, then, segment 141 is turned on At time T3, rows 3 and 4 have an "on" voltage 119 and 121, respectively, applied to them. Column 3 has an "on" voltage 129 applied to it, and column 4 has an "on" voltage 131 applied to it. The other rows and columns have "off" voltages applied to them.

At time T3, therefore, segments 143, 144, 145 and 147 are turned "on". In the next time frame, T1, T2 and T3 are repeated.

The voltage relationships of the rows and columns illustrated in Fig. 5 is the positive mode: of Fig, 4. It should be understood, of course, that if the negative mode in Fig. 4 were used, the results would be the same and switching between the negative and positive mode would only result in different polarities on the row and column conductors. The RMS differential between the two remains the same.

What Figs. 5 and 6 dearly illustrate is that by addressing two rows within a single time period T3, the duration of one time frame is decreased by reduction of a number of time periods. As a result, the multiplexing cycle is no longer tied to the number of rows in the matrix display.

The scanning of rows in blocks such as rows 3 and 4 together, as illustrated in Fig. 5, of course, is dependent upon the particular image pattern to be displayed. It should be remembered that-the activation of rows within a certain time period is not constant. It is contemplated by this invention that they may be varied as required for the image patterns to be displayed. Thus, for example, the scanning of rows 3 and 4 in time period T3 may, at some other time frame, be changed to where the rows 1 and 4, or rows 1, 4 and 3 together, are scanned as a block within a certain time frame.

As will be explained more clearly hereinafter in conjunction with Figs. 10 through 13, the time periods T1, T2 and T3 within a particular time frame also are not fixed. It is the contemplation of this invention that time frame T1, for example, may be expanded to be twice or three times as great as time frames T2 and T3, which may be equal or again may be different time lengths, all depending upon the particular image pattern two be displayed on the LCD matrix.

Referring now to Fig. 7, which illustrates a preferred embodiment of the row and column driver circuitry 25 of Fig. 1, the row voltages are being applied to the matrix display 23 (Fig. 1) over m lines 43. The column voltages are being supplied to the matrix display 23 over n lines 45. The particular voltage supplied to the m row lines and n column lines at a specific time period within a multiplexing time frame depends upon the row and column switches, such as row switches 179, 177, 175 and column switches 169, 171 and 1 73. These switches receive the "on" and "off" row and column voltages over lines 188, 191, 189 and 193.Line 188 carries the "on" voltage for the rows; line 1 91 carries the "off" voltage for the rows. Line 1 89 carries the "on" voltage for the columns; the line 1 93 carries the "off" voltage for the columns.The switches 175, 177, 1 79 would thus, for a particular time period, be actuated to select either the "on" voltage on line 1 88 or the "off" voltage on 1 91. The switches 169, 171 and 173, for example, would be activated at a particular time period, depending ul:on the pattern to be displayed, to select either the 189 ' "on" ' voltage or the ' "off" voltage on line 1 93. The voltages are supplied by a driver voltage supply 165, a preferred embodiment of which is shown in Fig. 9 and will be explained hereinafter.

The row and column switches are driven by a latch 1 67, which has bit positions equal to the number m of rows in the matrix display, and the number n of columns in the matrix display. These bits are supplied over lines 195, 197, 199, 201, 203 and 205, for example, to the row and column switches.

The m+ n bit latch 167 is supplied with binary bits by a plurality of shift registers 163, 161, 159 and 157.

Assuming that a 16-row X 16-column is to be driven, latch 1 67 would be a 32-bit latch, and the four shift registers 163, 161, 159 and 157, would each be eight-bit shift registers. These shift registers are serial in, parallel out registers; wherein lines 181 provide eight bits to latch 167; lines 183 provide eight bits to latch 167; lines 185 provide eight bits to latch 167; and lines 1 87 provide eight bits to latch 167.

For the example of a 16 X > ( 1 6 LCD matrix, the data bus 149 from the microprocessor wo gid be a four-bit bus. Control lines 153, 15 i carry clocking information from the microprocessor. Line 1 53 carries a register shift clock; and line 151 carries the latch strobe clock which strobes the latch after all four shift registers 163, 161, 159 and 157 are loaded with their respective eight bits from the data bus lines 149. Accordingly, the shift clock signals on line 1 53 occur at an 8:1 ratio for the strobe clock on line 1 51.

Lines 39 are from the power source and provide the ground and VCC voltage to the driver voltage circuit 165, as will be more fully explained in connection with Fig. 9. Line 1 55 carries a data bit to the driver voltage 165, which causes the driver voltage to shift its mode from positive to negative, or negative to positive, in the manner illustrated in Fig. 4.

This shifting is done in accordance with the strobe latch signal on line 151.

Fig. 8 is an alternate preferred embodiment of the driver circuit 25 of Fig. 1, in that rather than utilizing four eight-bit shift registers for a 1 6 x 1 6 LCD matrix, eight four-bit latches 213, 215, 217, 219, 221, 223,225 and 227 are utilized. An eight-stage counter 209 clocks each four-bit latch over bus 211. Bus 211 contains a line connect between one of the eight output stages of counter 209 and a latch. Counter 209 is incremented by the bit clock on line 153, and reset by the strobe clock on line 1 51. Thus, te e counter 209 addresses bit latch 212, then bit latch 215, then bit latch 217, and so on, to bit latch 227 before it is reset by strobe clock on line 153.

The outputs of the latches 213 through 227 are supplied to the m + n latch- 1 67 over output lines 229, 231, 233, 235, 237, 239, 241 and 243 at the time the respective bit latches are loaded, so that at the time the strobe clock on line 1 51 is supplied by the microprocessor to the driver chip, latch 1 67 is fully loaded and applies the m + n bits to the switches 179, 177, 175, 169, 171 and 173 of the driver chip.

Referring now to Fig. 9, a preferred embodiment of the driver voltage circuit 1 65 is illustrated. The circuit includes three resistors 255, 257 and 259 connected in series between a Vc, voltage source and ground received over cable 39 from the power supply 29 of the system. The ground side of the voltage divider provides the V0 voltage level.

the Vc, side of the voltage divider provides the V3 voltage level. Opposite sides of resistor 257 provide the V, and the V2 voltage levels.

The use of these voltage levels to drive the LCD matrix was described in connection with Fig. 4.

Latch 245 receives a mode data signal on line 1 51 and a strobe clock on line 1 55 from the microprocessor, and accordingly, responds by driving switches 247, 249, 251 and 253 over control link 261 to switch between their respective inputs. Taking switch 247, for example, it would switch between input V0 and input V3. Switch 249 would switch between input V0 and input V3. Switch 251 would switch between input V, and input V2. Switch 253 would switch between input V, and input V2.So, accordingly, the voltage outputs on lines 187, 189, 191 and 193 would respectively provice the "on" voltage for the rows, the "on" voltage for the columns, the "off" voltage for the rows, and the "off" voltage for the columns.

Referring now to Figs. 10, 11, 1 2 and 13, a 1 6-column by 1 6-row LCD matrix 23 is shown as illustrating a particular image pattern which consists of a block of segments 267, a single segment 269, and a block of three segments 275. According to the scanning technique of the present invention, the driven circuits under the control of the microprocessor might address the x columns and y rows of the LCD display 23 in a time frame sequence shown in Fig. 11, which has three time periods 279. In time periods T1, row 10 and column 9 is turned "on". This causes segment 269 to be displayed. In time frame T2, row 1 5 and columns 7, 8 and 9 are turned "on". This causes segments 275 to be displayed.In time frame T3, rows 3, 4 and 5 and columns 1-16 are turned "on". This causes segments 267 to be displayed. To continue displaying this static image pattern, the time frame consisting of periods T1, T2 and T3 of Fig. 11 will be continually repeated.

As can be seen from the LCD matrix of Fig.

10, the image patterns displayed illustrates a game wherein the brick wall made up of segments 267 is chipped away at by a bouncing ball, segment 269, which is controlled by coincidence with a moving paddle segment 275. Besides being able to provide a large LCD matrix display, it is desirable to provide the greatest contrast possible. This is accomplished by allocating more time to the moving ball, segment 269, than the other patterns.

A time frame having five time periods 283 is illustrated in Fig. 1 2. Rather than providing a single time period for each of the three elements of the image pattern on the LCD, the ball element, segment 269, is allocated a plurality of time periods T1, T3 and T3 of the time frame. The brick wall segments 267 and the paddle segment 275 are still only allocated a single time period within a time frame. In this manner, by addressing the ball segment 269 more frequently, its rapid movement across the LCD matrix is facilitated by faster turn "on" and "off" times for the segments that plot the path of movement of the ball.

Fig. 1 3 illustrates a series of time frames 287, wherein each time frame has three time periods T1, T2 and T3. However, movement of the ball, segment 269, and the paddle, segments 275, is indicated. In the first time frame designated by time periods T1, T2 and T3, the display is driven by the same time period allocation as shown in Fig. 11. In the second time frame T,1, T2' and T3', the segment 269, which is the ball segment, is moved from row 10, column 9, to row 11, column 10, shown as segment 271. The time period T,' designated as 291 in Fig. 13 is allocated to have a duration that may be two or three times greater than the time periods T21 or T3', which again produce the paddle image pattern 275 and the brick wall pattern 267.In the third time frame, T12, the ball moves to row 12, column 11, segment 273.

In the fourth time frame T,3, the ball is shown as remaining for that time frame in row 12, and column 11, but the paddle, segments 275, is moved to row 15, columns 10, 11 and 12, segment 277. This time period 295 is twice as long, or some other factor longer, than time periods T,3 and T23. In this manner, the microprocessor can allocate longer and shorter time periods for various time periods within a time frame, depending upon the movement occasioned by the moving patterns displayed on the LCD matrix.

The microprocessor directs the driver circuits of the present invention according to the instructions stored within its program memory. Referring first to Fig. 14, a display subroutine is illustrated in flow chart form for the game shown as an example in Figs. 10 through 1 3. It should be understood that the programmingtand subroutines stored within the memory capacity of the microprocessor of the system will change according to the parti cular game or training sequence that is to be displayed on the LCD matrix and executed by the system.

The routine of Fig. 14 receives the x and y coordinates of a ball from the game routine or lines 300 and 298, respectively. These coordinates cause an activation procedure for a 4:1 6 decode for the x position of the ball at 301, and the yposition of the ball at 299.

The x and y positions of the ball which are in a four-bit ASCII code, are then converted into 16-bit row and column patterns at stage 303, and supplied to the driver circuits at stage 305, aiong with the latch and clocking signals at stage 307. A decision is made at stage 309 whether this new position indicates that the ball has moved. If the answer is "no", then that is the end of the subroutine and a return to the game routine is indicated. If the answer is "yes", then a ball display timer is set at stage 311 which allocates the time period, such as time period T,', for example, in Fig. 13, to be longer than the other time periods in a time frame to accommodate the moving ball. Thereupon the ball move flag is reset at stage 313, and a 25 millisecond timer is set at stage 315 to allow the LCD display to catch up with the electronics.Upon time-out of this 25 milliseconds, return to the game routine is directed.

Referring now to Fig. 15, the game routine is illustrated in a simplified flow chart for the game illustrated in Fig. 10. The game routine is started by a serve instruction on line 316, which activates a y parameter for the ball at stage 317. An x direction andy direction for the ball is set at stage 319, whereupon a 25 millisecond timer is set at stage 321 to allow the LCD display to catch up with the electronics. Upon the time-out of 25 milliseconds a decision is made whether the paddle is to be moved at stage 323. If the answer is "no", then a decision as to whether the ball is to be moved at stage 333 is made.

If the answer to the paddle move question at 323 is "yes", then a paddle timer is set at stage 325. This allocates a larger time period for the paddle then the other elements of the display. The paddle control, which is manipulated by an operator, is read at stage 327.

The values thereof are stored at 329. After the paddle control is read, a ball move decision is made at stage 333. If the answer to the decision is "no", then display subroutine 331 is activated and the moved or unmoved paddle, in addition to the unmoved ball and unmoved brick wall, is displayed.

If the answer to the ball move decision at stage 333 is "yes", the ball timer 355 is set, which allocates certain time frames, such as T1' to accommodate the moving ball in the same manner that the paddle timer 325 accommodates a moving paddle.

A direction calculation at stage 353 is made, whereupon a ball direction change decision is made at 351. If the answer to the ball direction change question is "no", then a ball-hit-paddle decision is made at stage 347.

If the answer to a direction change for the ball is "yes", then a "bender-board" tone generator is activated at stage 349.

Subsequently, a ball-hit-paddle decision is made at stage 347. If the answer to the decision is no; that is, if the ball missed the paddle, a score display sequence is initiated at stage 345, and the program starts over at ball/serve. If the ball hit the paddle at stage 347 and the answer to the decision is "yes", then another decision is made whether the ball hit a brick at stage 343. If the answer is "no", then the display subroutine 331 is activated.

If the answer is "yes", however, and the ball hit a brick, a tone generator is activated at stage 341, the brick is removed from the display at stage 339. In addition, the score is calculated at stage 337 and a direction change to the ball is initiated at stage 335, whereupon a display subroutine 341 is initiated, and the sequence from the movepaddle stage 323 is again initiated.

What has been described is a game or a training apparatus that can utilize a large LCD screen for display of moving patterns and alphanumeric characters, which apparatus provides for the easy changeability and movement of the patterns displayed on the LCD screen, while at the same time the quality of the display is as good or better than much smaller displays of LCD matrixes using a multiplexed addressing scheme, thereby providing an inexpensive LCD display device without the prior art shortcomings of small matrix size, and cumbercome driven circuitry.

Claims (16)

1. In a game or training device having operator-manipulatable control means, apparatus for displaying a plurality of image patterns, comprising: a segmented matrix display means; means for generating signals for application to said matrix display to turn a desired segment "on" or "off", said means adapted for simultaneous application of a signal to more than one of said segments; central controller responsive to said operator-manipulatable control means for directing said signal generating means to turn specific segments of said matrix display "on" or "off''.

2. The apparatus of Claim 1 wherein said central controller comprises microprocessor means.

3. The apparatus of Claim 2 wherein said display means comprises a segmented matrix array of liquid crystals organized in rows and columns, and said microprocessor means is adapted to direct said signal generating means to generate signals for simultaneous application to a plurality of rows and columns, thereby to turn a plurality of segments in different rows and columns "on" or "off" simultaneously.

4. The apparatus of Claim 3 wherein said microprocessor means is adapted to direct said signal generating means to generate signals for application to various rows and columns for different predetermined time periods.

5. The apparatus of Claim 4 wherein said microprocessor is adapted to dynamically vary the length of said time periods.

6. The apparatus of Claim 5 wherein said microprocessor varies the length of said time periods to provide a longer time period for the rows and columns of the liquid crystal matrix that define a path of movement for an image pattern.

7. The apparatus of Claim 1 wherein said display means comprises a segmented matrix array of liquid crystals organized in m rows and n columns and said signal generating means includes means for storing m + n binary bits.

8. The apparatus of Claim 7 wherein said generating means further comprises an m+ n bit latch responsive to binary bits in same m + n bit storing means.

9. The apparatus of Claim 8 wherein said generating means further comprises a bank of M three terminal switches, each having two of its terminals connected respectively to an "on" voltage level and an "off" voltage level, and the third terminal to a particular row of said display matrix.

10. The apparatus of Claim 9 further comprising a bank of n three terminal switches, each switch having two of its terminals connected respectively to an "on" voltage level and an "off" voltage level, and the third terminal to a particular column of said display matrix.

11. The apparatus of Claim 7 wherein said m + n binary bit storing means comprises two m/2 bit length serial shift registers and two n/2 bit length serial shift registers.

1 2. The apparatus of Claim 7 wherein said m + n binary bit storing means comprises four m/4 bit latches and four n/4 bit latches.

1 3. In a hand-size housing having manual manipulatable control means and a segmented matrix array of liquid crystals organized in m segment rows and n segment columns, apparatus for causing the display of a plurality of image patterns on said liquid crystal matrix comprising: means for generating and applying "on" and "off" signals to the m rows and n columns of said liquid crystal matrix, said means adapted for simultaneous application of a signal to more than one of said segments; and microprocessor means for directing said signal generating means to apply the "on" and "off" signal generated to specific ones of said m rows and n columns of said liquid crystal matrix.

14. The apparatus of Claim 1 3 wherein said microprocessor means directs said signal generating means to apply the "on" and "off" signals to various of the m rows and n columns for predetermined time periods.

1 5. The apparatus of Claim 1 4 wherein said microprocessor dynamically varies the length of the time periods.

16. The apparatus of Claim 1 5 wherein said microprocessor varies the length of time periods yo provide a longer time period for the m rows and n columns of the liquid crystal matrix that define a path of movement for an image pattern.

1 7. A game or training device substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.