GB2035631A - Electronic speed rating calculator - Google Patents

Abstract

A calculator calculates a comparative speed rating for an entrant in a race such as a horserace so that the entrant's performance can be compared with the performance of other entrants. The speed rating is determined in accordance with a formula which is based on a linear relationship between speed and distance over a particular distance for a particular class of entrant and where the speed rating for an entrant other than the winner is determined over the actual distance covered by the non- winning entrant in the same time as the winner. The specific equation to determine the speed rating is as follows: <IMAGE> where f is the length of the race in furlongs, L is the number of lengths horse was behind the winner, and t is the time of the winner in seconds.

Description

Electronic speed rating calculator and method The present invention relates to apparatus and method for calculation and more particularly to apparatus and method for a speed rating for an entrant in a speed contest from predetermined constants and factors taken from previous race results. The present invention further relates to calculators for executing fixed arithmetic functions under the control of read-only storage programs.

In the prior art, there are many methods for calculating a speed rating for race entrants such as racehorses.

An animals ability to race is a function of his innate ability as modifier of his physical condition at the time of the race. That is, if an animal in peak condition can race over a given distance at a certain average speed that individual is now racing at this ultimate capacity and no further amount of training can improve his performance. The innate ability to race for the individuals of any species has a bell shaped curve, the same as all other physical and performance characteristics such as height or intelligence.

The individuals of a species tend towards a norm (the peak of the bell shaped curve) with exceptional individuals out at the tails on either end of the bell.

For many years horse racing enthusiasts have been seeking a method to evaluate a horses innate running capacity at various distances. This is difficult for several reasons: 1. Horses race at many different distances and there is great difficulty in relating performances at the different distances. For example, if you knew the racing ability of horse A at 1 mile and the racing ability of horse B at 1 1/2 miles, who would be the faster at 1 1/4 miles? 2. The past performances of all horses in a race are published in the Daily Racing Form, however only the time of the winner is given. The number of lengths that each other horse in a race was behind the winner at the finish is also given and the rule of thumb is to add one fifth of a second to the winning time for each length behind the winner.This rule of thumb is only accurate if the horses are running at the exact speed of one furlong (sixty lengths) per twelve seconds and is inaccurate for all other speeds.

3 3 The same horse will run at different speeds on different tracks. This difference is caused by the track structure and the track condition. There are long term variations (track structure) and short term variations (weather), amount of scraping etc.

A horses racing class is related to his position on the bell shaped performance curve. A horse of high class (out on the high side tail of the bell) will beat a horse of average class (at the peak of the bell) at any typical racing distance. Higher class horses tend to perform better than lower class horses at all racing distances.

The problem is how to rate a horses racing ability such that: 1. Horses of the same class average the same rating at all distances.

2. Horses of different class have different ratings on an acendant scale with performance.

3. Horses taken individually on the average have the same speed rating at all distances.

The present speed rating systems do not meet the criteria as stated above. In most systems such as the Daily Racing Form, one point is subtracted from 100 for each fifth of a second the horses performance was higher than the track record at this distance. This system does not meet the criteria stated above for the following reasons: 1. One fifth of a second at a distance is much less important than one fifth of a second at a sprint.

2. The track records at different distances could have been set by horses of different class. The track record is a function of the horse that set the record.

3. The rule of thumb that one-fifth second equals one length is not accurate.

In order to generate speed ratings that meet the three criteria set out above a basic concept with a simple equation is necessary.

Other systems are discussed in a book by Andrew entitled Picking Winners. One particular system employs matrix tables which plot time and distance with resultant lines, being various speed ratings. One then can presumably compare two different horses by determining each ones speed rating and then by comparing the speed ratings. This is inherently inexact, since there is no overall theory to determine the speed ratings, it is all done empirically. To compound this, there is another table for non-winning horses.

This also plots distance and time and is also empirical, however, when these empirical results are added to the previous results, the final comparison is even more obtuse because of the inherent inaccuracy of empirical systems.

Although there are many calculators for executing arithmetic functions, there was no calculator capable of executing an equation for calculating a speed rating based upon predetermined constants and factors taken from previous race results.

Therefore, it is a primary object of the present invention to calculate a speed rating for an entrant in a sporting event such as a racehorse by a method that employs a linear relationship between speed and distance for entrants of the same class, parallel linear relationships between entrants of different classes and a linear relationship between speed and distance for a particular entrant and where taking into consideration these linear relationships a specific equation is employed to determine the winner.The equation is as follows:

Where f is the length of the race in furlongs Where L is the number of length horse was behind the winner Where t is the time of the winner in seconds It is a further object of the present invention to calculate a speed rating for an entrant in a sporting event such as a horserace based upon comparative results of the entrant from a previous race and constant factors applicable to the classification of the entrant.

It is yet another object of the present invention to calculate a speed rating for an entrant in a sporting event by the following equation:

It is a further object of the present invention to calculate a speed rating for an entrant in a sporting event such as a horserace based upon distance and time inputs.

It is another object of the present invention to calculate a speed rating for an entrant in a sporting event such as horseraces based upon distance and time inputs by a calculator including means for entering data and control information, means for displaying the input data and the result, means for storing the data of the control information, means for computing a speed rating given the input data and program control, means for controlling the sequence of operations of the speed rating calculator.

It is a feature of the present invention that the method for calculating a speed rating according to the present invention provides an accurate speed rating which considers all pertinent factors.

It is another feature of the present invention that apparatus according to the present invention may be carried upon the person to sporting events so that speed ratings may be instantaneous and efficiently calculated before and after an event.

A still further feature of the invention is to allow any person without any knowledge of mathematics or racing characteristics of horses to quickly and easily compute, with the aid of a calculator, the speed rating of any horses in any race. The user merely inputs the distance of the race, the lengths behind the winner, and the winners times. From this data the computer automatically computes a speed rating. The speed rating as computed will automatically compensate for the exact variation of speed and distance that the rule of thumb (1/5 sec. = 1 length) did not, and will also use a discovered linear relationship between class and distance to correlate running times of different distances to class.

Accordingly, the method of the present invention includes the steps of classifying the entrant relative to other entrants in the same or similar sporting events. The speed rating of the entrant is calculated according to the mathematical formula shown above, which formula includes the pertinent factors for determining a speed rating for each entrant independent of variations such as track and classification of the entrant. Thus, by the method of the present invention, a speed rating is calculated which is general in its application, in that the same speed rating applies for the entrant regardless of the distance of the race to be run.

The apparatus of the present invention includes means for data entry such as a keyboard similar to keyboards commonly used by function arithmetic calculators, a random access memory for storing input data and other intermediate and output data, an arithmetic unit for calculating a speed rating given the input data, a display device for displaying selected data, and a read-only storage program control for controlling the sequence of steps to be executed in the calculation of a speed rating.

These and other objects, features, and advantages of the present invention together with the operation of the invention will be understood by reference to the following detailed description taken together with the following drawings.

Figure 1 is a graph showing the speed in lengths/second as a function of distance in furlongs showing the North American record speeds at distances 6 to 10 furlongs.

Figure 2 is a graph of speed in lengths/second versus distance in furlongs showing speed rating lines for ratings 0 to 100.

Figure 3 is a front isometric view of a hand-held calculator according to the present invention.

Figure 4 is a block diagram of the micro computer of this invention.

Figure 5 is a block diagram of the details of the arithmetric and memory sections of the microcomputer.

Figure 6 is a diagram of the display section of the microcomputer.

Figure 7 is a diagram of the program and address generator of the microcomputer.

Figure 8 is a block diagram of data entry 6, timing generator, and the program controller.

Figure 9 is a diagram of the decoder with off/on control.

Figure tO is a diagram of the decimal point logic circuit.

For many years horse racing enthusiasts have been seeking a method to evaluate a horses innate running capacity at various distances. This is difficult for several reasons: 1. Horses race at many different distances and there is great difficulty in relating performances at the different distances. For example, if you knew the racing ability of horses B at 1 1/2 miles and the racing ability of horse A at 1 mile, who would be the faster at 1 1/4 miles? 2. The past performances of all horses in a race are published in the Daily Racing Form, however, only the time of the winner is given. The number of lengths that each other horse in a race was behind the winner at the finish is also given and the rule of thumb is to add one fifth of a second to the winning time for each length behind the winner. This rule of thumb is inaccurate.

3. The same horse will run at different speeds on different tracks. This difference is caused by the track structure and the track condition. There are long term variations (track structure) and short term variations (weather) and etc.

A horses racing class is related to his position on the bell shaped peformance curve. A horse of high class (out on the high side tail of the bell) will beat a horse of average class - (at the peak of the bell) at any typical racing distance. Higher class horses tend to perform better than lower class horses at all racing distances.

The problem is how to rate a horses racing ability such that: 1. Horses of the same class average the same rating at all distances.

2. Horses of different classes have different ratings on an ascendant scale with performance.

3. Horses taken individually on the average have the same speed rating at all distances.

The present speed rating systems do not meet the criteria as stated above. In most systems such as the Daily Racing Form one point is subtracted from 100 for each fifth of a second the horses performance was higher than the track record at this distance. This system does not meet the criteria stated above for the following reasons: 1. One fifth of a second at a distance is much less important than one fifth of a second at a sprint.

2. The track records at different distances could have been set by horses of different classes. The track record is a function of the horse that set the record.

3. The rule of thumb of one fifth second equals one length is not accurate.

In all the present systems of speed ratings the focus is on the time of the race. If the average winning times of horses of the same class are plotted as a function of the distance of the race the resultant curve is non linear, however, if the average speed is plotted as a function of distance, the resultant curve is a straight line.

This relationship is shown in Figure 1 for North American Records at distances from 6 furlongs to 1 1/4 miles.

Extensive research on the speed - distance characteristics of all classes of race horsed from distance of 5 furlongs to 1 1/2 miles has confirmed that all classes of horses exhibit the same straight line (linear) relationship of average speed verses distance.

This basic discovery of the linear relationship of speed and distance for horses of the same class now allows for a system which fulfills the original requirements of the speed rating system. The slope of the line relating North American Records was found to be about exactly the same as the slope of the line relating horses of all different classes of horses. This slope is approximately (.07) length/second/furlong.

Figure 2 illustrates the generator of the speed rating system. The ordinate is the average speed over the distance. The abcissa is the distance in furlongs. The desire is to make a scale of 0-100 where the vast majority of all performances will all within the scale. The rating of 100 is chosen as follows: an optimum speed at 6 furlongs is 5.3 lengths per second (this is approximately the North American Record - See Figure 1) this is assigned a speed rating of 100, a minimum speed at 6 furlongs is approximately 4.5 furlongs per second and is assigned a speed rating of 0. The 100 speed rating line is then drawn for the ordinate 5.3 with a slope of (-.07). Each .08 length/sec. at six furlongs reduces the speed rating by 10 until a speed rating of 0 corresponding to a speed of 4.5 at 6 furlongs.Figure 2 then illustrates the family of speed rating lines so generated.

Let f = Distance of race in furlongs.

Let S = Average speed of runner in lengths/sec.

Let Sr = Speed rating Let Cr =The value where the r speed rating intercepts the vertical axis (speed in lengths/sec.) at zero distance (f = 0).

Lett = Race time of winner in seconds The equation forthe 100 speed rating line is: Sioo = 5.72 - (.07) f The equation for the 90 speed rating is: Ss0=5.64-(0.07)f The equation for the 80 speed rating is: S80=5.56-(.07)f S0 = 4.92 - (.07) f The problem now is to generate the speed rating as a continuous function of the average speed of the runner at the distance.

Therefore S = Cr-(.07)f Cr = 4.92 + Sr (.08) Substitute Cr in previous equation Therefore S = 4.92 + Sr (.08) - (.07) f Solve for Sr Sr = S+(.07)f-4.92 For Winner (.08) S = 60f t Therefore (1) Sr = 60f+(.07)f-4.92 t (.08) (1) Sr = 750f + 875f-61.5 Equation 1 then relates the speed rating as a function of time and distance.

This equation must be modified for non-winners because their winning time is not given in the Daily Racing Form. Many different methods of calculating the losing horses average speed over the distance are possible. One method is: Let L = lengths behind the winner at the time winner crosses the finish.

Let S2 = Average speed of the loser.

Therefore S2 = f(60)-L t

Equation 2 is then used for both winners and losers with L2=0 for winners.

Extensive research has proved that this equation generates a consistent family of speed ratings satisfying the original requirements.

Once the equation for calculating speed rating has been determined which is general enough to cover all variables involved in a sporting event such as a horserace, the method for executing the calculation becomes apparent and is as follows: 1. Determine an optimum average speed based upon superior performance for the distance.

2. Determine the minimum average speed which experience has shown to have 0 value for the particular kind of sporting event in question.

3. Determine intermediate values between the optimum and the minimum for speeds at various distances for races.

4. Then solve using the formula

The equation shown above may be executed by a special purpose digital computer or by a sequence of program steps executed on a general purpose digital computer.

Referring to Figure 3, an electronic speed rating calculator 10 may be packaged as a hand-held calculator having function keys 12, 13, 14 and 15 for identifying the data to be entered on data entry keys 16. The display 18 is included to provide visual display of input data and speed rating result.

Referring briefly to Figure 8, the block diagram 6 of the speed rating calculator includes data input means 38 which could be keyboard 12-16 shown in Figure 3. The data entry means is connected to arithmetic unit 1 which executes arithmetric functions in the calculator and to random access memory 2 for storage of entered data. Program control read-only storage 4 controls the sequence of arithmetic and logic functions performed by the calculator. Control and timing logic 8 interacts with all other inputs, data input means 6, arithmetic unit 1, random access memory 2, program control read-only storage 4 and display 3 to control execution of the speed rating calculation.

Referring now to Figure 5, the operation of a calculator according to the present invention for calculating a speed rating according to the present invention contains the following steps: a) Data entry of distance in furlongs, gap in lengths, and tin seconds.

b) Multiplying f by -60.

c) Adding L to -60f and storing the result.

d) Dividing the result by t and storing the new result.

e) Calculating.07f.

f) Adding .07f to the result previously calculated.

g) Adding a constant (4.92) to the calculation.

h) Dividing by 0.008.

i) Storing and displaying the result which is the speed rating.

Program control read-only storage 4 shown in Figure 7 contains a 28-step routine for calculating a speed rating given a distance in furlongs, a gap between the first place and a nth place finisher in lengths and time in seconds. The following is a listing of the program steps to execute the speed rating equation.

Program Dec. Function ref. to ram loc. Notes 00000 (0) Enter data SeeN1 & 2 00001 1 Clear 00000 00010 2 Clear 11000 & 11100 00011 3 Add00100to11000 & 1100 Sixtimes(6f) 00100 4 Shiftup11000 & 1100 (60f) 00101 5 Complement 11000 & 11100 (-60f) 00110 6 Add 01000 to 11000 & 11100 (-60f+L) 00111 7 Clear 00000 01000 8 Shift up 11000 & 11100 Prep. for Division 01001 9 Add 10000 to 11000 & 11100 Dividebyt 01010 10 Transfer 00000 to 01000 Place result in 'L' Loc.

01011 11 Clear 00000 011000 12 Clear 11000 & 11100 01101 13 Add 00100 to 11000 and 11100 SixTimes(6f) 01110 14 Add 00100 to 11000 to 11100 One Time (7f) 01111 15 ShiftDown11000 & 1100 (.7f) 10000 16 Shift Down 11000 & 11100 (.07f) 10001 17 Add 01000 to 11000 & 11100 'L' + .07f 10010 18 Complement11000 & 1100 -('L'+ .07f) 10011 19 Add01100to11000 & 1100 Add4.92 10100 20 Clear 00000 10101 21 Shift Up 11000 & 1100 Prep. for Division 10110 22 Shift Up11000 & 1100 Prep. for Division 10111 23 ShiftUp11000 & 1100 Prep. for Division 11000 24 Shift Up 11000 & 11100 Prep. for Division 11001 25 Add 10100 to 11000 & 11100 Divide by 8 Program Dec.Function ref. to ram loc. Notes 11010 26 Add (0101)to 00000 Add 5 11011 27 Shift Down 00000 (Round off) 11100 28 Stop 11101 29 11110 30 N1: Prog. for Entering Data Prog. Dec. Function 0000 0 Display (Stop) 0001 1 Enter 1 st Dig.

0010 2 Display (Stop) 0011 3 Enter 2nd Dig.

0100 4 Display (Stop) 0101 5 Enter3rdDig.

0110 6 Display (Stop) 0111 7 Enter 4th Dig.

1000 8 Display (Stop) N2: Prog.forTransferring Data Prog. Dec. Function 0 1 Standardize 1 2 Transfer As can be seen from the method steps outlined above, when the program control read-only storage initiates the routine to calculate a speed rating, the first step is a data entry. Data is entered in random access memory address 0. Random access memory 2 shown in Figure 6 is a 32-location memory wherein each location contains a 4-bit byte of binary coded decimal data. Four memory locations or 4 bytes of data comprise a memory word. The memory is organized in the following manner: Word Data stored 0 Temporary Storage and Display 4 fin furlongs 8 L in lengths 12 Constant 1--4.92 16 tin seconds 20 Constant 2-0.008 24 Operating Storage 28 Operating Storage Data is first entered in random access memory location 0.As the data is entered it is displayed on the display device. After the data has been entered in temporary storage 0 it is then transferred to the appropriate storage location determined by the particular data being entered such as f, L, or t.

After data has been entered and is properly stored in the appropriate locations, an add command is executed to execute a mu Itiply-by-6 operation on the contents of word 4 (f). Next, a shift operation occurs to multiply the 6f by 10 to obtain 60f. Next, a complement operation occurs to obtain the negative of 60f. The add operation is executed to add the contents of word 8 (L) to -60f previously calculated. Then the next quantity L-60f is dividied by t and the result is placed in word 8. 6f is again calculated and then added to fto achieve 7f. This factor is then divided by 10 and again by 10 to achieve 0.07f. An add operation adds 0.07f to word 8 which is the factor L-60f divided by t previously calculated. Next, the contents of word 12 (4.92) are added to the result obtained by prior operations and the total is divided by 0.008.The result is then stored in word 0 for display.

The basic equation is divided into separate function and the order of performing these functions is as follows: 1. Multiply 60 byf: 60f 2. Deduct Lfrom the multiplication result: (60f-L) 3. Divide the result by t: (60 f-L)/t 4. Multiplyfby.07: .07f 5. Add the result in (3) to the result of (4): (60f-L)/t + .07f 6. Deduct 4.92 from the result of (5): (60f-L)/t + .07f - 4.92 7. Obtain solution SR by dividing .008 into (6) (60f-L)/t + .07f - 4.92.

A specific computer to perform the aforementioned calculations is described hereinafter: The computer is supplied with t, L, f (enter data and load t f L locations) to prepare the operating memory sections by clearing.

ortransfering information. These additional steps must be taken preceeding each of the above basic functions. Also, the end result is to be rounded off to the nearest full decimal digit.

A basic program for operation of the calculator is as follows: Program control Program Dec. Function Ref. to Ram Loc. Notes 00000 (0) Enter Data SeeN1 & 2 00001 1 Clear 00000 00010 2 Clear11000 & 1100 00011 3 Add 00100 to 11000 8( 11100 Six Times (6f) 00100 4 ShiftUp11000 & 1100 (60f) 00101 5 Complement:11000 & 1100 (-60f) 00110 6 Add01000to11000 & 1100 (-60X+L) 00111 7 Clear 00000 01000 8 Shift Up 11000 & 11100 Prep. for Division 01001 9 Add10000to11000 & 1100 Dividebyt 01010 10 Transfer 00000 to 01000 Place result in 'L' Loc.

01011 11 Clear 00000 01100 12 Clear11000 & 1100 01101 13 Add 00100 to 11000 & 11100 Six Times (6f) 01110 14 Add 00100 to 11000 & 11100 One Time (7f) 01111 15 ShiftDown11000 & 1100 (.7f) 10000 16 ShiftDown11000 & 1100 (.07f) 5 10 15 20 25 30 35 40 45 50 55 60 65 Program Dec. Function ref. to ram loc.Notes 10001 17 Add01000to11000 & 1100 'L'+.07f 10010 18 Complement: 11000 & 1100 -('L'+.07f) 10011 19 Add01100to11000 & 1100 Add4.92 10100 20 Clear00000 10101 21 ShiftUp11000 & 1100 Prep. for Division 10110 22 Shift Up 11000 & 11100 Prep. for Division 10111 23 Shift Up 11000 & 1100 Prep. for Division 11000 24 Shift Up 11000 & 11100 Prep. for Division 110001 25 Add10100to11000 & 1100 Divideby8 11010 26 Add (0101)to 00000 Add 5 11011 27 Shift Down 00000 (Round Off) 11100 28 11101 29 11110 30 11111 31

Stop N1: Prog. for Entering Data N2: Prog. for Transferring Data Prog. Dec. Function Prog. Dec.Function 0000 0 Display (Stop) 0001 1 Enter 1 st Dig. 0 1 Standardize 0010 2 Display (Stop) 1 2 Transfer 0011 3 Enter 2nd Dig.

0100 4 Display (Stop) 0101 5 Enter3rdDig.

0110 6 Display (Stop) 0111 7 Enter 4th Dig.

1000 8(0) Display (Stop) The tasks commonly referred to as subroutine functions, are given in terms of memory RAM (random access memory) locations below which are sections of selected memory that are being operated on: MemoryAddress A4 A3 A2 A1 Ao 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 Temporary Storage 0 0 0 1 1 and Display 0 0 1 0 0 0 0 1 0 1 f 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 L 0 1 0 1 0 0 1 0 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 4.92 (in ROM form) 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1- t 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0.008 (in ROM form) 1 0 1 1 -0 1 0 1 1 1 Memory' Address 1 1 0 0 0 1 1 0 0 1 Operating Section 1 1 0 1 0 (Add, Compliment, Subtract, etc.) 1 1 0 1 1 1 1 1 0 0 11101 1 1 1 1 0 1 1 1 1 1 NOTE:Each Memory Address Location Contains Four (4) Bits of BCD Storage Information.

The total memory capacity is divided into eight (8) sections. Each section consists of four (4) locations.

Since each location has the capacity of four (4) binary bits, then the capacity of each section is 4 x 4 = 16 binary bits. Due to the fact that four BCD (binary coded decimal) bits represent one decimal digit, the four BCD bits, as stored in each memory location, are operated on in parallel. For this reason the memory with the total capacity of 128 binary bits was organized as 32 words x 4 bits.

Each section of the memory consists of four locations as mentioned and the sections may be defined in terms of memory address. For example; Temporary Storage and Display uses first four locations with memory address A4 A3 A2 A Ao being from 00000 consecutively through 00011, variable fsection is in address locations 00100 to 00111, L in 01000 to 01011, and tin 10000 to 10011. Fixed number 4.92 is stored as 04.92 in 01100 to 01111 locations, while the number 0.008 is stored as 0800 in 10100 to 10111 address locations. The fixed numbers are not expected to change and therefore they may be permanently stored in an ROM (read only memory) form. The last two sections of the memory, address 11000 to 11011 and 11100 to 11111 are assigned for operation and they are combined into one Operating Section.The two memory sections are needed for the case of multiplication or division, where double precision is required.

For the simplicity of notation, the program uses only the first starting location in defining the memory section. For example, the Temporary Storage is referred to as 00000, meaning a memory section with starting location of this address but four "words" long, or four consecutive locations from 00000 through 00011. The Operating Section referred to as 11000 & 11100 includes two memory sections: first section with starting location 11000 and second section with starting location 11100.

The program sequence is as follows: The initial program, defined by a binary number 00000 (0) Enter Data, consists of entering information into the memory. According to notes N1 and N2, two separate sub-programs are used to load the memory locations. These sub-programs shall be described with the description of data entry operation. Basically, the numbers are first entered and stored in the Temporary Storage section (which is being simultaneously displayed) and then the numbers are transferred to the prescribed section according to L, T or F designation.

Program 00001(1) Clear 00000: Clearing of Temporary Storage location 00000 is necessary because this section is used in multiplication.

Program 00010 (2) Clear 11000 & 11100: Clearing of Operating section is required because the two memory sections are used for multiplication.

Program 00011 (3) Add 00100 to 11000 & 11100: The multiplication is performed here by repeated addition of six times of variable f that was stored in memory location starting address 00100. Also the number of times added is first stored in Temporary Storage 00000 and then compared to six. Upon reaching comparison the program is advanced to the next operation.

Program 00100 (4) Shift-Up 11000 & 11100: The number in Operating Section is shifted up by one decimal position to effect the multiplication by a factor of 10 in this fixed point arithmetic operation.

Program 00101 (5) Complement 11000 & 11100: This is a preparatory step that is required in order to effect the subtraction in subsequent program.

Program 00110 (6) Add 01000 to 11000 & 11100: The subtraction is obtained by adding a complement (10's complement is used) and leaving the result in a complement form as a preparatory step for division in subsequent program 01001.

Program 00111(7) Clear 00000: Preparatory step for division.

Program 01000 (8) Shift-Up 11000 & 11100: Preparatory step for division. The number is shifted up by one decimal point so as to obtain a result of the division to an accuracy of two decimal places.

Program 01001 (9) Add 10000 to 11000 & 11100: Division is performed here by repeated subtraction. The subtraction is obtained by adding complement and variable t stored in memory section 10000. This program also calls for recording the number of repeated subtractions that were performed until an overflow was reached. The record is kept in section 00000.

Program 01010 (10) Transfer 00000 to 01000: The result of division recorded in section 00000 is being transferred to memory section 01000. This is a preparatory step because section 00000 is required in subsequent multiplication.

Program 01011(11) Same as 00001.

Program 01100 (12) Same as 00010.

Program 01101(13) Same as 00011.

Program01110(14)Add00100to11000 & 1100: Single addition of tto the number that was already multiplied six times in program 01101. This in effect accomplishes total multiplication by 7.

Program 01111(15) Shift-Down 11000 & 11100: Total number is shifted down to effect moving decimal point up one decimal position.

Program 10000 (16) Same as 01111.

Program 10001(17) Same as 00110 except that the result of division in step 01001 that was transferred there in step 01010 is now being added to the result of the Program 10000.

Program 10010 Same as 00101.

Program 10011 (19)Add01100to11000 & 1100: The subtraction is effected by adding 4.92 to the complement and leaving the result in complement form as a preparatory step for subsequent division.

Program 10100(20) Same as 00111.

Program 10101 (21) Shift-Up 11000 & 11100: This is a preparatory step for division effecting decimal point location.

Program 10110 (22) Same as 10101.

Program 10111 (23) Same as 10101.

Program 11000 (24) Same as 10101.

Program 11001 (25) Add 10100 to 11000 & 11100. Division is obtained here in similar fashion to the program 01001 with number 8 being used here instead of variable t. The result of the division is recorded in section 00000. The result is in the form xxx.x, with decimal point one position over from the right.

Program 11010 (26) Add (0101) to 00000. Preparatory step for rounding off the end result to the nearest full decimal digit. By adding 0101 (5) to the last digit of the form xxx.x the full decimal digit in front of the decimal point is increased by one if the number in the last position is 5 or greater and is not altered if that number is smaller.

Program 11011(27) Shift-Down 00000: Round off of display by shifting down the whole number in 00000 and discarding all digits below decimal point. The end result is in the form xxx.

Program 11100 through 11111(28 to 31) Stop: The operation is stopped and the result displayed.

The description of the 28 steps involved in the total operation was limited to explanation of what is being done to achieve the end result. The programmed operations are performed by a computer in a form of 28 consecutive subroutines. In order to understand how the computer performs these subroutines, it is necessary to study the machine that was designed for this purpose.

Figure 5 shows basic micro-computer organization chart. As shown, the computer consists of eight building blocks: 1 - Arithmetic Section, 2 - Memory, 3- Display Section, 4- Programs (stored subroutines), 5- Ar Ao Address Generator, Data Entry Circuit, 7 - Timing Generator, and 8 - Program Controller.

The Arithmetic Section 1, coupled with the Memory 2, performs all basic operations, the subroutines of addition, multiplication, division, complementing, shift-up, shift-down, transfer, count, etc. The Display Section 3 displays all information appearing on communication buss at given time with multiplexing accomplished by A1 Ao address being cycled.

Programs (subroutines) 4 provides not only information of what function is to be performed but generates all address information, buss bias for certain conditions and necessary controls. It also establishes the sequence for A, Ao Address Generator 5 which is used to produce proper sequence as required by subroutines.

Data Entry Circuits 6 are used to load the memory with initial information. These circuits translate decimal digits to BCD (binary coded decimal) numbers and store them in the assigned memory locations as designated by L, t orf. This includes an instruction for decimal point location as well as a clear entry instruction and the start of operation instruction SR.

All timing information: basic clock, cycle clock, T1 and T2 periods as well as A1Ao initial address cycling are generated by the Timing Generator 7.

Program Controller 8 makes basic decisions when a given subroutine is finished and provides an advance pulse for next subroutine until the stop subroutine is reached, at which time the display subroutine is used to display the final result.

PRINCIPLE OF OPERATION Arithmetic section elements: As mentioned previously all operations are performed by the Arithmetic Section 1 with Memory 2 being used as storage. As shown in Figure 5, the output from the Arithmetic Section is fed directly to the memory and conventional use of an accumulator (consisting usually of parallel-in, parallel-out shift registers) was eliminated.

The operation is explained by the detail block diagram shown in Figure 6. The diagram shows the connection between the output of the Memory by a way of a communications bus to the input of the Arithmetic Section. Then, the output of the Arithmetic Section, consisting of four wires, is connected to the input of the Memory. In addition, there are shown a series of addresses and controls with information being provided by other sections.

Referring to arithmetic section alone, in Figure Sit is observed that it consists of seven separate smaller blocks: three 4-bit full adders numbered 9, 11 and 12; one preaccumulator block 10; one inverter 13; one invert/non-invert gate block 14 and carry storage flip-flop 15 with an AND function at its D (data) input.

The four bit full adder circuits are presently commercial items and as a reference the SN74283, a TTL (transistor-transistor-logic) type, is a good example. Complete specification for these elements may be found in a book entitled: "The TTL Data Book for Design Engineers" 1973, Texas Instruments Incorporated, P.O.

Box 5012, Dallas, Texas, as wIl as in "Supplement to The TTL Data Book for Design Engineers" 1974 by the same publisher.

The full adder mentioned above performs additions of two four bit binary numbers giving a resultant sum in a form of four binary bits and also a carry (CouT). It also has a provision for carry-in (cho) which may be a carryover from previous lower order additions.

The preaccumulator circuit 10 is also a commercial item, type SN7495, with complete detail specification to be found in books referred to above. Basically, it consists of four parallel-in, parallel-out shift registers with data being clocked-in by a negative edge trigger type signal. This element is used here as temporary storage.

The inverter, circuit 13, commercial type designation SN7404, basically inverts the input signal from one level to its opposite level.

Invert/non-invert gates, circuit 14, are commercially available type SN74H87, inverts the data signal if its control input isO' (low) and sends through non-inverted signal when its control input is '1' (high).

The flip-flop, circuit 15 has commercial number SN7474. It is referred to as a D-type flip-flop with information being stored in response to a positive going clock pulse. The circuit is being used here as temporary storage for carry for subsequent higher order additions. Due to the fact that this type has only one D D input an AND NAND gate type SN7408 is used. Also, the trigger input as supplied by T2 time interval is inverted by inverter type SN7404.

Referring to memory 2, there is a need for 128 bits of storage capacity. Commercial type SN7489 has a capacity of 64 bits therefore two such elements must be used. Blocks numbered 17 and 18 represent the equivalent combination of the two SN7489's. The output control gates, block 19, were added by using a type SN7403, which is a quadruple 2-input NAND gate with open collector output. The desired function is obtained by wiring one input of all four gates to RE (read enable) control input. The output devices are biased off by applying a "0" (low) and they are biased according to memory outputs: 20, 21, 22, 23, by applying a "1" (high) at RE input. Data input to memory is clocked in by WE (write enable) control input applied to the gates, 16, as provided by SN7489.The information is clocked into the memory with negative type pulse, hence the designation WE.

It should be pointed out that commercial items referred to above serve as examples and do not limit the micro-computer to their use. In fact, any other type of components having similar logical function may be employed.

Arithmetic operations Since the BCD number has only ten combinations out of possible sixteen total, it is necessary to translate or correct the resultant sum of addition of two such numbers. The final result must be in a proper BCD form.

For this reason, following procedure for additions was adopted.: 1. Add binary 6 to BCD number using 4-bit full adder circuit 9.

2. Store the sum in preaccumulator, circuit 10 at the end of T1 time interval.

3. Add another BCD number, at Tlr by way of circuit 14, using another 4-bit full adder, circuit 11.

4. Correct the resultant sum by the following rule: A. If the carry out (CouT) is "O" (zero), then the "sum" has an excess of binary six which is to be deducted by using still another 4-bit full adder, circuit 12. The procedure for deduction is as follows: using an inverter, invert "0" to "1" and wire in as a complement of 6 (16th complement) to the appropriate inputs of circuit 12 and add to the existing "SUM".

B. If the carry out (CouT) is "1" (one), then the "sum" is in proper BCD form and no correction is required.

Therefore, using inverter add "0" to the "sum" by using the same circuit 12.

The correct sum is clocked into the memory at the end of time period T2. Also, the carry out is stored in 0 flip-flop circuit 15 at the end ofT2. The carry will be used for the next higher order additions.

It should be noted that the invert/non-invert gates pass on a normal non-inverted signal for the case of addition as well as for most subroutines, except for subtraction when a complement is required in which case invert-non-invert gates are used in the process of inverting BCD number in generating a complement.

Basically, the subtraction is obtained by adding a complement of a given BCD number.

From the description above, it is observed that the arithmetic section is tailored for additions only. The sub-routines requiring other functions must rely on buss bias generation by Section 4 at appropriate times. It is also observed that there are two time intervals involved: T1 and T2. The overall procedure requires two steps: 1. At T1 the information is passed on to arithmetic section preaccumulator, circuit 10.

2. At T2 the information is passed through the rest of section 1 to the inputs of memory and is stored there.

This procedure is followed no matter what type of subroutine is performed.

Example of addition: In order to understand better the process involved in additions, it may be advisable to follow a simple example: Assume that there are two numbers to be added: 3 (decimal) and 4 (decimal). In BCD form the numbers are: 3 = 0011 4 = 0100 Also assume that the number > 011 (3) is stored in memory location as designated by memory address: A4A3A2A1Ao = 00100 where: Ao = 0 A, = 0 A2 1 At = 0 A4 =0 And assume that the number 0100 (4) is stored in memory location: A4A3A2A1Ao = 11000.

The resultant sum is to be put back into the memory location A4A3A2A1Ao= 11000.

Time intervals T1 and T2 are generated by the timing generator 7.

1. AtT1timeinterval(T1=1,T2=0): The memory address as generated by 4 - Programs and 5 - Generator is: Ao = 0, A, = 0, A2 = 1, A3 = 0, A4=0.

Memory controls, also generated by 4-Programs, is WE = 1 (High, which prevents writing into the memory) and RE = 1 (High, which allows the memory to be read out).

The buss lines B3B2B1 B0 are to receive the information from the memory and therefore no bias is to be applied by 4-Programs.

It is observed that with given conditions, the information as it appears on buss lines from memory,0011 (3), is passed on into the circuit 9 of the arithmetic section. Here the binary 0110 (6) is added with the resultant sum: 3 = 0011 +6 = 0110 9 = 1001 This partial sum, 1001(9), is stored in preaccumulator, circuit 10, at the end of the time interval T1.

Note that Invert/Non-invert gates were not involved at T1 time and also there is no need to concern with carry control or COUT output at this time and therefore they may be marked x = don't care.

2. At T2 time invertal (T1 = 0,T2= 1): At this time the memory address as generated by 4 and 5 is: A4A3A2A1Ao = 11000.

Memory controls as generated by 4 are: WE = (Low, allowing to write), RE = 1.

Buss lines are left open to allow reading from memory.

The input to invert/non-invert gates 14 is also generated by 4-Programs and it must be high (1) in order to pass on the information unaltered to circuit 11 for additions. The carry storage control is also supplied by 4 and it is high (1) allowing the carry, if any, to appear at the D-input to flip-flop 15.

Hence, with given conditions, it is observed that for memory addressA4A3A2A,A0 = 11000 a binary number 0100 (4) appears on buss lines. The passage through circuits 9 and 10 is blocked due to =0. The number is allowed to pass through invert/non-invert gates unaltered to the inputs of circuit 11, where the addition takes place.

The two numbers, partial sum stored in circuit 10 and new input, passing through circuit 14 is added in circuit 11: 9- 1001 +4= +0100 13 = 1101 It is noted that in above addition, there is no carry and therefore the "sum" must be corrected by subtracting six in circuit 12.

Since COUT = O, inverter 13 gives output = 1. This "1" is applied to two places in circuit 12 to appear as a 16th complement of binary six which is binary ten: 13= 1101 +10 = +1010 23=10111 By using only the first 4 binary digits and discarding carry in circuit 12, the result is: 23r 10111 -16 = -10000 7= 0111 It is observed that 3+4=7, hence 0111(7) is correct result.

The seven segment display elements are commercial items. The four parts 23 through 26 may be individual, for example MAN-3M type, by Monsanto Display Products, 3400 HillviewAve., Palo Alto, California 94304 or the elements may be in one section as in the case of DL-34M, by Litronix, 19000 Homestead Road, California 95014.

It should be pointed out that the above parts are given by a way of example and do not limit the microcomputer to their use.

Display operation: Circuit 20 converts the BCD number appearing on buss lines into seven segments for display. In multiplexing scheme, commonly used, like segments are connected together and the multiplexing is done by cycling digit drives.

The digit drive information obtained from memory address A1Ao is decoded into four outputs by 1/4 decoder circuit 21. Only one output is low at a given time. Therefore only one decimal digit is displayed at a time. However, due to the fact that A1Ao are cycled rapidly, all four decimal digits appearto be displayed simultaneously to the "naked" eye.

The display on/off control coming from Data Entry Circuits, block 6, control the display on with input being "1" (High) or offwith this input being "0" (Low).

The decimal point information appears here from Data Entry Circuits also, and is being used primarily during the time of loading the memory. Final display of result is in a standard form with decimal point at extreme right or Do position.

Due to WE= 0, the resultant sum is stored or written into the memory at the end of time inverval T2. Also, at the end ofT2, the carry is clocked into flip-flop 15. However, since the carry was zero in this example, therefore "0" is clocked in.

The described addition operation may be represented in a table form shown below: Memory Memory Buss address controls bias Arithmetic controls Interval A4 A3 A2 A1 Ao WEP RE B3 B2 B1 Bo I/NI Carry COUT T1 T2 001001 1 ----x x x 1 0 110000 1 ----1 1 x 0 1 This is the notation that is being used in describing and performing subroutines.

DISPLAY SECTION Parts: Display section 3 is shown in detail in Figure 7. This section consists of three logical circuits: 20,21 and 22; and four display elements: 23, 24, 25 and 26.

The logical circuit 20 is commercial type SN74248 (Texas Instruments). The 1/4 decoder with on/off display control, circuit 21, is constructed using standard types: SN7440 and SN7404 as shown in Figure 10. The decimal point logic, circuit 22, is also made from standard elements SN7412 and SN7404 as shown in Figure 11.

The readout of the memory directly without the use of conventional shift registers as intermediaries saves the cost of the extra parts and also provides the flexibility of direct visual access to any part of the memory.

Also, the method of direct readout eliminates the necessity of transferring the information from memory to the readout and display section. Only memory address is selected for desired location to be displayed.

The The table below DISPLAY SUBROUTINE FOR 0000 RAM LOCATIONS shows actually the display of four decimal digits stored in memory locations 00000 through 00011 with 00000 being used here by a way of notation. It is observed that location 00000 is part of the group with the least significant digit being stored there.

Display Subroutine for 00000 Ram Section Memory Arithmetic Memory Address Controis Buss Bias Controls Intervals A4 A3 A2 A1 A0 WE RE B3 B2 B1 B0 VNI CARRY Cout T1 T2 0 0 0 0 0 1 1 - - - - 1 x x 1 0 0 0 0 1 1 1 1 - - - - 1 x x 0 1 0 0 0 1 0 1 1 - - - - 1 x x 1 0 0 0 0 1 0 1 1 - - - - 1 x x 0 1 0 0 0 0 1 1 1 - - - - 1 x x 1 0 0 0 0 0 1 1 1 - - - - 1 x x 0 1 0 0 0 0 0 1 1 - - - 1 x x 1 0 0 0 0 0 0 1 1 - - - - 1 x x 0 1 Note : 1. x = irrelevant (anyinput including transitions0.

2. - = nobias on buss lines exceptfor RAM output.

DISPLAY OPTIONS : Leading Zero Suppression for first and second positions.

Data Entry Subroutine for 00000 Ram Section 0 0 0 1 0 1 1 - - - - 1 x x 1 0 (N3) 0 0 0 1 1 0 x 0 0 0 0 1 x x 0 1 0 0 0 0 1 1 1 - - - - 1 x x 1 0 (N2) 0 0 0 1 0 0 x 0 0 0 0 1 x x 0 1 0 0 0 0 0 1 1 - - - - 1 x x 1 0 (N3) 0 0 0 0 1 0 x 0 0 0 0 1 x x 0 1 x x x x x 1 0 - - - - 1 x x 1 0 (Enter BCD) N3 : For the first digit the buss lines must have zero bias in order to clearthe Memory, B3B2B1B0 = 0000.

From the above, it is noted that except for time intervals coming from the timing generator the only change appears in the A1Ao address being cycled. WE memory control is kept at "1" (high) to prevent writing erroneously into the memory during the display cycle. The A1A0 address is being cycled by a way of sequence Address Generator, 5, with sequence provided by 4-Programs. The sequence of starting with A1 = 1 and Ao = 1, and cycling down to Ar = 0, Ao = 0 is for the purpose of deleting leading decimal zero s in the display.

Programs This section is shown in detail block form in Figure 7. It is observed that it consists of 10 logical circuit blocks, circuits 27 and 36.

Circuits 27, 28, 29, 30 are commercial type SN7450. These circuits are select switches and are used by T1 and T2 time intervals to select proper addresses and controls applicable to each period.

Circuit block 33 consists of ROM output override logical functions and they are obtained by wiring commerical types as shown in Figure 8. The types are standard TTL gates.

Circuit block 34 and 35 constitute a ROM (read only memory). These circuits, in order for the micro-computer design to be reduced to practice were wired using commerically available NAND (Not AND) TTL gates. Detail specification for these circuits, as was already mentioned previously, may be found in the referred books. The organization and logical functions generated by these gates, however, are equivalent to the diagram as shown in Figure 8.

Circuit block 36, a program counter, was constructed using five (5) commerical type TTL D Flip-Flops SN7474.

Here again, it is pointed out, the types mentioned are given by a way of example and they do not limit microcomputer to their use.

- - Programs Operations: Circuit blocks 34 and 35 form the base of detail instruction generating station. All adresses and controls are stored there in fixed form and are supplied to the outputs for a given subroutine program.

The program is selected by circuit 35 by decoding the outputs of a program counter, circuit 36, which has a minimum count of 00000 (0) and a maximum count of 11111(31) for a total capacity of 32 subroutine programs. Since only 28 programs were needed, the last four outputs from decoder were wired as STOP.

The given program, as decoder by 1/32 decoder, then determines all outputs of circuit block 34 applicable to this subroutine. These outputs may be either addresses or control signals. As it is shown in Figure 7, the outputs may be divided into eight (8) groups, which are marked as a, b, c, d, e, f, and g.

Group a generates memory RAM addresses A4A3A2 forT1 time interval and also A4A3A2 address forT2 interval for a total of six outputs. These addresses are later selected by circuit block 27 switches, that are controlled by T1 and T2, so as to obtain only three outputs applicable to respected intervals.

Group b generates control signals which in turn determine the sequence of A1Ao generation by address generator 5 since each subroutine has a prescribed order of A1 and Ao variation.

Group c generates memory controls: WE (write enable) and RE (read enable). These signals are also given for both T1 and T2 periods simultaneously and are later selected by switches in circuits 28 and 29.

Group d generates communications buss bias conditions for both T1 and T2 periods, a total of eight "ROM" outputs that are further selected into four outputs at give time interval by switches 30. These outputs may be in any one of the three states, so called "tri-state": low (0), high (1) or High z (floating).

Group e generates control levels for Invert/Non-lnvert gates in Arithmetic Section 1 as required by given subroutine program. This output is normally high (1) except for the case of complementing when it is low (0).

Group f generates carry storage control for Flip-Flop &num;15 in Arithmetic Section. This output control is referred to as "carry" for the simplicity of notation.

Group g generates the number of cycles that must be performed in a given subroutine. Minimum cycles is one and maximum is four. Four separate decoded outputs are generated simultaneously, however, only one output (depending upon the number of cycles) is high.

Group fgenerates only one output which may be 1 (high) for continuing operation or 0 (low) for stopping.

It is observed that there are some 31 outputs being generated by the ROM block. These outputs may be modified by Override circuits 33 as in the case of Data Entry sub-program or if a subroutine requires several cycles. Study showed that the approach of modifying ROM outputs to be more economical than expanding ROM capacity which otherwise would be required.

Address Generator Figure 7 also shows a detail block diagram for the address generator. It is noted that it consists of four basic logical circuits: 37, 38, 39 and 40. The circuit 37 is a commerical type SN7450, which is a "Dual 2 Input AND OR Invert" gates.

Circuit 38 is Invert/Non-Invert gate, commerical type SN74H87.

Circuit 39 is type SN7450, the same as 37 except that ROM control outputs do the selecting instead of T1 or T2 signals.

Circuit 40 is "2 Bit Full Adder", commercial type SN7482.

It is also noted that the inputs to circuit 38 also come from ROM.

Operation: (5) Each Individual Subroutine requires a certain sequence of A1Ao address. For example, a transfer operation uses A1Ao sequence as follows: A, Ao T1 T2 Case &num;1: 0 0 1 0 0 0 0 1 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 1 0 1 1 0 1

CYCLE This sequence as it appears is the same as generated by Timing Generator (7) and therefore the input to Invert/Non-lnvert circuit 38 is high (1) as generated by ROM in order to pass the signals unaltered. The input to circuit 39 is also high (1) as put out by ROM because the adder is not used.

The display subroutine requires a sequence that is as follows: As Ao T1 T2 Case &num;2: 1 1 1 0 1 1 0 1 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0 1 0 0 1 0 O 0 0 0 1 Here the address must be inverted as compared to case 1 above and therefore the input to Invert/Non-lnvert gates is low (0), but, the input to circuit 39 is still high (1).

The Shift-Down subroutine required A1Ao sequence as follows: An Ao T1 T2 Case &num;3: 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 The sequence as it appears has certain order that must be generated precisely by generator 5.For the purposes of analysis, given sequence may be shown separately for T1 interval and also separately for T2 with following respective order: Ar Ao T1 A Ao T2 0 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 It is observed that for T2 interval the address is normal, the same as in the case of transfer, however, for T1 interval the address appears to have an extra 1 in it: this 1 may be added to A1Ao sequence from Timing Generator 7. The addition may be performed by using 2-Bit Full Adder, circuit 40.

The input then from ROM is low (0) to L/R (left'right) switches, circuit 39, so that the output from circuit 40 may be passed through. Since there is no inversion, the input to I/NI circuit 38 is high (1) as it appears from ROM. The switches circuit 37 eventually select proper sequence for T1 as well as T2 time intervals.

The Shift-Up subroutine sequence is as follows: A1 Ao T1 T2 Case &num;4: 1 0 1 0 1 1 0 1 0 1 1 0 1 0 0 1 O 0 1 0 0 1 0 1 1 1 1 0 O 0 0 1 Comparing the sequence of case &num;4 to the one in case &num;3, it is noted that the sequence in case &num;4 is inverted in respect to case &num;3. For this reason, the input for I/NI gate must be low (0) to cause inversion and the input to L/R switches circuit 39 is the same as in case 3, low (0), to allow the use of output of adder, circuit 40.

The four cases of A1Ao address sequences mentioned were the only ones required for all subroutines.

With the present scheme only gating is required while in the conventional approach, with up-down counters and skip provision two flip-flops would be needed in addition to gating.

Timing Generator Detail block of this section is shown in Figure 9. It is noted that the timing generator consists of five logical circuits: 54, 55, 56, 57 and 58.

Circuit 54, the oscillator, is built out of inverters, commercial type SN7406. Circuit 55, as well as 56 and 57 are D-type Flip-Flops SN7474. Circuit 58 is an AND function built out of SN7420 (NAND) and inverter type SN7404.

The oscillator, consisting of three inverters in series and connected backfrom output to input generates basic clock for microcomputer. The use of this type of oscillator is well known, it is very reliable, because, being unstable, the oscillations will persist under all conditions of variations of voltage or temperature. The period of oscillation is being controlled by an external capacitor.

The oscillator drives first Flip-Flop, circuit 55, which is connected as counter-divider. This circuit generates in turn the two time intervals T1 and T2 which are of equal time duration. The outputs from circuit 55 must be buffered by inverter-buffer type SN7406 in order to drive all sections of the machine.

The output of circuit 55 is also applied as a clock to Flip-Flop 56 which is also connected as counter-divider.

This flip-flop is used to generate basic Ao address. Circuit 56 in turn drives Flip-flop 57 to obtain basic A address.

The three Flip-Flop circuits 55, 56 and 57 are AND'ed together with oscillator 54 to generate a cycle clock by circuit 58. This cycle clock is fed into the Program Controller and also the Data Entry Circuitry.

8-Program Controller Program Controller is a part of Figure 9, where all logical blocks of this section are shown in detail form. It is observed that the controller consists of four logical circuits numbered 59,60, 61 and 62.

Circuit 59, a cycle counter, uses two D-type Flip-Flops SN7474. Circuit 60 is a 1/4 (one out of four) decoder as shown in Figure 10 but without on/off control. Circuit 60 is a logical block shown in detail in Figure 12, using basic type SN7406 with wired "OR" functions to generate set and reset pulses for cycle counter. Circuit 62 is made of standard SN7400 series TTL gates.

The number of cycles that the subroutine requires are counted by circuit 59 and then decoded in circuit 60.

The control for the counter comes from ROM outputs which determine by circuit 61 when the counter is to be reset and new program to begin. The outputs from 60 circuit, the decoder, are used in program advance circuit 62 and also ROM output section to override the signals there for certain subroutines.

Advance program block 62 makes basic decisions when to advance the program. It receives inputs from ROM, cycle counter COUT from arithmetic section and timing generator, and it produces an advance pulse to program counter. This pulse is subject to conditions which may be expressed as follows: Advance program pulse=SR(ltf)+E1S1 +E2S2+E3S2A1AoCoUT+E4S4COUT Where: SR (ltf) is a term determining the start of the program, only after all variables f and L and t have been entered.

2. E,S1 is a term referring to one cycle operation, with E1 signal coming from ROM and S1 from cycle counter.

3. E2S2 is a term referring to two cycle operation, with E2 coming from ROM and S2 from cycle counter.

4. E3S2AlAoCouT is a term defining three cycle operation by E3 from ROM output and in second cycle S2 from cycle counter, with As and Ao being 1 (high) from timing generator, there is a carry COUT = 1 (high) from arithmetic section.

5. E4S4COUT is a term defining four cycles by E4 from ROM, being in fourth cycle S4 as determined by cycle counter, there is a carry COUT = 1.

Data Entry Circuits Figure 9 shows detail block diagram of Data Entry Circuits. The circuits are standard logical components with complete specification given in the referenced books. They are numbered in Figure 9 from 37 through 51, a total of fifteen.

Circuit 37 is a Decimal to BCD Encoder, SN74147 with negative NOR gate SN74s133. Circuit 38 is a set of switches a standard component of hand held calculator. Circuit 39 is a digit counter and it was constructed using three D-type Flip-Flop SN7474. Circuit 40 is 1/8 (one out of eight) decoder SN74S138. Circuit 41 is constructed out of SN7420 and SN7404 gates. Circuit 42 is made out of SN7403 NAND gates and circuit 35 is made out of SN7420 and SN7404. Circuit 44 is a decimal point counter using two SN7474's type. Circuits 45, 46 and 47, as well as 48, are RS Flip-Flops wired from SN7/s1/2??. Circuit 49 is a negative NOR SN7420 (positive NAND). Circuit block 50 is a combinational logic consisting of standard SN7400 series gates and one SN7474 Flip-Flop. Circuit 43 is an RS Flip-Flop wired from SN7410 gates.

Entering Data Date Entry Circuits employ a special sub-program, consisting of two parts: N1 = program for entering data into temporary storage section of memory and N2 = program for transferring data to designated memory sections.

Referring to page 18 note 1(N1), it is observed that sub-program for entering data consists of eight (8) steps. The sub-program is stored in the data entry section by digit counter, circuit 39, digit decoder 40 and enter/display logic circuit 41. This sub-program is given in terms of the three outputs of the digit counter.

Sub-programs 000,010, 100 and 110 are display subroutines according to the display subroutine table.

(Page 34) Sub-programs 001,011, 101 and 111 are data entree subroutines as given on Page 34. The subroutine consists of shift-up operation and entering BCD number during A, = 0, Ao = 0, (which is the least significant digit location). A note appears - N3. During the first digit entree, sub-program 001, the bus bias has a 0 (low) potential applied in order to clear all digits above the one being entered.

Physical realization of entering data consists of pressing appropriate decimal digit button: 0,1,2,3,4,5,6,7,8,9, which when encoded to BCD number is allowed to pass to the communications buss and by a way of arithmetic section is stored in the memory, 00000 temporary storage section. The subroutine for this operation is defined by the data entry subroutine table.

Decimal Point A special track is being kept of decimal point during data entry. Basically, the decimal point, with button pressed, is first stored in RS Flip-Flop, circuit 45, and then shifted together with digit entry to proper location as defined by decimal point counter circuit 44. The output of this counter is supplied to the Display Section for display purposes.

Memory Section Loading According to the program control, N2, a special two step sub-program is used to transfer the data from 00000 memory section to the predesignated section f, I or tin the memory.

The first step in this sub-program consists of putting the entering number in standard form: XX.XX for the case of for L and XXX.X for the case oft. Standardization consists of shifting up the number (Data Entry Table) until the decimal pqint appears in proper location.

The second step is performed according to transfer subroutines shown in Tables, Page 47, depending upon which button was pressed. This second step also resets the digit counter and decimal point counter as a preparatory step for future entries.

Record of the t f I loading is kept by the three RS Flip-Flops 46,47 and 48.

Clear Entry Operation Last data entry may be cleared by pressing CE (clear entry) button. The internal operations consists of using established procedures as fort f L with zero being entered in memory (no digit buttons were pressed) and resetting digit counter and decimal point counter at the same time to prepare for entering the first number.

Display Control The display is initiated by pressing any number or SR and is turned off by pressing f, t or L button. An RS Flip-flop is used for this purpose to record the last button pressed. The output from this Flip-Flop circuit 51 is supplied to the display.

SR: By pressing SR button, the operation may start if all three t f L variables were entered, at least once, each.

The last entry is recorded. If any one or more of the variables were not recorded and are missing the display shows this: 1111 = f is missing 2 2 2 2 = L is missing 3333 = t is missing This display is visible only when SR button is held depressed. In the case of all three f L and t missing: display shows 1111; for L and t missing: display shows 2222.

With all variables stored, pressing of the SR button will start the operation: Start= SR (ftL) The display flickers during the run and comes to fixed number display upon completion.

OVERALL MICROCOMPUTER OPERATIONS Subroutines: Program 00000: Data is entered using data entry subroutine shown in table form by Data Entry Subroutine combined with Transfer Subroutine for 00100 for f, Transfer Subroutine for 01000 to L, or transfer Subroutine for 10000 tot sections.

Transfer suborutine for 00100 Memory addres Memory Buss bias Arithmetic controls Intervals controls A4 A3 A2 A1 A0 WE RE B3 B2 B1 B0 I/NI Cary Cour T1 T2 0 0 0 0 0 1 1 - - - - 1 x x 1 0 0 0 1 0 0 0 x 0 0 0 0 1 x x 0 1 0 0 0 0 1 1 1 - - - - 1 x x 1 0 0 0 1 0 1 0 x 0 0 0 0 1 x x 0 1 0 0 0 1 0 1 1 - - - - 1 x x 1 0 0 0 1 1 0 0 x 0 0 0 0 1 x x 0 1 0 0 0 1 1 1 1 - - - - 1 x x 1 0 0 0 1 1 1 0 x 0 0 0 0 1 x x 0 1 Transfer subroutine for 01000 0 0 0 0 0 1 1 - - - - 1 x x 1 0 0 1 0 0 0 0 x 0 0 0 0 1 x x 0 1 0 0 0 0 1 1 1 - - - - 1 x x 1 0 0 1 0 0 1 0 x 0 0 0 0 1 x x 0 1 0 0 0 1 0 1 1 - - - - 1 x x 1 0 0 1 0 1 0 0 x 0 0 0 0 1 x x 0 1 0 0 0 1 1 1 1 - - - - 1 x x 1 0 0 1 0 1 1 0 x 0 0 0 0 1 x x 0 1 Transfer subroutine for 10000 0 0 0 0 0 1 1 - - - - 1 x x 1 1 1 0 0 0 0 0 x 0 0 0 0 1 x x 0 0 0 0 0 0 1 1 1 - - - - 1 x x 1 1 1 0 0 0 1 0 x 0 0 0 0 1 x x 0 0 0 0 0 1 0 1 1 - - - - 1 x x 1 1 1 0 0 1 0 0 x 0 0 0 0 1 x x 0 0 0 0 0 1 1 1 1 - - - - 1 x x 1 1 1 0 0 1 1 0 x 0 0 0 0 1 x x 0 0 Program 00001 : Clear Subroutine, for 10000, one cycle operation.

Clear subroutine for 00000 Memory addres Memory Buss bias Arithmetic controls Intervals controls A4 A4 A2 A1 A0 WE RE B3 B2 B1 B0 I/NI Carry Cour T1 T2 0 0 0 0 0 x x 0 0 0 0 1 x x 1 0 0 0 0 0 0 0 x 0 0 0 0 1 x x 0 1 0 0 0 0 1 x x 0 0 0 0 1 x x 1 0 0 0 0 0 1 0 x 0 0 0 0 1 x x 0 1 0 0 0 1 0 x x 0 0 0 0 1 x x 1 0 0 0 0 1 0 0 x 0 0 0 0 1 x x 0 1 0 0 0 1 1 x x 0 0 0 0 1 x x 1 0 0 0 0 1 1 0 x 0 0 0 0 1 x x 0 1 Program 00010 : Clear subroutine, two cycle operation.

Clear subroutine for 11000 & 11100 1 1 0 0 0 x x 0 0 0 0 1 x x 1 0 1 1 0 0 0 0 x 0 0 0 0 1 x x 0 1 1 1 0 0 1 x x 0 0 0 0 1 x x 1 0 1 1 0 0 1 0 x 0 0 0 0 1 x x 0 1 1 1 0 1 0 x x 0 0 0 0 1 x x 1 0 1 1 0 1 0 0 x 0 0 0 0 1 x x 0 1 1 1 0 1 1 x x 0 0 0 0 1 x x 1 0 1 1 0 1 1 0 x 0 0 0 0 1 x x 0 1 1 1 1 0 0 x x 0 0 0 0 1 x x 1 0 1 1 1 0 0 0 x 0 0 0 0 1 x x 0 1 1 1 1 0 1 x x 0 0 0 0 1 x x 1 0 1 1 1 0 1 0 x 0 0 0 0 1 x x 0 1 1 1 1 1 0 x x 0 0 0 0 1 x x 1 0 1 1 1 1 0 0 x 0 0 0 0 1 x x 0 1 1 1 1 1 1 x x 0 0 0 0 1 x x 1 0 1 1 1 1 1 0 x 0 0 0 0 1 x x 0 1 Program 00011: Multiplication subroutine as shown below. This subroutine consists of four cycles, repetitive. The repetition is conditional. When a carry-out COUT=1 is obtained during the fourth cycle, then the multiplication is completed and the program is advanced to next subroutine.

Multiplication subroutine for 00100, 11000 & 11100 Memory Memory address controls Buss bias Arithmetic Controls Intervals A4 A3 A2 A1 A0 WE RE B3 B2 B1 B0 1/NI Carry Cour T1 T2 0 0 1 0 0 1 1 - - - - 1 x x 1 0 1 1 0 0 0 0 1 - - - - 1 1 x 0 1 0 0 1 0 1 1 1 - - - - 1 x x 1 0 1 1 0 0 1 0 1 - - - - 1 1 x 0 1 0 0 1 1 0 1 1 - - - - 1 x x 1 0 1 1 0 1 0 0 1 - - - - 1 1 x 0 1 0 0 1 1 1 1 1 - - - - 1 x x 1 0 1 1 0 1 1 0 1 - - - - 1 1 x 0 1 1 1 1 0 0 1 1 - - - - 1 x x 1 0 1 1 1 0 0 0 x 0 0 0 0 1 1 x 0 1 1 1 1 0 1 1 1 - - - - 1 x x 1 0 1 1 1 0 1 0 x 0 0 0 0 1 1 x 0 1 1 1 1 1 0 1 1 - - - - 1 x x 1 0 1 1 1 1 0 0 x 0 0 0 0 1 1 x 0 1 1 1 1 1 1 1 1 - - - - 1 x x 1 0 1 1 1 1 1 0 x 0 0 0 0 1 1 x 0 1 0 0 0 0 0 1 1 - - - - 1 x x 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 x 0 1 0 0 0 0 1 1 1 - - - - 1 x x 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 x 0 1 0 0 0 1 0 1 1 - - - - 1 x x 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 x 0 1 0 0 0 1 1 1 1 - - - - 1 x x 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 x 0 1 0 0 0 1 1 1 x x x x x 1 x x 1 0 0 0 0 1 1 1 x x x x x 1 x x 0 1 0 0 0 1 0 1 x x x x x 1 x x 1 0 0 0 0 1 0 1 x x x x x 1 x x 0 1 0 0 0 0 1 1 x x x x x 1 x x 1 0 0 0 0 0 1 1 1 0 x 0 0 1 x x 0 1 0 0 0 0 0 1 1 - - - - 1 x x 1 0 0 0 0 0 0 1 0 0 1 1 0 1 0 (1) 0 1 Program 00100 : Shift-up by two cycles.

shift-up subroutine for 11000 & 11100 Memory Memory address controls Buss bias Arithmetic Controls Intervals A4 A3 A2 A1 A0 WE RE B3 B2 B1 B0 1/NI Carry Cour T1 T2 1 1 1 1 0 1 1 - - - - 1 x x 1 0 1 1 1 1 1 0 1 0 0 0 0 1 x x 0 1 1 1 1 0 1 1 1 - - - - 1 x x 1 0 1 1 1 1 0 0 1 0 0 0 0 1 x x 0 1 1 1 1 0 0 1 1 - - - - 1 x x 1 0 1 1 1 0 1 0 1 0 0 0 0 1 x x 0 1 1 1 0 1 1 1 1 - - - - 1 x x 1 0 1 1 1 0 0 0 1 0 0 0 0 1 x x 0 1 1 1 0 1 0 1 1 - - - - 1 x x 1 0 1 1 0 1 1 0 1 0 0 0 0 1 x x 0 1 1 1 0 0 1 1 1 - - - - 1 x x 1 0 1 1 0 1 0 0 1 0 0 0 0 1 x x 0 1 1 1 0 0 0 1 1 - - - - 1 x x 1 0 1 1 0 0 1 0 1 0 0 0 0 1 x x 0 1 1 1 x 1 1 1 1 - - - - 1 x x 1 0 1 1 0 0 0 0 1 0 0 0 0 1 x x 0 1 Program 00101 :Complementing subroutine, two cycle opertion Complementing subroutine for 11000 & 11100 Memory Memory address controls Buss bias Arithmetic Controls A4 A3 A2 A1 A0 WE RE B3 B2 B1 B0 1/NI Carry Cour T1 T2 1 1 0 0 0 1 0 0 1 0 0 x 0 x 1 0 1 1 0 0 0 0 1 - - - - 0 0 x 0 1 1 1 0 0 1 1 0 0 1 0 0 x 0 x 1 0 1 1 0 0 1 0 1 - - - - 0 0 x 0 1 1 1 0 1 0 1 0 0 1 0 0 x 0 x 1 0 1 1 0 1 0 0 1 - - - - 0 0 x 0 1 1 1 0 1 1 1 0 0 1 0 0 x 0 x 1 0 1 1 0 1 1 0 1 - - - - 0 0 x 0 1 1 1 1 0 0 1 0 0 1 0 0 x 0 x 1 0 1 1 1 0 0 0 1 - - - - 0 0 x 0 1 1 1 1 0 1 1 0 0 1 0 0 x 0 x 1 0 1 1 1 0 1 0 1 - - - - 0 0 x 0 1 1 1 1 1 0 1 0 0 1 0 0 x 0 x 1 0 1 1 1 1 0 0 1 - - - - 0 0 x 0 1 1 1 1 1 1 1 0 0 1 0 0 x 0 x 1 0 1 1 1 1 1 0 1 - - - - 0 1 x 0 1 Program 00110:Add by using Multiplication Subroutine but limit to singletwo-cycle operation, first two cycles, A4A3A2 (T1) = 010.

Program 00111: Same as 0001.

Program 01000: Same as 00100.

Program 01001: Divide as below. This is a three cycle operation, but repetitive until an overflow carryout.

COUT = 1, is detected during the end of second cycle at which time the program is stepped up to next subroutine.

Division subroutine for 10000 and 11000 & 11100 Memory Memory address controls Buss bias Arithmetic Controls A4 A3 A2 A1 A0 WE RE B3 B2 B1 B0 1/NI Carry Cour T1 T2 1 0 0 0 0 1 1 - - - - 1 x x 1 0 1 1 0 0 0 0 1 - - - - 1 1 x 0 1 1 0 0 0 1 1 1 - - - - 1 x x 1 0 1 1 0 0 1 0 1 - - - - 1 1 x 0 1 1 0 0 1 0 1 1 - - - - 1 x x 1 0 1 1 0 1 0 0 1 - - - - 1 1 x 0 1 1 0 0 1 1 1 1 - - - - 1 x x 1 0 1 1 0 1 1 0 1 - - - - 1 1 x 0 1 1 1 1 0 0 1 1 - - - - 1 x x 1 0 1 1 1 0 0 0 x 0 0 0 0 1 1 x 0 1 1 1 1 0 1 1 1 - - - - 1 x x 1 0 1 1 1 0 1 0 x 0 0 0 0 1 1 x 0 1 1 1 1 1 0 1 1 - - - - 1 x x 1 0 1 1 1 1 0 0 x 0 0 0 0 1 1 x 0 1 1 1 1 1 1 1 1 - - - - 1 x x 1 0 1 1 1 1 1 0 x 0 0 0 0 1 1 (1) 0 1 0 0 0 1 1 1 1 - - - - 1 x x 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1 x 0 1 0 0 0 1 0 1 1 - - - - 1 x x 1 0 0 0 0 1 0 0 x 0 0 0 0 1 1 x 0 1 0 0 0 0 1 1 1 - - - - 1 x x 1 0 0 0 0 0 1 0 x 0 0 0 0 1 1 x 0 1 0 0 0 0 0 1 1 - - - - 1 x x 1 0 0 0 0 0 0 0 x 0 0 0 0 1 1 x 0 1 Program 01010: Transfer according to Transfer Subroutine for 00100, one cycle operation.

Program 01011: Same as 00001.

Program 01100: Same as 00010.

Program 01101: Same as 00011.

Program 01110: Same as 00110, limit to first two cycles.

Program 01111: Shift-Down as shown below, two cycles.

Shift-down subroutine for 11000 & 11100 Memory Memory address controls Buss bias Arithmetic Controls A4 A3 A2 A1 A0 WE RE B3 B2 B1 B0 1/NI Carry Cour T1 T2 1 1 0 0 1 1 1 - - - - 1 x x 1 0 1 1 0 0 0 0 1 0 0 0 0 1 x x 0 1 1 1 0 1 0 1 1 - - - - 1 x x 1 0 1 1 0 0 1 0 1 0 0 0 0 1 x x 0 1 1 1 0 1 1 1 1 - - - - 1 x x 1 0 1 1 0 1 0 0 1 0 0 0 0 1 x x 0 1 1 1 1 0 0 1 1 - - - - 1 x x 1 0 1 1 0 1 1 0 1 0 0 0 0 1 x x 0 1 1 1 1 0 1 1 1 - - - - 1 x x 1 0 1 1 1 0 0 0 1 0 0 0 0 1 x x 0 1 1 1 1 1 0 1 1 - - - - 1 x x 1 0 1 1 1 0 1 0 1 0 0 0 0 1 x x 0 1 1 1 1 1 1 1 1 - - - - 1 x x 1 0 1 1 1 1 0 0 1 0 0 0 0 1 x x 0 1 1 1 x 0 0 1 1 0 0 0 0 1 x x 1 0 1 1 1 1 1 0 1 0 0 0 0 1 x x 0 1 Program 10000: Same as 01111.

Program 10001: Same as 00110.

Program 10010: Same as 00101.

Program 10011 'Same as 00110, except A4A3A2 (T1 =611.

Program 10100: Same as 00001.

Program 10101: Same as 00100.

Program 10110: Same as 00100.

Program 10111: Same as 00100.

Program 11000: Same as 00100.

Program 11001: Same as 01001, exceptA4A3A2 (T2)= 101 Program 11010: Same as in Multiplication Subroutine but the operation is limited to the first cycle operation with memory address A4A3A2 being 000.

Program 11011 : Same as01111 but limitto one cycle operation with A4A3A2= 000.

Program 11100: Stop.

Machine Construction The designed microcomputer was built using available components, standard TTL SN7400 series logical family. The construction was done on two boards, in the size of approximately 8-1/2 x 11 inches, with LED (ligh emitting diodes) display and buttons on separate module. A portable battery was used as a power unit.

While the invention has been described with respect to a particular mathematical equation for calculating speed rating given specified input data, the invention might also be used for other equations to calculate speed rating or the method according to the present invention might be used to calculate other results than a speed rating.

While the present invention has been described with reference to preferred embodiments thereof, it is understood by those skilled in the art that various changes in form and application of the electronic speed rating calculator and method may be made without departing from the spirit or scope of the invention.

Claims (21)

1. An automatic speed rating computer for determining the speed rating of an entrant in a speed contest comprising, in combination: a first register for storing a signal indicative of the predetermined distance, a second register for storing a signal indicative of the desired entrant, a third register for storing a signal indicative of the time of the winner to complete the predetermined distance, means for accessing the signal from the first register means for selectively accessing the signal from the second register and subtracting means for subtracting the signal from the second register from the signal from the first register, division means for dividing the result of the aforesaid subtraction by the signal from the third register, a first memory for selectively providing a signal indicative of a constant factor, multiplication means for multiplying the signal from the first register by the signal from the first memory, and means for adding the result of said multiplication to the result of said aforesaid division to determine a speed rating;

2. The automatic speed rating computer of claim 1 including a second register for selectively storing a signal indicative of the distance the desired entrant was behind the winning entrant at the completion of the predetermined distance by the winner.

3. The automatic speed rating computer of claim 1 including means for accessing another constant and subtracting said constant from said aforesaid addition, said contstant being based on the ordinate intersection of the slope of a line which forms the linear relationship between speed and distance for a zero speed rating.

4. The automatic speed rating computer of claim 1 including means for accessing another constant based a particular speed rating and dividing the result of said subtraction by said aforementioned constant.

5. Means for determining a speed rating for a entrant in a speed contest comprising; first means for determining the average speed of the entrant over a predetermined distance and; second means for adding a factor based upon the predetermined distance of the contest.

6. The means according to claim 5 including third means for adding a constant factor for determining a base speed rating.

7. The means according to claim 6 including fourth means for dividing the result of the first three means by a constant.

8. The means according to claim 7 wherein the first means includes the predetermined distance minus the distance the desired entrant was behind the winning entrant at the completion of the predetermined distance by the winner divided by the time of the winner to complete the predetermined distance.

9. The means according to claim 8 wherein the second means includes the predetermined distance multiplied by a constant factor, which factor is based on the slope of a line which forms the linear relationship between the speed and distance for a particular speed rating.

10. The means according to claim 9 wherein the constant of the third means is determined by determining the result of the first and second means and subtracting the constant of the third means from the result so that the final result is a predetermined amount for a predetermined class of entrant.

11. The means according to claim 10 wherein the constant of the fourth means is determined so that the results of the first three means when divided by said constant will cause the speed rating to be predetermined amount for a predetermined class of entrants.

12. The means according to claim 1 operated in accordance with the relationship

where f is the predetermined distance of the race and L is the distance the entrant is behind the winner and t is the time it takes the winner to complete the race overthe predetermined distance.

13. The means according to claim 12 wherein the entrants are horses and the race is a horse race.

14. A means for determining a speed rating for an entrant in a speed contest comprising, means for providing a linear relationship between the average speed of a plurality of individuals having a common characteristic in a speed contest over predetermined distances and: means for employing said linear relationship to determine the speed rating of an entrant in a speed contest.

15. A means for determining a speed rating for an entrant in a speed contest including means for providing the time it takes an entrant in a speed contest to cover a predetermined distance; means for providing the distance covered; means for determining the speed rating by taking into consideration the linear relationship between average speed and distance in a speed contest.

16. The means of claim 15 including means for providing the distance the entrant is behind the winner to determine the speed rating of the entrant.

17. The means of claim 16 including a means for adding a constant factor for determining a base speed rating.

18. The means of claim 17 including means to multiply the predetermined distance by a constant factor, the constant factor, which factor is based on the slope of a line which forms the linear relationship between speed and distance for a particular speed rating.

19. The means of claim 18 wherein the result is a predetermined amount for a predetermined class of entrant.

20. The means of claim 1 which is operated in accordance with the relationship:

where t is the predetermined distance of the race and L is the distance the entrant is behind the winner and t is the time it takes the winner to complete the race over the predetermined distance.

21. The means according to claim 20 wherein the entrants are horses and the race is a horse race.