GB2034954A - A PCM recording and reproduction system - Google Patents

Abstract

A reproduced PCM signal in the form of continuous frames is subjected to a code check after the separation of its frame synchronizing signals and then stored in a memory. If more than two frames are continuously determined to include code errors resulting from a spliced portion of an associated PCM magnetic tape then those frames are prevented from being written in the memory but the latter is continuously read out by filling the gap with other data stored in the memory. Also an amount of data stored in the memory is sensed and maintained at a predetermined constant magnitude by controlling the speed of travel of the tape.

Description

SPECIFICATION A PCM recording and reproducing system This invention relates to improvement in a PCM recording and reproducing system and more particularly to means for filling the omission of digital signals that may occur resulting from the splice editing of a PCM magnetic record tape.

PCM recording and reproducing systems have been already well known in the field of the digital recording technique. Among them, PCM recording and reproducing systems utilizing the magnetic record tape and including the multi-track type stationary recording and reproducing head are advantageous in that the mechanism is not only simple but also the splice editing is possible. Particularly, PCM recording and reproducing systems for sound signals indispensably require the editing of the magnetic record tape and are especially advantageous in that the splice editing can be performed with a singe recorder.

The splice editing is to cut the magnetic record tape in order to remove an unnecessary portion thereof or to insert the required tape portion and to slice the tape portions into a single tape by applying short lengths of a splicing tape to the tape portions to be jointed. However, upon reproducing digital signals recorded on the spliced tape portion, some of them will be omitted for the following reasons. The cutting of the magnetic record tape causes the deterioration of the record on that portion of the tape adjacent to the cut end thereof. When the cut end portions of the tape are spliced to each other, a splice angle to the longitudinal axis of the tape may deviate from a predetermined splice angle, a mismatch may occur in the joint of the tape portions, the splicing tape may extend and so on.Also during the travel of the tape the spliced portion thereof may touch an associated head in the deteriorated manner. Even with the splice editing effected by using a jig, it is impossible to eliminate fully this omission of the digital signals. The manual splice usually utilized results in the omission of the reproduced signal for a few milliseconds. This means that several thousand bits will be omitted assuming that is at a recording speed is on the order of 1 megabits per second. This figure is far large as compared with scores of bits usually omitted resulting from flaws and scratches on and dust sticked to the magnetic record tape. Therefore the conventional compensation for the omission of reproduced signals exhibits no effect.As a result, conventional PCM recording and reproducing systems have been disadvantageous in that, noise is generated upon converting reproduced digital signal to the original analog signal and the resulting sound quality is much injured particularly for sound signals.

Accordingly, it is an object of the present invention to provide a new and improved PCM recording and reproducing system free from the omission of reproduced digital signals due to the splice editing of a PCM record medium by filling digital signals omitted upon reproducing a spliced tape portion with other digital signals stored in a memory and reproduced with a predetermined delay time.

It is another object of the present invention to provide a new and improved PCM recording and reproducing system for reproducing continuously an output signal from a PCM record medium involved by filling the omission of reproduced signals resulting from the splice editing of the PCM record medium.

It is still another object of the present invention to perform effectively the splice editing of PCM magnetic record tapes.

The present invention provides a PCM recording and reproducing system for recording a PCM signal converted from an analog signal in a predetermined pattern on a plurality of record tracks disposed on a PCM record medium and reproducing the PCM signal from the PCM record medium, comprising, memory means having a predetermined capacity to store the reproduced PCM signal, as data, therein, reading means for reading the data out from the memory means with a time delay, first sensor means for sensing a spliced portion of the record medium to produce a splice sensing signal, and writing suspending means responsive to the splice sensing signal to suspend the writing of the data in said memory means.

Preferably, second sensor means may be operatively coupled to the first sensor means to sense an amount of the data stored in the memory means and also connected to control means for controlling the amount of the data stored in the memory means to a predetermined constant amount by controlling a speed of travel of the record medium.

The present invention will become more readily apparent from the following detailed description taken in conjunction with the accompanying drawings in which: Figure 1 is a schematic diagram of one portion of a signal pattern recorded on a PCM magnetic record tape in accordance with a conventional frame distribution technique; Figure 2 is a block diagram of one embodiment according to the essential portion of the PCM recording and reproducing system of the present invention; Figure 3 is a connection diagram of the details of the slice sensor circuit shown in Fig.

2; Figure 4 is a graph illustrating signal waveforms developed at various points in the arrangement shown in Fig. 3; Figure 5 is a connection diagram of the details of the memory and control circuits shown in Fig. 2; Figure 6 is a graph illustrating signal wave formsdeveloped at various points in the arrangement shown in Fig. 5; Figure 7 is a connection diagram of the amount sensor circuit shown in Fig. 2; Figure 8 is a graph illustrating signal waveforms developed at various points in the arrangement shown in Fig. 7; and Figure 9 is a connection diagram of the details of the speed control signal generator circuit shown in Fig. 2.

In PCM recording and reproducing systems employing the stationary recording and reproducing head, the audio signal in the analog form is digitalized into a corresponding digital signal. Then a predetermined number of samples of the digital signal forms a frame with a frame synchronizing and a check signal disposed before the foremost sample and behind the rearmost sample respectively. This is repeated to form the frames one after another.

Usually, the digital signal is in the binary form, the frame synchronizing signal is formed of a predetermined number of bits and each frame includes several samples forming data bits. For example, the check signal or bits may be preferably formed of a CRCC (which is the abbreviation for "Cyclic Redundancy Check Character") code having a high ability to sense burst errors for a check bit as an example.

The frames thus formed are recorded in a predetermined pattern on a plurality of record tracks disposed on a PCM magnetic record tape. Figs. 1 shows, by way of example, some frames distributed to N record tracks Tr, T2, TN T, disposed on a PCM magnetic record tape in accordance with a conventional frame distribution technique and recorded thereon.

As shown in Fig. 1, the plurality of record tracks T1, T2, ... TN run in parallel relationship longitudinally of the record tape to be contacted by one another and each frame includes frame synchronizing bits 10 followed by data bits 12 and check bits 14 located at the end thereof. A first one of the frames is recorded on the uppermost tracks T1, as viewed in Fig. 1 on the tape and a second one of the frames is recorded on a second track T2 immediately under the uppermost track T, as viewed widthwise of the tape with a time delay equal to the duration of the frame synchronizing bits 10 and so on until the N-th frame is recorded on the lowermost track TN as viewed in Fig. 1.

Thereafter the (N + 1)th frame is recorded on the uppermost rack T, so as to be contiguous to the check bits 14 of the first frame.

Then the process as above described is repeated to record successively and repeatedly the frames on the tracks T" T2, --, TN with incremental time delays equal to the duration of the frame synchronizing bits.

In this way, the digital signal is subjected to the speed convertion to be recorded on the PCM multi-track tape as a low speed PCM signal.

Referring now to Fig. 2, there is illustrated one embodiment of the present invention wherein a digital signal, in this case, in the binary form reproduced from a PCM magnetic record tape such as shown in Fig. 1 is processed so that the reproduced signal is continuously delivered by filling up an omitted portion of the reproduced digital signal resulting from a spliced portion of the record tape with another portion of the digital signal with a speed of travel of the tape controlled. The comprise a plurality of input terminals 20 one arrangement illustrated for each track disposed on the PCM magnetic record tape and one frame synchronization separator circuit 22 connected to each input terminal 20. All the frame synchronization separator circuits 22 are connected to a code check circuit 24 that is, in turn, connected to a splice sensor circuit 26 connected to a control circuit 28.The code check circuit 24 is further connected to a memory 30 subsequently connected to an output terminal 32. The control circuit 28 is connected to the memory 30 and also to an amount sensor circuit 34. Then the quantity sensor circuit 34 is connected to a speed control signal generator circuit 36 subsequently connected to a control output terminal 38.

In operation, the frames reproduced from the associated tracks T1, T2 . ., TN on the PCM magnetic record tape are applied in parallel relationship with the incremental delay times to the input terminals 20 and then to the frame synchronization separator circuits 22 respectively. The frame synchronization separator circuits 22 separate the frame synchronizing signals 12 in the form of bits (see Fig. 1) from the mating reproduced frames to leave the remaining portions of the reproduced frames arranged in the parallel form with the incremental delay times. Then those remaining frame portions are subjected to the speed conversion to form a series signal for each set of the frames adjacent to one another widthwise of the PCM magnetic record tape.

The series signals thus formed one after another are delivered to the code check circuit 24 which check if the data bits included in each reproduced frame are erroneous. An output from the code check circuit 24 is applied to the memory 30 to be normally written therein and also to the splice sensor circuit 26. The splice sensor circuit 26 senses the presence or the absence of the splice editing in the output from the code check circuit 24.

If the splice sensor circuit 26 senses the presence of the splice editing then the same supplies a splice sensiting signal to the control circuit 28. When received the splice sensing signal, the control circuit 28 is operated to prevent the memory 30 from writing therein the output from the code check circuit 24.

The memory 30 continues to be prevented from writing that output therein while the PCM magnetic record tape is traveling until the spliced sensing signal disappears. Thereafter the data passed through the code check circuit 24 are again written in the memory 30.

On the other hand, the memory 30 is unintermittingly or continuously read out, and those data read out from the memory 30 are delivered to the output terminal 32. The amount sensor circuit 34 is responsive to an output from the control circuit 28 to sense an amount of data stored in the memory 30 to cause the speed control generator circuit 36 to generate a speed control signal which is, in turn, supplied via the control output terminal 38 to a speed control circuit (not shown) for controlling the speed of travel of the PCM magnetic record tape.

The circuits 26 through 38 will now be described in more detail with the operation thereof.

The slice sensor circuit 26 serves as first sensor means and may be of a circuit configuration shown in Fig. 3. The arrangement illustrated includes three inputs 40, 42 and 44. The input 40 is connected to a first one of three serially connected "D FLIP-FLOP" circuit 46, 48 and 50, the input 42 is connected to all the three "D FLIP-FLOP" circuits 46, 48 and 50, and the remaining input 44 is connected to a first input to an 'TANS" gate 52 including a second a third, and a fourth input connected to outputs of the "F FLIP FLOP" circuits 46, 48 and 50 respectively.

The input 44 is also connected via an inverter 54 to a first input to a "NOR" gate 62 while the outputs of the "D FLIP-FLOP" circuits 46, 48 and 50 are connected to a second, a third and a fourth input to the "NOR" gate 56.

The "AND" and "NOR" gates 52 and 56 respectively are connected to a pair of inputs R and S to an "R-S FLIP-FLOP" circuit 58 subsequently connected to an output 68.

The operation of the arrangement shown in Fig. 3 will now be described with reference to Fig. 4 wherein there are illustrated signal waverorms developed at various points in the arrangement of Fig. 3. The output from the code check circuit 24 or a series of negatively going error check pulses a (see waveform a, Fig. 4) is applied through the input 40 to the first "D FLIP-FLOP" circuit 46. Simulataveously a train of clock pulses b (see wave ormb, Fig. 4) is applied via the second input 42 to all the D "FLIP-FLOP" circuits 46, 48 and 50.As seen in Fig. 4, the error check pulses a are equal in pulse repetition period to and synchorized with the clock pulses b and each of the error check pulses a is successively passed through the three ''FLIP-FLOP" circuits 46, 48 and 50 in response to the corresponding clock pulses b so that each time the pulse a is passed through a different one of the "FLIP-FLOP" circuit it is delayed by one pulse repetition period of the clock pulses b. Therefore the error check pulses a appearing at the outputs of the "D FLIP FLOP" circuits 46, 48 and 50 has time delays equal to one, two and three times the pulse repetition period of the clock pulses b.

Further another train of clock pulses c (see waveform c, Fig. 4) is applied to the "AND" gate 52 while it is inverted in polarity by the inverter 54 and then applied to the "NOR" gate 56. As seen Fig. 4, the clock pulses c are equal in pulse repetition period to the clock pulses b and appear midway between the adjacent clock pulses b.

In Fig. 4 more than three error check pulses a are shown at dotted line to indicate that data bits continuously include errors. In the splice sensor circuit 26 shown in Fig. 2, at least three error check pulses a have continuously indicated the occurrence of errors. In other words, it has been sensed that the series signal delivered from the frame synchronization separators circuits 22 has included at least three frames continously erroneous. This means that in the frame distribution pattern as shown in Fig. 1, errors have been developed in the data resulting from at least three tracks adjacent to one another widthwise of the PCM magnetic record tape. The continous occurrence of errors widthwise of the PCM magnetic record tape is inherent to the splice editing.In the example illustrated it is considered that the three continous occurrence of errors is sufficient to determine a spliced portion of the tape.

Accordingly, the "R-S FLIP-FLOP" circuit 64 is adapted to produce a splice sensing signal din the form of a rectangular pulse (see waveform d, Fig. 4) in response to that clock pulse c developed immediately after the three error check pulses a have continuously indicated the occurrence of errors. This splice sensing signal d is delivered to the output 60 for the purpose of preventing erroneous pulses a from being written in the memory 30. The splice sensing signal dterminates upon that clock pulse coccurring immediately following the three error check pulses which continuously indicate that no error occurs after the last one of the error check pulses continuously indicating the occurrence of errors as shown in Fig. 4.

As shown in Fig. 5, the memory 30 includes an input 70 connected to the code check circuit 24, a plurality of memory sections 72, in this case, four sections arranged in paralle to one another and connected to the input 70 and an output 74 connecting the four memory sections to the output terminal 32 (see Fig. 2).

The control circuit 28 may be of a circuit configuration shown in Fig. 5 and has signal waveforms developed at various points therein as illustrated in Fig. 6. The arrangement illus trated comprises a writing input 76 connected to isçtee input to an-"AND" gate 80 including anr 6ut-pu-:t connected to a writing counter 82 and a! reading input 78 connected to a reading eounter 84.

The writing; canter 82 ish connected to an input T to a' "T FLIP-FlOP" circuit 85 included ing one output 0 connected to an input T to another "T FLl-PFLOP" circuit 86. The one output Q of the "T FLI--P-FLOP" circuit: 85 is connected one input to "AND gates: 88 and 92 while the other output Othereof is. connected to one input to "AND" gates 90 and 94.The "T FLIP-FLOP" circuit 86 includes one output Q connected to- the other inputs to the "AND" gates 90 and 92 and the other output G connected to the other inputs to the "AND" gates 88 and 94, The reading counter 84 is connected to a pair of serially connected "T FLIP-FLOP" circuits 96 and 98 subsequently connected to ''AND'' gates 100, tO2, 104 and 106 in the same manner as above described in conjunction with the writing counter 82. The "AND" gates 88 and 100 have respective outputs connected to a first decoder 108, and the "AND" gates 90 and 102 have respective outputs connected to a second decoder 110.

Similarly, the "AND" gates 92 and 104 have respective outputs connected to a third decoder 112 and the "AND" gate 94 and 106 have respective outputs connected to a fourth decoder 114. All the decoders 108, 110, 112 and 114 are connected to a separate input 116 to which clock pulses are applied and also to an output 118. The decoders 108, 110, 112 and 114 include further outputs connected to the memory 72 sections respectively.

Further a pair of outputs 120 and 122 are connected to the output Q of the "T FLIP FLOP" circuit 84 and the output Q of the "T FLIP-FLOP" circuit 96 respectively.

The output Q of the "T FLIP-FLOP" circuit 84 is also connected to one input to an "AND" gate 124 including the other input connected to a reset input 126. The output Q of the "T FLIP-FLOP" circuit 86 is further connected to one input to another "AND" gate 128 including the other input connected to an output of the "AND" gate 124. The "AND" gates 128 are connected at the outputs to the "T FLIP-FLOP" circuits 96 and 98 respectively.

The writing counter 82 counts writing frame pulses with a predetermined pulse repetition frequency successively passed through the "AND" circuit 80 up to an amount of data stored in the memory circuit 72. The count on the counter 82 is frequency divided by the "T FLIP-FLOP" circuit 85 to form control gate pulses f(see waveform f, Fig. 6) and further frequency-divided by the "T FLIP FLOP" circuit 86 to form control gate pulses e (see waveform e, Fig. 6). The "AND" gates 88: through 94 convert those control gate pulses to: gating pulses required for writing the data from the code check circuit 24 into the memory circuit 72-.

Cifniíarly, reading frame pulses successively applied to the reading input 78 are counted by the reading: counter 84 and then conver termed to control gate pulses g and h (see waveforms sand k Fig. 6) by the "T FLIP FLOP" circuits 96 and 98 after which the "AND" gates 100 through 106 produce gat ing pulses required for reading out the data stored in the memory sections 72.In order to maintain the phase relationship between the control gate pulses e, fand g, h constant as predetermined, reset pulses iwith a predeter mined pulse repetitiors frequency (see wave form i, Fig. 7) are applied through the resent input 126 to the "AND" gate 124 having the control gate pulses false applied thereto and the outputs from the "AND" gates 124 and 128 are applied to both "T FLIP-FLOP" circu its 96 and 98 respectively to reset the latter.

Thus the phase relationship between the writ ing and reading processes are maintained.

Under these circumstances, it is assumed that a spliced portion has been sensed by the splice sensor circuit 26 resulting in the gener ation of a splice sensing pulse d(see wave form d, Fig. 4). In the assumed condition, after having been inverted in polarity, the splice sensing signal d from the output 68 (see Fig. 3) is applied, as a pulse d~ (see waveform r/ , Fig. 6), to the "AND" gate 80 through a splice input 130 so that, when the pulse d~ has a value of binary ZERO, the "AND" gate 80 delivers a null output to the writing counter 82. As a result, the corre sponding control gate pulses e and fare temporally extended by the duration of the pulse d~ as shown at waveforms eand fin Fig. 6.However, if this temporal extension is within the storage capacity of each memory circuit portion then that signal appearing im mediately before the sliced tape portion is smoothly jointed with the normal signal devel oped immediately after the dropout.

Assuming that the signal recording speed is of 1 megabits per second, one splice editing results in the ommission of 5 kilobits for five milliseconds by leaving a margin of a few milliseconds. With the existing IC memories in view, it is possible to form easily the memory circuit 72 having a storage capacity sufficient to absorb the omission of data on the order of the figure just specified.

Also the waveforms fand h shown in Fig. 6 are labelled the reference numerals 1, 2, 3 and 4 in the circle. Those reference numerals also designate the memory sections starting, for example, with the uppermost section as viewed in Fig. 5 and means that each rectan gular pulse developed in the waveforms fand h is operative to write or read data in or out from that memory section designated by the same reference numeral as the rectangular pulse. For example, the pulse in the waveform flabelled 1 in circle is operated to write date in the memory section designated by the reference numeral 1 while the pulse in the waveform h laballed 3 in circle is operative to read data out from the memory section designated by the reference numeral 3.

It will readily be understood that the arrangement of Fig. 5 is effective for processing a single spliced portion but that the presence of two or three spliced portions may cause a fear that the memory circuit 72 become clear.

In order to avoid this fear, means are provided for sensing an amount of data stored in the memory sections 72 and responding to the sensed amount of data below a predetermined amount to increase the speed of travel of the PCM magnetic record tape so as to maintain a predetermined constant amount of data stored in the memory circuit 72. This permits a plurality of spliced portions to be processed.

The amount sensor circuit 34 serving as second sensor means may be of a circuit configuration shown in Fig. 7 and have signal waveforms developed at various point therein as shown in Fig. 8. The arrangement illustrated comprises a reading input 140 connected to the output 122 (see Fig. 5) and a writing input 142 connected to the output 120 (see Fig. 5). The reading input 140 is connected to a first one-shot multivibrator 144 subsequently connected to a second oneshot multivibrator 146 while the writing input 142 is connected to a third one-shot multivibrator 148 subsequently connected to a fourth one-shot multivibrator 150.The first and third one-shot multivibrators 144 and 148 respectively are connected to a pair of inputs to an "AND" gate 152 and the second and fourth one-shot multivibrators 146 and 150 respectively are connected to a pair of inputs to another "AND" gate 154. Then \ both "AND" gates 152 and 154 include respective output connected to a pair of inputs R and S of an "R-S FLIP-FLOP" circuit 156 that is connected to an output 158.

In operation, the reading and writing control gate signals h and f(see waveforms h and f, Figs. 6 and 8) enter the reading and writing inputs 140 and 142 respectively to actuate the associated one-shot multivibrators 144 and 148 to produce reading and writing gate signals jand k(see waveforms jand k, Fig. 8) with their rise. Those gate signals jand kare applied to the "AND" gate 152 to cause the latter to supply pulses 1 (see waveform 1, Fig. 8) to the reset input R of the "R-S FLIP FLOP" ' circuit 1 56.

Also the second and fourth one-shot multivibrators 146 and 150 respond to the decay of the control gate signals h and frespectively to produce gate pulses n and m (see waveforms n and m, Fig. 8). Those gate pulses m and n pass through the "AND" gate 154 to form output pulses o tsee waveform o, Fig. 8) which is, in turn, applied to the set inputs of the "R-S FLIP-FLOP" circuit 156.

Assuming that a splice sensing signal d (which is also shown at waveform d, in Fig. 8) is developed, the corresponding writing control gate pulse fis extended by the duration of the pulse dhaving a value of binary ONE as shown at waveform fin Fig. 8. This causes the reading gate pulses jand m to shift in phase from the writing gate pulses rand n respectively resulting in the generation of the set pulse a In this way a phase shift between the writing and reading control gate pulses fand h respectively has been sensed thereby to sense an amount of data stored in the memory 30. The "R-S FLIP-FLOP" circuit 156 is responsive to the set pulse oto deliver a speed control signal p (see waveform p, Fig.

8) to the output 158.

Then this speed control signal p is used to control the speed of travel of the PCM magnetic record tape. The tape speed control is accomplished by adjusting a speed of rotation of a capstan (not shown) involved in accordance with a phase difference between servo pulses resulting from the tape and a reference signal produced by an associated local quarlzcrystal oscillator. It needs that the speed of travel of the tape can vary by changing the frequency of the reference signal. For the restoration, the reference signal should increase in memory frequency while the particular castan servo mechanism (not shown) in maintained in phase locked state.

In order to change the control signals resulting from the train of clock pulses, the speed control signal generator circuit 36 serving as control means may be of a circuit configuration shown in Fig. 9. The arrangement illustrated comprises a clock input 160 connected to both a divide-by-M frequency divider 162 ;and a divide-by(M-1) frequency divider 164 which are connected to a pair of control signal generator circuits 166 and 168. Those control signal generator circuits 166 and 168 are then connected to a selector circuit 170 that is, in turn, connected to the control output 38 (see also Fig. 2).

The arrangement comprises further a control input 172 receiving the speed control signal pthrough the output 158 (see Fig. 7) and connected to a "D FLIP-FLOP" circuit 174 to which the clock input 160 is connected through a divide-by Mx(M-1) frequency divider 176.

The clock pulses entering the clock input 160 are frequency divided by both frequency dividers 162 and 164 and then converted to two types of control signal by both control signal generator circuits 166 and 168 respectively. On the other hand, the speed control signal p applied to the control input 172 is synchronized with clock pulses from the di vide by Mx(M-1) frequency divider 176 by means of the "D FILP-FLOP" circuit 174 after which the synchronized, signal from the "DFLIP-FLOP" circuit 74 is delvered to the selector circuit 170.The selector circuit 170 is responsive to the synchronized signal from the "D FLIP-FLOP" circuit 174 having a value of binary ZERO to select an output from the control signal generator circuit 166 and also to that having a valve of binary ONE to select an output from the control signal generator circuit 168 to produce a speed control signal for the travel of the PCM magnetic record tape. The speed control signal thus produced is supplied via the output terminal 38 to a speed control circuit (not shown) to control thee speed of travel of the PCM magnetic record tape The present invention exhibits the effect that the memory fills the omission of data resulting from the splice editing of an associated magnetic record tape thereby to provide continously an output signal. -.

While the present invention has been illus trated and described in conjunction with a single preferred embodiment thereof it is to be understood, that numerous changes and módi- fications may. be resorted to without departing from the spirit and scope of the present invention.

Claims (8)

1. A PCM recording and reproducing system for recording a PCM signal converted from an analog signal in a predetermined pattern on a plurality of record track disposed on a PCM record medium and reproducing the PCM signal from the PCM record medium comprising memory means having a predeter- mined storage capacity to store said reproduced PCM signal, as data, therein, reading means for reading said data out from said external memory means with a time delay, first sensor means for sensing a spliced portion of said record medium to produce a splice sensing signal, and writing suspending means responsive to said splice sensing signal to suspend the writing of a said data in said memory means.

2. A PCM recording and reproducing system as claimed in claim 1 wherein a decrease in amount of the data stored in said memory means is filled up by rendering a speed of a data writing signal higher than a speed of a data reading signal for a predetermined time interval.

3. A PCM recording and reproducing system as claimed in claim 1 wherein second sensor means is operatively coupled to said first sensor means to sense an amount of data stored in said extrnal memory means, and also connected to control means for control- ling the amount of data stored in said memory means to a predetermined constant amount by controlling a speed of travel of said record medium.

4. A PCM recording and reproducing sys tem as claimed in claim t wherein said first sensor means' includes a plurality of "FLIP FLOP" circuits serially interconnected to delay error check signals in incremental manner an "AND" gate having respective outputs from said ''FLIP-FLOP'' cir'cui'fs" and cIdok pulses applied to inputs thereto, an inverter for inverting the polarity of said clock pulses, a "NOR" gate receiving said outputs from said "FLIP-FLOP" circuits and said clock pulses passed through said inverter, and an "R-S FLIP-FLOP" circuit receiving outputs from said "AND" and "NOR" gates to provide said splice sensing signal at the output.

5. A PCM recording and reproducing system as claimed in claim 1 wherein there is provided control circuit means including a writing counter circuit for determining addresses for writing said data in said external memory means, and gate means responsive to said splice sensing signal from said first se-h- sor means to prevent said data from being written in said external memory means.

6. A PtM recording and reproducing sys- tem as claimed in claim 3 wherein said sec- ond sensor means includes gate means receiving a writing and a reading control signal for controlling the writing and reading of said data in and from said memory means, said gate means being operative to extend a duration of said writing control signal haaving a predetermined level by a duration of said splice sensing signal from said first sensor mearis when the latter signal is sensed, and a sensor circuit for sensing a phase shift between said writing and reading control signals to deliver a speed control signal for said record medium to said control means.

7. A PCM recording and reproducing sy'stem as claimed in claim 3 wherein said control means includes a divide-by-M frequericy divider, a divide-by-(M-1) frequency divider and a divide-by-(M-1) frequency divider, a train of clock pulses applied to each of said frequency dividers, control signal generator means connected to both said divide-by-M frequency divider and said divide-by(M-1) fre- quency divider to produce two types of control signal, a "D FLIP-FLOP" circuit connected to said divide-byMx(M-1) frequency divider to synchronize a speed control signal applied thereto with an output signal from said divideby-mx(M-1) frequency divider, and a selector circuit connected to said "D FLIP-FLOP" circuit and also to said control signal generator means to select one of said two types of control signal dependent upon an output from said "D FLIP FLOP" circuit, said selected type of control signal forming a speed control signal for the traveling magnetic medium.

8. A PCM recording and reproducing system substantially as hereinbefore described with reference to the accompanying drawings.