GB2033683A - Improvements in or relating to digital-analog converters - Google Patents

Abstract

A digital/analog converter is connected to the output of a Fibonacci convolution unit 4 counting pulses applied at input 6. The digital-analog converter comprises a reference value adder 1 connected to a multidigit output of a switch unit 3, and the output of which the multidigit output of the Fibonacci p-code convolution unit 4 is connected. The Fibonacci p-code convolution unit 4 comprises a plurality of stages 7 in which the contents of two adjacent bit positions and of the next bit position are subject to a convolution procedure. Each of the stages 7, except the first and the last one, comprises a flip-flop 8 whose set output is a bit output of the multidigit output of the Fibonacci p-type convolution unit 4, an AND gate 10, and an OR gate 13. The first and last stages 7 comprise, a flip-flop 8 and an OR gate 13, and a flip-flop 8 and an AND gate 10 respectively. A set input 11 and a reset input 14 of the flip-flop 8 are connected to the output of the AND gate 10 and the output of the OR gate 13 respectively, while the set input 11 of the flip-flop 8 of the stage 7 of the low-order bit position is a counting input 6 of the digit-analog converter. First and second inputs of the OR gate 13 of each intermediate stage 7 are connected to the outputs of the AND gates 10 of the (i+1) and (i+p + 1)th stages 7, respectively. First, second and third inputs of the AND gate 10 of the ith stage 7, beginning with the p + 1)th bit position, are connected to a reset output 12 of the flip-flop 8 of the same stage 7, to the set output 9 of the flip-flop 8 of the (i-1)th stage 7, and to the set output 9 of the flip-flop 8 of the (i p 1)th stage 7, respectively. The AND gates 10 each have a further input connected together to serve as a clock input 5 of the digital-analog converter. <IMAGE>

Description

SPECIFICATION Improvements in or relating to digital-analog converters The invention relates to digital-analog converters for use in the digital instrumentation industry for conversion of data.

The invention is suitable for use, for instance, with analog-digital converters, measuring information systems, and with apparatus for displaying data on cathode ray tubes with digital scanning of the beam.

According to the invention, there is provided a digital-analog converter comprising a reference value adder having a multidigit input connected to a mu Itidigit output of a switch unit, and a Fibonacci p-code convolution unit having a multidigit output connected to a multidigit input of the switch unit, the Fibonacci p-code convolution unit being provided with n stages, each stage corresponding to the ith bit position of a Fibonacci p-code lying between the first and (n - 2)th bit positions of the Fibonacci p-code being provided with a flip-flop, and AND gate and or OR gate, the stage corresponding to the low-order, zeroth, bit position of the Fibonacci p-code being provided with a flip-flop and an OR gate, and the stage corresponding to the high-order, (n-l )th, bit position of the Fibonacci p-code being provided with a flip-flop and an AND gate, the flip-flop of the stage of the ith bit position having set and reset inputs connected to the output of the AND gate of the same stage and to the output of the OR gate, of the same stage, respectively, the flip-flop of the stage of the low-order, zeroth, bit position having a reset input connected to the output of the OR gate of the same stage, and having a set input connected as a counting input of the digital converter, the flip-flop of the stage of the high-order, (n - 1)th, bit position having a set input connected to the output of the AND gate of the same stage, the set outputs of the flip-flops of all the stages being the multidigit output of the Fibonacci p-code convolution unit, first and second inputs of the OR gate of each stage of the ith bit position, lying between the zeroth and (n-2)th bit positions, being connected to the output of the AND gate of the (i + 1 )th stage and to the output of the (i + p + 1 Xth stage, respectively, first and second inputs of the AND gate of each stage of the ith bit position, lying between the first and (n - 1 )th bit positions, being connected to the reset output of the fiip-flop of the same stage and to the set output of the flip-flop of the (i- 1 )th stage, respectively, a third input of the AND gate of each ith stage, beginning with the (p + 1 Xth bit position, being connected to the set output of the flip-flop of the (i - p - 1 )th stage, and a further input of each of the AND gates being connected to a clock input of the digital-analog converter, where n is the length of the Fibonacci p-code and i = 0,1,2..., n-1.

The invention will be further described, by way of example, with reference to the accompanying drawing which is a circuit diagram of a preferred digitalanalog converter used for generating linearly varying values.

The preferred digital-analog converter comprises a reference value adder 1 having an output 2 used as the output of the converter.

The reference values, for example, reference currents, are chosen in proportion to respective Fibonacci p-numbers. This means that the weight of the ith bit position is proportional to the ith Fibonacci p-number defined according to a recurrence relationship as follows

where p is a given natural number.

The digital-analog converter further comprises a switch unit 3 (incorporating, for example, transistor switches), the switches of the switch unit 3 being equal in number to the bit positions of the Fibonacci p-code. The outputs of the switches of the switch unit 3 are used to constitute a mu Itidigit output of the switch unit3 and are connected to a multidigit input of the reference value adder 1. The digital-analog converter further comprises a Fibonacci p-code convolution unit 4 which is operated to perform a stepby-step convertion of the original p-code of a number to other code combinations representing the same number. The multidigit output of the Fibonacci p-code convolution unit4 is connected to a multidigit input of the switch unit 3.A first input of the Fibonacci p-code convolution unit4 serves as a clock input 5 of the digital-analog converter to sync hronizetransients, whereas a second input of the Fibonacci p-code convolution unit 4 is a counting in put 6 of the digital-analog converter to receive count pulses.

In the case of an arbitrary p, the Fibonacci p-code convolution unit 4 comprises n stages 7 (with n = 6 in the embodiment) equal in number to the bit positions in the Fibonacci code. Each ith stage 7 corresponds to the ith bit position of the Fibonacci p-code and comprises a flip-clop 8 whose set output 9 is connected to the ith bit position of the multidigit input of the switch unit 3. Note that i = 0,1,2 .

1. Each stage 7 related to the bit positions lying between the first and (n - 1 )th, fifth, bit positions incorporates an AND gate 10 whose output is connected to a set input 11 of the flip-flop 8. A first input of each AND gate 10 is connected to a reset output 12 of the corresponding flip-flop 8. In addition, each stage 7 corresponding to the bit positions lying in a range from Oto n - 2 comprises an OR gate 13. The output of the OR gate 13 of each such stage 7 is connected to a reset input 14 of the flip-flop 8 of the same stage 7. The following connections are established between the stages 7.A first input of the OR gate 13 of the stage 7 of the ith position (with i equal, for example, to 2) is connected to the output of the AND gate 10 of the stage 7 of the (i + 1)th, (for example third) bit position, while a second input of the same gate 13 is connected to the output of the AND gate 10 of the stage 7 of the (i + p + 1 Xth (for example fourth) bit position since p = 1 in this case.A second input of the AND gate 10 of the stage 7 of the ith (for example second) bit position is connected to the set output 9 of the flip-flop 8 of the stage 7 of the (i -1 )th, (for example first) bit position, the next input of the AND gate 10 of the stage 7 of the ith (for example second) bit position is connected to the set output 9 of the flip-flop 8 of the stage 7 of the (i - p - 1 )th, (for example zeroth) bit position, and the remaining inputs of all the AND gates 10 are joined together to constitute the clock input 5 of the digital-analog converter which receives clock signals for transients.

The set input 11 of the flip-flop 8 of the stage 7 of the iow-order, zeroth, bit position is the counting input 6 of the digital-analog converter which receives count pulses.

The operation of the digital-analog converter (with p=1) is as follows. Count pulses are applied to the counting input 6 of the digital-analog converter. The Fibonacci p-code convolution unit 4 operates to convert a train of count pulses to a respective Fibonacci p-code which appears at the multidigit output of the Fibonacci p-code convolution unit 4 and activates respective switches of the switch unit 3. These switches, in turn, select the reference elements in the reference value adder 1 having their values proportional to respective Fibonacci p-numbers. As a result, the output 2 of the reference value adder 1 provides an analog value proportional to the number of pulses, N, applied to the counting input 6.

Within a time interval between two consecutive, for example, first and second, count pulses, clock pulses are applied to the clock input to allow for a sequential conversion (convolution) of the original p-code of a natural number to other code combinations of the same number. In this case, the output 2 provides the same analog value corresponding to the original p-code and selected previously under the action of the initial count pulse.

Given below is a detailed description of the Fibonacci p-code convolution unit 4. Before the operation commences, the flip-flops 8 of all the stages 7 are kept in the 0 state. As a result, enable signals (logic l's) available from the reset outputs 12 of the flip-flops 8 are applied to the first inputs of the AND gates 10 while disable signals (logic 0's) are applied to the second and third inputs of the AND gates 10.The first count pulse arriving at the counting input 6 causes the flip-flop 8 of the stage 7 of the zeroth bit position to take up the 1 state, with the result that the following codeword is stored in the Fibonacci p-code convolution unit4: 54321 0- nos. of bit positions of Fibonacci 1 codeN=1 0 0 0 0 0 1codeword In the reference value adder 1, the reference value of the zeroth bit position is selected, fp (0)=1, and the output 2 provides the first component of a linearly varying value proportional to N = 1.

When a 1 is placed in the flip-flop 8 of the stage 7 of the zeroth bit position, an enable signal (logic 1 ) produced at the set output of that flip-flop 8 is deli vered to the second input of the AND gate 10 of the stage 7 of the first bit position.

A clock signal to synchronize a transient is a train of short clock pulses having a duration equal to the duration of the transient occurring in the AND gate 10. The time interval between the clock pulses is equal to the duration of the transient occurring in the digital-analog converter during the switchingon/switching-off of any switch. Note that the first clock pulse is applied to the clock input 5, with a count pulse delivered to the counting input 6, after a time interval equal to the duration of the transient in the digital-analog converter occurring during the switching-on of the switch of the zeroth bit position.

The first clock pulse applied to the input of the AND gate 10 of the stage 7 of the first bit position causes the appearance of a logic 1 at the output of this AND gate 10 with the resu It that the flip-flop 8 of the stage 7 of the first bit position takes up the 1 stafe. That logic 1 is supplied through the OR gate 13 of the stage 7 of the zeroth bit position and causes the flipflop 8 of the stage 7 of the zeroth bit position to take up the 0 state.As a result, the codeword in the Fibonacci p-code convolution unit 1 assumes the following value 543 2 1 0 - nos. of bit positions of Fibonacci 1-code 000010-codeword This codeword also represents the number 1. In the digital-analog converter, a transient takes place due to simultaneous switching-on of the flip-flop 8 of the stage 7 of the first bit position and switching-off of the flip-flop 8 of the stage 7 of the zeroth bit position. After the transient has been terminated, the output 2 produces again a linearly varying value proportional to N=1.

The second count pulse causes the flip-flop 8 of the stage 7 of the zeroth bit position to take up the 1 state with the result that the following codeword is placed in the Fibonacci p-code convolution unit 4 5432 1 0 - nos. of bit positions of Fibonacci 1-code 000011-codeword In the reference value adder 1, the reference value of the zeroth bit position is selected and the output 2 produces the second component of a linearly vary- ing value proportional to N=2.

Enable signals therefore appear at the first, second and third inputs of the AND gate 10 of the stage 7 of the second bit position. The appearance of a clock pulse at the clock input 5 causes the production of a logic 1 at the output of that AND gate 10. This logic 1 causes the flip-flop 8 of the stage 7 of the second bit position to take up the 1 state and also causes, via the OR gates 13 of the stages 7 of the first andzernth bit positions, the flip-flops 8 of these stages 7 to take up the 0 state, thereby resulting in a codeword as follows 5432 1 2 1 nos. of bit positions of Fibonacci 1-code 0 0 0 1 0 0 - codeword This codeword represents the Fibonacci 1-code of the number N equal to 2. In the digital-analog con verted, a transient takes place due to simultaneous switching-on of the flip-flop 8 ofthe stage 7 of the second bit position and switching-off of the flip-flopsF 8 of the stages 7 of the first and zeroth bit positions.

After this transient has beenterminated, a linearly varying value proportional to N=2 appears at the output 2.

After the seventh count pulse and all the clock pulses which follow it, a static state of the Fibonacci p-code convolution unit 4 is as follows 54321 0-nos. of bit positions 01 01 00-codeword This condition corresponds to the Fibonacci I-code of the number 7. In this case, an analog value proportional to the natural number7 appears at the output 2.

With the eighth count pulse available, the first intermediate state which Fibonacci p-code convolution unit 4 assumes is as follows 543 2 1 0 - nos. of bit positions 0 1 0 1 0 1 - codeword This condition corresponds to the Fibonacci 1-code of the natural number 8. With the first clock pulse available, the Fibonacci p-code convolution unit 4 assumes a new intermediate state as follows 54321 0- nos. of bit positions 010110-codeword This condition corresponds to the second Fibonacci 1-code of the natural number 8. When subsequent count pulses arrive, the operational steps are repeated.

The advantage of the preferred digital-analog converter is that a transient occurring during pulse counting is broken down into a number of local transients belonging to not more than three bit positions, with, (i - I )th and (i - p - 1 )th, at a time. In addition, it is possible to control the duration of the transient using clock pulses, with the resultthatthe quality of the transient is enhanced and its power is decreased.

In the preferred digital-analog converter, the appearance of any count pulse causes the switching-on of a single, zeroth, bit position only and the output of the converter immediately produces a static value corresponding to N, with a concurrent production of a transient. This feature also tends to improve the transient quality and is considered to be important in the case of analog-digital converters with feed-back as used in scanning-type digital measuring systems wherein the digital-analog converter is coupled to the input of a comparator which could produce a false response to a transient.

Moreover, functional check of the digital-analog converter is a simple procedure as follows. After the current count pulse has been delivered and an output analog value corresponding to N has been selected, it is sufficient to check the output value for constancy each time a clock pulse is applied. A nonconstancy of that value may only be due to the fact that the weights of the individual bit positions in the digital-analog converter do not obey the recurrence relationship (1). This means that the latter is used as a specific "mathematical checker". If a large deviation from the constancy takes place, then trouble in the digital-analog converter is likely to occur.

The implementation of the transient in which the weights of bit positions are subject to a convolution procedure (without changing the numerical equivalent of N) as follows

001 Q1 01 1 1 01a00 N=?010l~10000 101 100oooo 100000000 may be treated as an averaging of the output analog value, which provides for a higher accuracy of the preferred digital-analog converter.

Claims (2)

1. Adigital-analog converter comprising a reference value adder having a multidigit input connected to a multidigit output of a switch unit, and a Fibonacci p-code convolution unit having a multidigit output connected to a multidigit input of the switch unit, the Fibonacci p-code convolution unit being provided with n stages, each stage corresponding to the ith bit position of a Fibonacci p-code lying between the first and (n - 2)th bit positions of the Fibonacci p-code being provided with a flip-flop, an AND gate and an OR gate, the stage corresponding to the low-order, zeroth, bit position of the Fibonacci p-code being provided with a flip-flop and an OR gate, and the stage corresponding to the high-order, (n-1 )th, bit position of the Fibonacci p-code being provided with a flip-flop and an AND gate, the flip-flop of the stage of the ith bit position having set and reset inputs connected to the output of the AND gate of the same stage and to the output of the OR gate of the same stage, respectively, the flip-flop of the stage of the low-order, zeroth, bit position having a reset input connected to the output of the OR gate of the same stage, and having a set input connected as a counting input of the digital converter, the flip-flop of the stage of the high-order, (n 1 Xth, bit position having a set input connected to the output of the AND gate of the same stage, the set outputs of the flip-flops of all the stages being the multidigit output of the Fibonacci p-code convolution unit, first and second inputs of the OR gate of each stage of the ith bit position, lying between the zeroth and (n - 2)th bit positions, being connected to the output of the AND gate of the (i + 1 Xth stage and to the output of the (i + p + 1 )th stage, respectively, first and second inputs of the AND gate of each stage of the ith bit position, lying between the first and (n 1 Xth bit positions, being connected to the reset output of the flip-flop of the same stage and to the set output of the flip-flop of the (in 1 )th stage, respectively, a third input of the AND gate of each ith stage, beginning with the (p + 1 )th bit position, being connected to the set output of the flip-flop of the (i-p - 1 )th stage, and a further input of each of the AND gates being connected to a clock input of the digital-analog converter, where n is the length of the Fibonacci p-code and i = 0,1,2 . . ., n -1 .

2. A digital-analog converter substantially as hereinbefore described with reference to and as illustrated in the accompanying drawing.