GB2033149A - Semiconductor device - Google Patents

Abstract

A semiconductor device comprises a semiconductor substrate having at least one semiconductor region formed therein and a laminate structure including a polycrystalline silicon layer (24) formed on the semiconductor substrate and a metal layer (25) formed on the polycrystalline silicon layer (24). The metal layer (25) extends beyond the periphery of the polycrystalline silicon layer (24). In a variant a polycrystalline silicon layer is disposed on an oxide layer over the substrate and constitutes a resistor the end contacts of which are formed by metallisations which extend beyond the end and the lateral edges of part of the polycrystalline layer. <IMAGE>

Description

SPECIFICATION Semiconductor device This invention relates to a semiconductor device, and more particularly to a semiconductor device having an improved laminate structure formed in at least a portion thereof.

Polycrystalline silicon, hereinafter referred to as "poly-Si", is widely used as a part of the electrode of a semiconductor region such as a base or emitter or as a resistance member or a wiring layer, for enhancing the integration degree of a semiconductor device or improving the performance of a transistor. Poly-Si is also used as the source of impurity diffusion. Particularly, poly-Si used as the diffusion source and electrode for forming an emitter region of a high frequency transistor is effective for enabling the transistor to exhibit improved electric properties and reliability.

In general, a wiring layer is formed of metal. Thus, for the case of using a poly-Si layer, a metal wiring layer is in contact with the poly-Si layer. What should be noted is that breakage of the metal wiring layer tends to take place at the contact portion in the step of forming the metal wiring layer, leading to a decreased reliability of the semiconductor device.

Specifically, a wiring layer of laminate structure is formed by depositing a wiring metal on a poly-Si layer formed in advance in a desired shape, followed by selectively removing the metal layer by photo etching technique or the like. Appended Figures 1A and 1 B are intended to show the situation. It is seen that a poly-Si layer 4 is formed in a manner to cover the exposed portion of a semiconductor region 2 formed in a semiconductor substrate 1 and to cover partly an insulation layer 3. Further, a metal wiring layer 5 is formed in a manner to cover the poly-Si layer 4 and part of the insulation layer 3. In general, the metal layer 5 is rendered abnormally thin at a boundary portion 5a between the portion disposed on the poly-Si layer 4 and the portion disposed on the insulation layer 3 and strains are concentrated in the boundary portion 5a.

In addition the metal wiring layer 5 does not cover entirely the poly-Si layer 4 as clearly seen in Figure 1 A. It follows that the edges of the boundary portion 5a are brought into direct contact with the etchant in the metal layer etching step. Naturally, the edges mentioned are abnormally etched, bringing about wedge-shaped clearances in the metal layer. The difficulty is further promoted if the metal layer has a low activation energy of etching, resulting in failure to achieve a satisfactory connection of the metal layertothe poly-Si layer.

The difficulty can be overcome to some extent by adjusting the conditions for the metal vapor deposition. But, the improvement achieved in this fashion is not yet satisfactory.

An object of this invention is to provide a semiconductor device comprising an improved laminate structure of a metal layer and a poly-Si layer free from the difficulty accompanying the conventional device and a method of producing the same.

According to this invention, there is provided a semiconductor device, comprising: a semiconductor substrate having at least one semiconductor region formed therein; and a laminate structure including a poly-Si layer formed on the semiconductor substrate and a metal layer formed on the poly-Si layer, said metal layer extending beyond the periphery of the poly-Si layer.

In general, the laminate structure includes an insulation layer formed on the semiconductor su bstrate.

In a first embodiment of this invention, the poly-Si layer constitutes a part of the electrode mounted to the semiconductor region. In this case, the insulation layer has an aperture exposing the semiconductor region formed in the semiconductor substrate and the poly-Si layer covers the exposed surface of the semiconductor region and the insulation layer around the aperture.

In a second embodiment, the poly-Si layer acts as a resistance member or a wiring layer. In this case, the poly-Si layer need not be in direct contact with the semiconductor region.

This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figure 1A is a plan view showing a part of a conventional semiconductor device; Figure 1B is a cross sectional view along the line 1B-lBofHgure 1A; Figure 2A is a plan view showing a part of a semiconductor device according to one embodiment of this invention; Figure 2B is a cross sectional view along the line IIB-IIB of Figure 2A; Figure 3A to 3E are cross sectional views collectively showing a method of producing a semiconductor device according to one embodiment of this invention; Figure 4A is a plan view showing a semiconductor device according to another embodiment of this invention; and Figure 4B is a cross sectional view along the line IVB-IVB of Figure 4A.

Figures 2A and 2B collectively show a semiconductor device of the present invention in which a poly-Si layer constitutes a part of the electrode mounted to the semiconductor region. It is seen that a semiconductor region 22, e.g. a base or emitter region, is formed in a semiconductor substrate 21.

Further, an insulation layer 23 consisting of, for example, SiO2 or Si3N4 is formed on the surface of the substrate 21. The insulation layer 23 has an aperture 23a exposing the surface of the semiconductor region 22. In this embodiment, a poly-Si layer 24 is formed in a manner to fill the aperture 23a and cover the insulation layer 23 around the aperture 23a.

Figure 2A clearly shows that a metal wiring layer 25 formed on the poly-Si layer 24 extends beyond the periphery of the poly-Si layer, resulting in that the peripheral portion of the metal wiring layer 25 is substantially flat and uniform and is in direct contact with the insulation layer 23. Although the metal wiring layer 25 is abnormally thin along the periphery of the poly-Si layer 24, it has a uniform thickness in the region apart from the periphery of the poly-Si layer. In this invention, the metal layer is etched so as to leave such a uniform thickness portion. In other words, the thin portion along the periphery of the poly-Si layer 24 is not brought into contact with the etchant in the etching step. It follows that the device shown in Figures 2A and 2B is free from abnormal etching of the metal layer and from wedge-shaped clearances within the metal layer.Naturally, the metal layer is satisfactorily kept in contact with the poly-Si layer.

Incidentally, the poly-Si layer 24 may be doped with an n- or p-type impurity. Naturally, the doped poly-Si layer exhibits an improved conductivity.

Also, it is possible to use the doped poly-Si layer as a diffusion source for forming, for example, a base or emitter region of a transistor.

Figures 3A to 3E collectively show how to produce a a semiconductor device of this invention.

In the first step, a silicon oxide layer 32 is formed on the entire surface of an n-type silicon substrate 31 having an impurity concentration of, for example, 3 x 1015, followed by selectively removing the oxide layer 32 for providing apertures 32a and 32b. Then, an impurity is diffused into the substrate 31 through the aperture 32a, with the other aperture 32b covered, so as to form a base region 33 about 0.5 # deep, followed by forming a thin oxide layer 34 by thermal oxidation, said oxide layer 34 filling the apertures 32a and 32b (see Figure 3A).

A silicon nitride layer 35 having a thickness of, for example, about 1000 is formed in a manner to cover the oxide layers 32 and 34, followed by selectively removing the silicon nitride layer 35 so as to provide apertures 35a, 35b and 35c simultaneously. Then, the silicon oxide layer 34 is selectively removed by utilizing the apertures 35b and 35c of the nitride layer, with the aperture 35a covered, so as to provide apertures 34a and 34b exposing the surface of the substrate 31. As shown in Figure 3B, the aperture 34a communicates with the aperture 35b and the aperture 34b with the aperture 35c.Poly-Si layers 36 and 37 each doped with an n-type impurity, e.g., phosphorus or arsenic, are formed in a manner to cover the apertures 34a and 34b, respectively, and the adjacent regions thereof, followed by forming an emitter region 38 and a high impurity concentration region 39 by impurity diffusion from the poly-Si layers 36 and 37, respectively (Figure 3B). Incidentally, the high impurity region 39 is positioned in a collector region and serves to provide an ohmic contact with the collector electrode which is to be formed later.

After formation of the emitter region 38 and the high impurity region 39, a silicon oxide layer 40 is formed on the entire surface by a low temperature gas phase growth method as shown in Figure 3C.

The oxide layer growth is carried out at 500 to 600 C.

It should be noted that the heat in this step serves to transfer into the oxide layer 40 alkali metal ions such as sodium ions present at the boundaries between the poly-Si layers 36,37 and the substrate 31. The oxide layer 40 containing the alkali metal ions is then removed for cleaning the semiconductor device.

Then, the oxide layer 34 in direct contact with the substrate is removed at the portion exposed by the aperture 35a of the nitride layer 35 by a wash out method using an ammonium fluoride solution or a dilute hydrofluoric acid so as to provide an aperture 34c partly exposing the base region 33 as shown in Figure 3D. It is unnecessary to use a photoresist in this step because silicon nitride and poly-Si are not etched by the etchant mentioned above.

Finally, a metal layer about luthick is deposited on the entire surface by a sputtering method, followed by selectively etching the metal layer so as to provide electrodes or wiring patterns 41,42,43 as shown in Figure 3E. The metal layer is formed of, for example, aluminum or an aluminum-silicon-copper alloy and an aqueous solution of acetic acid, nitric acid or phosphoric acid is used as the etchant. It is important to note that the etching should be carried out such that the remaining metal layers 42 and 43 cover entirely and extend beyond the peripheries of the poly-Si layers 36 and 37, respectively. As described previously, the metal layer is abnormally thin along the periphery of the poly-Si layer.In accordance with the invention, the metal layer should be etched so as to have a uniform thickness portion in the extended region apart from the periphery of the poly-Si layer, thus forming the metal layers 42 and 43, preventing abnormal etching, leading to breakage, of the metal layer.

Incidentally, it is possible to use titanium, molybdenum, tungsten, etc. for forming the metal layer.

Figures 3A to 3E are directed to a method of producing an npn transistor. But, a pnp transistor can also be produced by simply reversing the conductivity type of the impurity.

Figures 4A and 4B collectively show that a poly-Si layer 54 acts as a resistance member or a wiring layer. In this case, metal layers 55 and 56 coverting the end portions of the poly-Si layer 54 extend beyond the peripheries of the end portions of the poly-Si layer 54. Incidentally, reference numerals 51 and 53 shown in the drawings denote a silicon substrate and an insulation layer, respectively.

Claims (10)

1. A semiconductor device comprising: a semiconductor substrate having at least one semiconductor region formed therein; and a laminate structure including a polycrystalline silicon layer formed on the semiconductor substrate and a metal layer formed on the polycrystalline silicon layer, said metal layer extending beyond the periphery of the polycrystalline silicon layer.

2. The semiconductor device according to claim 1, wherein the laminate structure comprises an insulation layer in direct contact with the semiconductor substrate and having an aperture partly exposing the semiconductor region, and the polycrystalline silicon layer fills the aperture and covers the insulation layer around the aperture.

3. The semiconductor device according to claim 2, wherein the polycrystalline silicon layer contains an impurity contributing to the conductivity.

4. The semiconductor device according to claim 3, wherein the polycrystalline silicon layer contains an n-type impurity.

5. The semiconductor device according to claim 3, wherein the polycrystalline silicon layer contains a p-type impurity.

6. The semiconductor device according to claim 2, wherein the polycrystalline silicon layer contains an impurity which has been partly diffused into the semiconductor substrate for forming the semiconductor region.

7. The semiconductor device according to claim 1, wherein the polycrystalline silicon layer acts as a resistance member.

8. The semiconductor device according to claim 1, wherein the polycrystalline silicon layer acts as a wiring layer.

9. A method of producing a semiconductor device comprising the steps of: forming an insulation layer on the surface of a semiconductor substrate having at least one semiconductor region formed therein; selectively forming a polycrystalline silicon layer on the insulation layer; forming a metal layer on the polycrystalline silicon layer and the exposed portion of the insulation layer; and selectively etching the metal layer in its substantially uniform thickness portion outside and apart from the periphery of the polycrystalline silicon layer.

10. The semiconductor device, substantially as herein before described with reference to Figures 2A to 48.