GB2032210A

GB2032210A - Logic Circuit

Info

Publication number: GB2032210A
Application number: GB7840126A
Authority: GB
Original assignee: Kushner J K
Current assignee: Kushner J K
Priority date: 1978-10-11
Filing date: 1978-10-11
Publication date: 1980-04-30
Also published as: GB2032210B

Abstract

A logic signal and an amplified version of it are summed at an output point, to reduce the time taken for the output to reach its maximum amplitude. Multi-emitter input arrangements are described in which the amplified version of the signal is derived from an emitter coupled pair of farther transistors. <IMAGE>

Description

SPECIFICATION Method and Logic Circuit for Converting Signals The invention relates to computer industry, and more-particularly to a method and a logic circuit for converting signals.

The invention is applicable to the design of LSI logic circuits of a very high speed to be employed in high performance computers belonging to the fourth generation. Other uses are concerned with automatic devices and with measurement and radar engineering systems.

There is disclosed a method for converting signals comprising logically converting the source signals, amplifying logic signals produced and passing the logic signals to the output of a respective logic circuit, which method comprises, according to the invention, passing the logic signals to the output of a respective logic circuit during the amplification and subjecting the amplified and the produced logic signals to voltage summation.

There is disclosed a logic circuit to realize the proposed method, comprising a logic arrangement and an amplifier which has an input coupled to an output of the logic arrangement, and has one of its outputs coupled to at least one true output of the logic circuit, the output of the logic arrangement being coupled, according to the invention, to the true output of the logic circuit.

Preferably, in a logic circuit, according to the invention, the logic arrangement having its output coupled, via a resistor, to a true output of the amplifier coupled to at least one true output of the logic circuit.

Advantageously, in a logic circuit, according to the invention, the logic arrangement having its output coupled to the true output of the logic circuit via a resistor, the true output of the amplifier being the true output of the logic circuit, and a complement output of the amplifier being coupled to the output of the logic arrangement.

Preferably, in a logic circuit, according to the invention, the logic arrangement has its output and the amplifier has its complement output both coupled to the true output of the logic circuit via the same resistor.

Advantageously, in a logic circuit, according to the invention, the logic arrangement has its output coupled to the true output of the logic circuit via a resistor and an emitter follower, connected in series, the true output of the amplifier being coupled to the true output of the logic circuit via the emitter follower.

Preferably, in a logic circuit, according to the invention, the logic arrangement comprises a multiple emitter transistor performing logical conversion and forward amplification of the signal, the collector of the multiple emitter transistor being coupled to an input of a current switch which provides for reverse amplification of the signal, and the base of the multiple emitter transistor being coupled to a complement output of the current switch.

Advantageously, in a logic circuit, according to the invention, the logic arrangement comprises a multiple emitter transistor performing logical conversion and forward amplification of the signal, the base of the multiple emitter transistor being coupled, via another resistor, to a voltage source, and the collector of the multiple emitter transistor being coupled to the input of the emitter follower.

Preferably, in a logic circuit, according to the invention, the amplifier is implemented as a current switch having its complement output coupled to at least one complement output of the logic circuit via second and third emitter followers connected in series, the third emitter follower being implemented as a multiple emitter transistor, and a still another resistor being inserted between the output of the second emitter follower and the output of the logic arrangement in order to obtain an additional voltage signal passing through the first resistor.

The disclosed method provides for a reduced time interval necessary for the restoration of the signal being passed through any one of the disclosed logic circuits, with result that the logic circuits can operate at a high speed.

The logic circuits disclosed include a smaller number of components, require low power consumption, can perform complex logic functions and possess high speed of operation.

The invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 shows an embodiment of a logic circuit, according to the invention; Figure 2 shows another embodiment of a logic circuit to provide for a higher gain of the amplifier, according to the invention; Figure 3 shows a still another embodiment of a logic circuit comprising an output emitter follower, according to the invention; Figure 4 shows a yet another embodiment of a logic circuit utilizing an amplifier with a negative feedback, according to the invention; Figure 5 shows another embodiment of a logic circuit with an amplifier having true and complement outputs and a negative and positive feedback according to the invention;; Figure 6 shows a still another embodiment of a logic circuit possessing a higher speed of operation and a low output impedance, according to the invention; Figure 7 is a circuit diagram of an AND gate built around emitter followers, according to the invention; Figure 8 shows a circuit diagram of an AND OR/AND-OR-lnvert gate with a logic arrangement built around multiple emitter transistors, according to the invention; Figure 9 shows a circuit diagram of an AND/OR gate with an input multiple emitter transistor performing logical conversion and amplification of the signal according to the invention; Figure 10 shows a circuit diagram of a logic circuit having no amplifier, according to the invention;; Figure 11 shows a circuit diagram of an AND OR/AND-OR-lnvert gate with a complement output used for a recovery of the signal provided by true output, according to the invention; Figure 12 shows timing diagrams for different points of a logic circuit, according to the invention; Figure 13 shows a series of characteristic curves of a chain of gates, according to the invention.

Figure 1 illustrates an embodiment of a logic circuit 1 of the invention to implement the disclosed method for converting signals. The logic circuit 1 comprises a logic arrangement 2 and an amplifier 3 connected in series. Those inputs of the logic arrangement 2 to which the source signals are applied serves as the inputs of the logic circuit 1, while one of the outputs of the amplifier 3 is coupled (in a direct relationship in the given embodiment) to a true output 4 of the logic circuit 1. The output of the logic arrangement 2 is coupled to the true output 4 of the logic circuit 1. This provides for the application of the logic signals obtained during the conversion of the source signals in the logic arrangement 2 to the true output 4 of the logic circuit 1 and for simultaneous amplification of the logic signals in the amplifier 3.The internal resistance of the logic arrangement 2 serves as a load for the amplifier 3.

Figure 2 illustrates another embodiment of the logic circuit 1 of the invention which comprises the logic arrangement 2 having its output coupled to the true output 4 of the logic circuit 1 via a resistor 5. The latter provides for an increase in the internal resistance of the logic arrangement 2 in order to increase the gain of the amplifier 3. A true output of the amplifier 3 is coupled directly to the true output 4 of the logic circuit 1. In this case, the working characteristics of the logic circuit 1 do not vary providing that the resistor 5 is inserted between the output of the logic arrangement 2 and the amplifier 3 and that the input of the amplifier 3 is coupled to its true output, i.e., to a true output of the logic circuit 1 (such an embodiment is not shown in Fig. 2). In this case, the logic circuit 1 offers somewhat higher noise immunity.

Figure 3 illustrates a still another version of the logic circuit 1 of the invention wherein the output of the logic arrangement 2 is coupled to the true output 4 of the logic circuit 1 via a resistor 5 and an emitter follower 6 connected in series. A true output of the amplifier 3 is coupled to the true output 4 of the logic circuit 1 via the emitter follower 6.

Figure 4 illustrates a yet another embodiment of the logic circuit 1 of the invention wherein a complement output of the amplifier 3 is coupled to the output of the logic arrangement 2 which is coupled to the true output of the logic circuit 1 via the resistor 5. Like the above embodiments, the input of the amplifier 3 is coupled to the output of the logic arrangement 2; however, it is possible to connect the input of the amplifier 3 to the output of the logic arrangement 2 via the resistor 5 (such an embodiment is not shown in Fig. 4) and the noise immunity of the logic circuit 1 is increased in this case.Note that in the embodiment according to Fig. 3 the connection of the amplifier 3 with a positive feedback to the output of the logic arrangement 2 results in a deterioration of the frequency characteristic of the logic arrangement 2; on the other hand, the embodiment of Fig. 4 is freed of this drawback since the amplifier 3 has a negative feedback; in the latter case, however, there is an increase in the loss of the magnitude of the logic signal in the logic arrangement 2.

Figure 5 illustrates another embodiment of the logic circuit 1 of the invention which has no drawbacks found in the embodiments of Figs. 3 and 4. In the embodiment of Fig. 5, use is made of the true and complement outputs of the amplifier 3 concurrently. The output of the logic arrangement 2 and the complement output of the amplifier 3 are coupled to the true output 4 of the logic circuit 1 via the resistor 5. The true output of the amplifier 3 is coupled directly to the true output 4 of the logic circuit 1. The input of the amplifier 3 is coupled directly to the output of the logic arrangement 2. As a result, the logic circuit 1 of the described embodiment (Fig. 5) has a high transfer factor as in the case of the embodiment of Fig. 3, while the logic arrangement 2 possesses a good frequency characteristic similar to that of the embodiment of Fig. 4.

Figure 6 illustrates another embodiment of the logic circuit 1 of the invention wherein the output of the logic arrangement 2 is coupled to the true output 4 of the logic arrangement 2 via the resistor 5 and an emitter follower 6. The true output of the amplifier 3 is coupled to the true output 4 of the logic circuit 1 via the emitter follower 6.

The emitter follower 6 (Figs 3, 6) makes it possible to decrease the output impedance of the logic circuit 1 and, therefore, to decrease the time delay of the logic signal in the case where a load is available.

Figure 7 illustrates a circuit diagram of the embodiment of Fig. 2 performing the AND function. The logic arrangement 2 (Fig. 7) is built around emitter followers 7t to 7m where m is an integer number equal to,the number of the inputs of the logic circuit 1, namely, to 3. The emitter followers 71 to 73 have their bases used as the inputs of the logic circuit 1, and have their emitters joined together and coupled to the direct output 4 of the logic circuit 1 and to a current source 8. The input and the true output of the amplifier 3 are coupled to the output of the logic arrangement 2, i.e., to the true output 4 of the logic circuit 1.

Figure 8 illustrates a circuit diagram of the embodiment of Fig. 3. The logic circuit 1 (Fig. 8) performs a complex function AND-OR/AND-OR Invert since here both the true output 4 and a complement output 9 of the logic circuit 1 produce output signals. The logic arrangement 2 utilizing a multiple emitter transistor 10 which is part thereof and performs the OR function. The emitters of the multiple emitter transistor 10 are coupled to respective current sources 8 and serves as the inputs of the logic circuit 1. The transistor 1 0 has its collector joined together with its base and coupled, via a resistor 11, to a common bus 12 and, via a resistor 5, to the input and the true output of the amplifier 3 which is a current switch built around two transistors 1 3 and 14.The current switch also comprises a resistor 1 5 which provides a means of coupling the transistor 13 to the common bus 12, and a current source 8 coupled to the emitters of the transistors 1 3 and 14. The base of the transistor 14 is coupled to a reference voltage source 1 6.

The true output of the amplifier 3, namely, the collector of the transistor 14, is coupled, via the emitter follower 6 built around a multiple emitter transistor, to the true outputs 4 of the logic circuit 1 which serve as the emitters of that multiple emitter transistor. Coupled to the complement output of the amplifier 3, namely, to the collector of the transistor 13, is an emitter follower 1 7 used to effect matching between the voltage levels at the inputs and the complement outputs 9 of the logic circuit 1. The emitter follower 1 7 is built around a transistor having its collector and emitter coupled respectively to the common bus 12 and to its own current source 8.The output of the emitter follower 1 7 is coupled to an emitter follower 1 8 utilizing a multiple emitter transistor having its emitters coupled directly to the complement outputs 9 of the logic circuit 1. As shown in Fig. 8, the logic arrangement 2 of the logic circuit utilizers three multiple emitter transistors. The first logic stage built around the emitter followers 1 8 and 6 performs the "wired" AND function; this can be attained by joining together the complement outputs 9 and the true outputs 4 of the logic circuit 1 with respective complement and true outputs of other logic circuits which are signal sources (the latter logic circuits are not shown in the drawings). The second logic stage performing the OR function utilizes a diode-coupled multiple emitter transistor 10.The embodiment of Fig. 8, as compared to that of Fig. 7, is advantageous since it can perform a complex logic function with inversion. Since the emitter followers 4, 9 are connected to the output of the logic circuit 1, and not to the input of the latter, this then result in a decrease on the output impedance of the logic circuit 1 and allows for the use of multiple emitter transistors as emitter followers with the result that the number of components and logic contacts in the logic circuit 1 is decreased.

Figure 9 illustrates a circuit diagram of the embodiment of Fig. 6 used to perform the AND OR function. The collector of the multiple emitter transistor 10 is coupled to its base, which is the output of the logic arrangement 2, via the resistor 5 and is coupled to the common bus 12 via the resistor 1 The transistor 10 operates concurrently to perform the OR function and to accomplish forward amplification of the signal. A current switch performing reverse amplification of the signal has its complement output coupled to the output of the logic arrangement 2, namely, to the base of the multiple emitter transistor 10. The emitter follower 6 is made as a multiple emitter transistor.The output of the logic arrangement 2, namely, the base of the multiple emitter transistor 10, is coupled to the true outputs of the logic circuit 1 via the resistor 5 and the emitter follower 6.

Figure 1 0 illustrates a circuit diagram of the logic circuit 1 of the invention similar to that of Fig. 9 and performing the AND-OR function. Here, however, there is no amplifier 3, while the base of the multiple emitter transistor 10 (Fig. 10) is coupled to a voltage source 16 via a resistor 19.

The multiple emitter transistor 10 is used to perform concurrently logical conversion and amplification. As compared to the above logic circuits 1, this logic circuit 1 of Fig. 10 possesses the highest speed of operation since the input capacitances available from the amplifier 3 are not present in this case. In addition, this logic circuit 3 includes a smaller number of components.

Figure 11 illustrates an embodiment of the logic circuit 1 of the invention performing the AND-OR/AND-OR-lnvert function. In this embodiment, as compared to those of Figs. 8 and 9, a resistor 20 inserted between the output of the emitter follower 1 7 and the base of the multiple emitter transistor 10 is used to create an additional voltage signal passing through the resistor 5.

Figure 12 illustrates the timing diagrams according to which the disclosed method of converting signals is effected with the help of the logic circuit 1 of the invention. The time delay, t, of the logic signal is read along the abscissa, while the amplitude, U, of the source and the logic signal is read along the ordinate. Source signals 21 applied to the inputs of the logic circuit 1 are subject to logical conversion in the logic arrangement 2 with the result that logic signals 22 (logic 1 's or logic O's) are produced. The produced logic signal 22 has a value less than that of the source signal 21 since the logic arrangement 2 introduces a loss due to the internal resistance of its elements. Developed across the internal resistance of the logic arrangement 2, i.e., the load of the amplifier 3, is a voltage signal 23. The latter and the logic signal 22 are subject to voltage summation and the true output of the logic circuit 1 produces an output logic signal 24 equal to the sum of the signals 22 and 23. The timing diagrams show that the disclosed method makes it possible to restore practically without delay the level of the logic signal 22 so as its full amplitude is obtained. The portion 24' is substantially similar to the portion 21 and these portions are separated by the time delay At resulted from the logic arrangement 2.

The portion 24" has a greater steepness, as compared to the source signals 21, due to the fact that the transients from the signals 22, 23 are superimposed. The portion 24" has the edge steepness determined by the parameters of the amplifier 3. Since the latter has a small gain, the edge steepness of the signal 23 is less than that of the source signals 21. As a result, the portion 24"' features a most flat portion of the signal 24.

In practice, the logic arrangements 2 of integrated circuits with bipolar transistors utilize emitter followers and diodes which, when working into even small capacitance-type loads, tend to transmit signals with spikes and the edge steepness of the portion 24"' practically does not differ from that of the source signals. The above described logic circuits are characterized, at small capacitance-type loads, by an extremely small time delay, At, close to the transit time characteristic of the transistors. The output logic signal 24 at the true output 4 of the logic circuit 1 (Fig.1) therefore has a shape practically identical with that of the source signals 21 (Fig. 1 2). Figure 12 also shows a graph 25 for conventional logic circuits, having a time delay exceeding the time delay, At, characteristic of the signal produced by the logic circuit 1.

Figure 1 3 illustrates a series of curves that describe how the output logic signal 24 passes through a chain incorporating logic circuits 1 utilizing emitter followers and diodes and performing the 4AND-40R function.

The proposed method can be used in building logic circuits of AND-OR type which have a considerably higher speed of operation. The signal delay time for such circuits can be reduced to a value close to the transistor transit time.

The logic circuit 1 of the invention operates in the following manner. The source signals 21 (Fig.

12) are applied to the inputs of the logic arrangement 2 (Fig. 1) which converts them into logic signals 22 (Fig. 12). The logic signals 22 are applied to the true output 4 of the logic circuit 1 and to the input of the amplifier 3 (Fig. 1) whose load is the internal resistance of the logic arrangement 2. Developed across the above internal resistance is the voltage signal 23 to which the logic signal 22 (Fig. 12) is added at the true output of the logic circuit 1 (Fig. 1). As a result, the delay time, At, of the output logic signal 24 as related to the source signal 21, is considerably reduced, which finally provides for a higher speed of operation of computers.

The embodiment of the logic circuit 1 of Fig. 1 uses only the simplest logic arrangements, either AND or OR; this is due to the fact that a higher gain of the amplifier 3 cannot be obtained with this circuit.

The embodiment of the logic circuit 1 of Fig. 2 can give a higher gain since the resistor 5 is connected in series with the internal resistance of the logic arrangement 2. Increasing the load resistance of the amplifier 3 results in an increase in the level of the voltage signal 23. This allows for the use of the complex logic arrangements type AND-OR in the logic circuits 1.

The emitter follower 6 coupled to the output of the logic circuit 1 (Fig. 3) causes a decrease in its output impedance so that the delay time, At, tends to rise slowly at the moment that a load is connected to the output of the logic circuit 1.

Other advantages of this embodiment have been described above.

With the amplifier 3 (Figs. 1,2, 3) having a positive feedback at the output of the logic arrangement 2, the frequency characteristic of the latter deteriorates and the time delay resulted from the logic arrangement 2 is increased. This drawback is eliminated in the embodiment of Fig.

4 wherein the amplifier 3 has its complement output coupled to the output of the logic arrangement 2. In this case, the sign of the voltage across the resistor 5, which is added to the logic signal 22 (Fig. 12) is the same as that of the voltage signal 23, which provides for a higher speed of the logic circuit 1. The use of the complement and true outputs of the amplifier 3 (Fig. 5) provides concurrently for the occurrence of both negative and positive feedback in the amplifier 3. When a voltage of positive level is applied to the inputs of the logic arrangement 2, the outputs of the latter provide a signal having a lesser positive level and the amplifier 3 provides for an additional voltage across the resistor 5 which is added to the voltage across the output of the logic arrangement 2.The employment of the amplifier 3 with a positive feedback provides for a reduced loss in the logic arrangement 2.

The operation of the logic circuit 1 shown in Fig. 6 is similar to that described for the embodiments of Figs. 3, 5.

The operation of the logic circuit 1 may be described in more detail with reference to the circuit diagrams of the embodiments of Figs. 1- 6. For example, the logic circuit 1 of Fig. 7 operates in the following manner. When logic 0 (of a positive voltage level) is applied to one or more inputs of the logic circuit 1 (the inputs of the emitter followers 717m) logic 0 appears at the output of the logic circuit 1. The amplifier 3 is driven to conduction and a current from the current source 8 begins to flow through the emitter followers 717m. A greatest absolute level of logic 0 is produced when logic 0 is applied only to one input of the logic circuit 1. In this case, the overall current from the current source 8 flows through one of the emitter followers 717m and a maximal voltage drop is created across its emitter-base junction. When logic 0 is applied to all inputs, the current from the current from the current source 8 is distributed between the transistors. A voltage drop across their emitterbase junctions has a lesser value and a voltage level of a lesser absolute value appears at the output of the logic circuit 1. Therefore, logic 0 at one of the inputs of the logic circuit 1 and logic 1 s at the remaining inputs are responsible for the most unsatisfactory conditions under which logic O at the output of the logic circuit 1 assumes a maximal absolute value of its voltage. When logic 1 is applied to all the inputs of the logic circuit 1 its output provides logic 1.

If no amplifier 3 is available, a current of 18/m must flow through each emitter follower 7, where m is the number of inputs of the logic circuit 1 and 1s is the current produced by the current source 8. In this case, a decrease of AU=?T In m occurs in the voltage drop across the emitter-base junctions where VT is the gain temperature coefficient; the voltage level of logic 1 at the output of the logic circuit 1 must be increased by the same value. As a result, the value of the signal passing through the logic circuit 1 is decreased in proportion to the value of natural logarithm of the number of its inputs.

With the amplifier 3 coupled to the output of the logic circuit 1 and with logic 1 applied, the amplifier 3 is brought to conduction and a current of la=l8(m-1) begins to flow through the latter. As a result, each of the emitter followers 7, with logic 1 applied to it, passes a current of 18. The current through any one of the emitter followers 7t7m does not vary, therefore, in response tovariation of the state of the logic circuit 1 and the signal is transferred to its output without loss.

The logic circuit 1 of Fig. 8 operates as follows.

The current sources 8 provide for the operating mode of the logic arrangement 2 built around the multi emitter transistor 10. Assume that the source signals 21 (Fig. 12) corresponding, for example, to logic l's are applied to one or more inputs of the logic arrangement 2. Since the voltage of logic 1 is of a negative value, the current through the multiple emitter transistor 10 tends to increase; as a result, there exists, at its collectqr-base connection point, a negative voltage whose absolute value is less than that of the source voltage by the value of the loss in the logic arrangement 2 and by the value of the voltage across the emitter-base junction of the multiple emitter transistor 10. That negative voltage is applied to the input of the current switch.The transistor 1 3 is brought to conduction and a current begins to flow through it and through the resistor 5 with the result that a voltage is produced across the latter with the minus sign at the true output of the amplifier 3.

Therefore, a voltage equal to the sum of the voltages at the output of the logic arrangement 2 and across the resistor 5 is provided by the true output of the amplifier 3. The complement output of the current switch provides a voltage corresponding to the voltage of logic 0, which is applied to the complement outputs 9 of the logic circuit 1 via the emitter followers 1 7 and 1 8.

With logic O's applied to all inputs of the logic circuit 1, a voltage corresponding to logic 0 exists in the collector and base of the multiple emitter transistor 10. The parameters of the logic circuit 1 of Fig. 8 are selected so that the voltage across its outputs (with the circuit in the 0 state and with the loss due to the wired AND function taken into consideration) is equal to the voltage corresponding to logic O's at its inputs.

If this condition is difficult to attain for some reason, then an additional transistor (not shown in Fig. 8) is inserted between the true output of the current switch and the common bus 12.

The logic circuit 1 of this embodiment can perform a complex function 4AND-40R/4AND4OR-lnvert at a high operational speed, comprises a small number of components and consumes a low power. However, it cannot realize all the advantages of the disclosed method since there are seveal drawbacks as follows. First, the transfer of the signal from the output of the logic arrangement 2 to the outputs of the logic circuit 1 is effected via the resistor 5 due to the fact that a relatively large stray capacitance is available for the true output of the amplifier 3. Secondly, connection of the amplifier 3 with a positive feedback to the output of the logic arrangement 2 causes a decrease in the speed of operation of the latter.

The logic circuit 1 of Fig. 10 operates in the following manner. When the source signals corresponding to logic 1 are applied to one or more inputs of the logic circuit 1, the converted signal appears at the collector, and with a small time delay at the base of the multiple emitter transistor 10. The current produced by the voltage source 1 6 begins to flow through the resistor 5.

Since the absolute value of the voltage of the voltage source 16 is selected to be equal to a mid level between the levels "0" and "1" of the signals deiivered to the collector of the multiple emitter transistor 10, a voltage is created across the resistor 5 with the minus sign at the base of the multiple emitter transistor 1 0. There exists a negative voltage across the collector of the transistor 10 which is equal to the sum of the voltages across the base of the transistor 10 and across the resistor 5.

When logic 0 is applied to all inputs of the logic circuit 1, the voltage corresponding to logic 0 is developed across the collector and base of the multiple emitter transistor 10. The voltage across the resistor 5 changes its sign, while the voltage corresponding to logic 0, which is developed across the collector of the transistor 10, becomes equal to the sum of the voltages across its base and across the resistor 5.

The embodiment of Fig.10 differs from that of Fig. 8 in that the logic signal 24 (Fig. 12) is applied to the true outputs of the logic circuit 1, bypassing the resistor 5. The latter is operated to perform two functions as follows: first, it creates an additional voltage signal 23 for the recovery of the amplitude of the logic signal 22 and, secondly, it provides for a negative feedback between the collector and base of the multiple emitter transistor 10, thereby resulting in a high speed of operation of the logic circuit 1.

The logic circuit 1 of the embodiment possesses a most high operational speed as compared to other embodiments described. It also offers a compact design and includes a small number of components. However, it has no complement output. Moreover, the voltage levels of logic 1 and logic 0 at the output of the logic circuit 1 vary considerably in response to a variation of the same levels at its input. The logic circuit 1 of the embodiment can therefore be used in building logic chains of a shorter length.

The embodiment of Fig. 9 differs from the embodiment of Fig. 10 in that it comprises an additional cutoff-type amplifier 3 (current switch) having its complement output coupled to the base of the multiple emitter transistor 1 0. The input of the current switch is coupled to the collector of the multiple emitter transistor 10; however, that input can be coupled to the base of the transistor 10 (this variant is not shown in Fig. 9).

When a signal appears at the collector of the multiple emitter transistor 10, it is transferred to the input of the current switch. A voltage developed across the complement output of the current switch and across the resistor 5 is added to a voltage across the base of the transistor 10 with the result that the overall signal is produced by the collector of the transistor 10. The cutofftype amplifier 3 provides for a considerable improvement of the static characteristics of the logic circuit 1.

The embodiment of Fig. 9, as compared to that of Fig. 10, possesses a somewhat lesser operational speed but better static transfer characteristics, which provides for creation of logic chains of a greater length.

The embodiment of Fig. 11 differs from that of Fig. 10 in that it has the complement output 9 whose amplification capability provides for the recovery of the logic signal at the true output 4 of the logic circuit 1.

When the logic circuit 1 is held in the 1 state related to its true output 4, its complement output 9 provides a voltage corresponding to logic 0 and a current from the output of the emitter follower 1 7 begins to flow through the resistors 20, 5 and results in a drop of voltage across the resistor 5 with the minus sign at the collector of the multiple emitter transistor 10.

When the logic circuit 1 is held in the 0 state related to its true output 4, its complement output 9 provides a voltage corresponding to logic 1 and the current through the resistor 5 changes direction. As a result, the resistor 5 provides a voltage whose plus sign is at the collector of the multiple emitter transistor 10.

The described logic circuit 1 possesses operational speed same as in the case of the embodiment of Fig. 9 but also has an ability to additionally perform the NOT function. The resistor 20 provides for a condition in which the complement signal at the output of the emitter follower 1 7 is responsible for the recovery of the logic signal 22 at the true output 4.

The proposed method makes it possible to build LSI circuits having an extremely high speed of operation, since logic circuits of type AND, OR, and AND-OR utilizing bipolar transistors may be given an operational speed of a value close to a theoretical limit determined by the threshold frequency, fT of transistors.

The proposed logic circuits utilize emitter followers and diodes built around multiple emitter transistors to perform functions AND, OR, and AND-OR. As a result, these circuits require low power, comprise small number of components and require small number of insulated packages for mounting in integrated circuits. The proposed logic circuits can perform complex logical functions. All these features provide for the creation of LSI logic circuits possessing an extremely high speed of operation and suitable for use with high performance computers of the fourth generation.

For example, the logic circuit 1 (Fig. 9) performing the 4AND-40R function utilizes transistors having parameters as follows: T=20 ps, CEB=O.3 pF, Rub=250 Ohms, Cos=0.2 pF. The time delay of this circuit amounts to 1 80 ps, which corresponds to less than 100 ps per one gate at a power consumption of 25 mW approx.

(6 mW per one gate). The delay time for the logic circuit 1 of Fig.10 amounts to 120 ps. When loads are connected to the logic circuits 1, the delay time is increased by 50 ps per load.

It is recommended that the disclosed logic circuits be used with LSI circuits, especially with matrix-type ones. The disclosed logic circuits are versatile ones, require small number of logic elements and perform complex logic functions 4AN D-4OR/4AND-40R-lnvert. When they are used to perform simple logical functions, such as 2AND, the excessive area is equal to that occupied by a single transistor.

Claims

1. A method for converting signals comprising logically converting source signals, amplifying logic signals so produced, simultaneously passing the produced logic signals to the output of a respective logic circuit, and subjecting the amplified and the produced logic signals to voltage summation.

2. A logic circuit to realize the method as claimed in claim 1, comprising a logid arrangement having its output coupled to an amplifier which has an output coupled to at least one true output of the logic circuit, the output of the logic arrangement being coupled to the true output of the logic circuit.

3. A logic circuit as claimed in claim 2, wherein the logic arrangement has its output coupled, via a resistor, to the true output of the logic circuit maintained in direct coupling to a true output of the amplifier in order to increase the load resistance of the latter.

4. A logic circuit as claimed in claim 2, wherein the logic arrangement has its output coupled to the true output of the logic circuit via a resistor, the true output of the amplifier being used as the true output of the logic circuit, and a complement output of the amplifier being coupled to the output of the logic arrangement in order to decrease the signal delay time and the voltage loss determined by the latter.

5. A logic circuit as claimed in claim 2, wherein the output of the logic curangement and the complement output of the amplifier are coupled to the true output of the logic circuit via the same resistor in order to provide for the lesser signal delay time for the logic arangement.

6. A logic circuit as claimed in claim 2 or 4, wherein the logic arrangement has its output coupled to the true output of the logic circuit via a resistor and an emitter follower coupled in series in order to decrease the output impedance of the logic circuit, and the true output of the amplifier being coupled to the true output of the logic circuit via the emitter follower.

7. A logic circuit as claimed in claim 6, wherein the logic arrangement comprises a multiple emitter transistor performing logical conversion and forward amplification of the signal, the collector of the multiple emitter transistor being coupled to an output of a current switch which provides for reverse amplification of the signal, and the base of the multiple emitter transistor being coupled to a complement output of the current switch.

8. A logic circuit as claimed in claim 6, wherein the logic arrangment comprises a multiple emitter transistor performing logical conversion and forward amplification of the signal, the base of the multiple emitter transistor being coupled, via a second resistor, to a voltage source, and the collector of the multiple emitter transistor being coupled to the input of the emitter follower.

9. A logic circuit as claimed in claim 6, wherein the amplifier comprises a current switch having its complement output coupled to at least one complement output of the logic circuit via second and third emitter followers connected, in series, the third emitter follower being implemented as a multiple emitter transistor, and a resistor being inserted between the output of the second emitter follower and the output of the logic arrangement to provide for an additional voltage signal passing through said first resistor.

1 0. A method for converting signals and a logic circuit to realize the method substantially as hereinbefore described with reference to the accompanying drawings.