GB2030393A - Analogue to digital converter system - Google Patents

Description

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GB 2 030 393 A 1

SPECIFICATION

Analog to Digital Converter System

This invention is concerned with improvements in or relating to analog to digital converter systems.

Analog signals are generally translated into their digital form by applying them to analog-to- 5

digital converters, hereinafter referred to as A/D's, before any computation or signal processing is performed. The A/D's sample the amplitude of the analog signal at intervals of t0 seconds and produce digital words that represent the closest amplitude to the actual amplitude of each sample that can be attained with the number of bits used by the converter. Any difference between the actual amplitude of the sample of the analog wave and the amplitude represented by a digital word derived from it is 10

known as "digitization noise".

The highest frequency of the analog signal that can be accurately represented by such a sampling process is known as the "Nyquist frequency" and is equal to one-half the sampling frequency. If the analog signal is permitted to include higher frequencies, they can heterodyne with the sampling frequency and its harmonics to produce signals lying below the Nyquist frequency and therefore within 15 the signal frequencies of interest. This is known as "aliasing". In order to prevent this form occurring, it has been customary to pass the analog signal through a low pass filter having a cut-off at or below the Nyquist frequency, but the sharper the cut-off, the greater the phase distortion. For this reason, it would be desirable to avoid the use of an analog filter.

In many applications, interference from power lines, at 50 Hz or 60 Hz, as the case may be, can 20 introduce severe aliasing effects. Notch filters can be used to attenuate these frequencies in the analog signal prior to its application to an A/D converter, but they also introduce troublesome errors in phase.

The present invention provides a system for digitizing an analog signal in such manner as to reduce noise and provide anti-aliasing comprising a continuously integrating A/D converter, and a digital filter coupled to the output of said converter, said digital filter having more than two sections 25 and a gain greater than two.

In accordance with this invention, digitization noise and aliasing can be reduced and high attenuation of the effects of power line frequencies can be attained by utilizing an integrating A/D followed by a digital filter. For reasons that will be explained, significantly better results can be attained by use of an integrating A/D, even though it is inherently more noisy than a sample-and-hold A/D. gQ

There now follows a detailed description which is to be read with reference to the accompanying drawings of a prior art A/D system and of a system according to the present invention; it is to be clearly understood that the system according to the present invention has been selected for description to illustrate the invention by way of example only.

In the accompanying drawings:— 35

Figure 1 is a block diagram of an A/D system of the prior art;

Figure 2 is a block diagram of an A/D system incorporating the invention;

Figure 3 is a simplified diagram of an integrating A/D;

Figure 3A illustrates the operation of the integrating A/D of Figure 3;

Figure 4 is a graph illustrating the operation of the invention; and 40

Figure 5 is used to illustrate the operation of a two-point boxcar filter.

Reference is made to the block diagram of Figure 1 for an understanding of prior art systems for making the A/D conversion. A source 2 provides an analog signal that may include signal frequencies above the maximum frequency of interest, 1/2t0, as well as interference at fifty or sixty cycles, as the case may be, from power lines. The effects of the latter interference may be reduced by a notch filter 4 45 that is coupled to the source 2, and the analog signal may be cut off at the Nyquist frequency of 1/2t0 by a low pass or anti-alias filter 6. The output of the filter 6 is applied to a sample-and-hold A/D converter 8 which samples the analog signal at intervals of t0 seconds and produces digital words respectively representing the amplitudes of the analog signal at these sampling instants. As previously pointed out, an analog filter such as the filter 6 will introduce undesirable phase shifts in the analog 50 signal that is applied to the A/D converter 8 and cause errors in the digital signal it provides.

Figure 2 illustrates an analog-to-digital conversion system embodying this invention. Signals that may include signal components that are higher than the highest signal frequency of interest as well as interference from power lines that may be at 50 Hz or 60 Hz, as the case may be, are supplied from a source of analog signals 10 to an integrating A/D converter 12. The output of the converter 12 is applied 55 to a digital filter 14. Although the particular details of the manner in which the filter 14 carries out the functions required by this invention is not important to this invention, the filter is illustrated as comprising a shift register having sections rv r2, r3, r4, rs, r6, r7, r8, r9, r10, r„,... rn with their outputs respectively connected to multipliers 16, 18, 20, 22,24,26, 28, 30, 32, 34, 36,... Xn. The outputs of the multipliers are coupled via separate leads in a harness 54 to the input of an adder 56. The 60

multiplying factors for each of the multipliers 16—36 are for one particular digital filter that is useful in carrying out this invention, but as will be explained, other digital filters having different numbers of multipliers and respectively different multiplying factors may be used.

2

GB 2 030 393 A 2

Integrating A/D

The integrating A/D of Figure 3 is simplified and impractical values of certain components are assumed in order to facilitate the explanation of the functional characteristics that relate to this invention. An analog signal V,N to be digitized, that is assumed to be +1 volt, is applied via a one-ohm 5 resistor 40 to the inverting input of an operational amplifier Ur Clock #1 supplies pulses that are 5

precisely one second apart to the "set" input of a relay control device 42 which immediately provides a voltage at its "out" terminal so as to energize a relay coil 44 and close a normally open switch s. This applies —10 volts via a one-ohm resistor 46 to the inverting input of the amplifier Ur Its non-inverting input is connected to ground, and a one-farad capacitor C is connected between the inverting input of 10 the amplifier U, and its output, so that the amplifier U, supplies an integrated voltage VINT to the non- 10 inverting input of a comparator U2. The inverting input of the comparator U2 is connected to a voltage —E,/2, E0 being the voltage of one conversion step, as will be explained.

Each tick of the clock #1 starts a faster clock #2, e.g. having a frequency of 1000 Hz, that outputs pulses to the "in" terminal of a counter 48. When the integrated voltage VINTfrom U, reaches 15 —Eg/2, the output of the comparator U2 shifts to a high state. This is applied to one input of an AND 15 gate U3 but it cannot change until the next pulse from clock #2 reaches its other input via a lead 50.

When this occurs, the output of the gate U3 changes state. The output of the gate U3 is applied to the "reset" input of the relay control device 42, causing it to de-energize the relay coil 44 and permitting the switch s to open. The output of the gate U3 is also applied to a "data ready" output that is 20 connected to a process controller 52. Although the connections are not shown, the process controller 20 52 causes the digital words in the stages rr..rn of the shift register to advance to the next stage and the digital word at the output of the counter 48 to be stored in the stage rr The multipliers 16 to Xn then multiply the outputs of the respective sections of the shift register to which they are connected. The outputs of the multipliers 16 to Xn are applied by conductors in the harness 54 to the adder 56. When 25 the addition is complete, a signal indicating that the data has been fetched is applied to the "reset" 25 terminal of the counter 48.

Operation of the Integrating A/D

Reference is now made to the graph of Figure 3A wherein the horizontal line G represents ground potential and the sawtooth line VINT represents the voltage at the output of the amplifier Ur If VIN is +1 30 volt and the switch s is open, the capacitor C charges in a negative direction at the rate of one volt per 30 second, and V,NT does likewise. When the clock #1 ticks, the switch s closes, the capacitor C starts charging in a positive direction at a rate of 9 volts per second, the clock #2 starts ticking, and the counter 48 starts counting the ticks. E0 is the voltage by which VINT increases in a positive direction between ticks. When V,NT reaches — EJ2, the output of the comparator U2 changes state so as to 35 increase the voltage in one of the inputs of the gate U3. However, as previously stated, the gate U3 35

cannot change state until the next tick of the clock #2 is applied to its other input via the lead 50. This could occur anywhere between the dotted lines — E J2 and +E(/2. When it does occur, the clock #2 is stopped and the count then in the counter 48 is used by the counter to output a digital word representing the size of the count and therefore the amplitude of VIN. Until the gate U3 fires, VINT keeps 40 increasing so that it can have a value anywhere between — Ej/2 and +Eq/2. When the gate U3, fires, the 40 capacitor is charged in a negative direction until the one-second clock #1 ticks. It can thus be seen that both ends of the +9-volt/second portion of V,NT can vary so that the number of pulses from clock #2 that are counted by the counter 48 can change. These variations are independent variables but they are related owing to the fact that an increase in the voltage at the upper end of one 9-volt/second portion 45 of VINT causes an increase in the voltage of VINT at the lower end of the next 9-volt/second portion of 45 VINT. These variations are the source of the digitization noise.

Digital Noise

It can be shown that the RMS value of the digitization noise in the system shown in Figure 2 is

Eo

VT2."\|

£{h(L)-h(L-1)|! (1|

50 wherein h(L) is the impulse response of the digital filter 14 and L is digital time. 50

Thus, if the signal from the integrating A/D 12 is applied to a digital filter having one section that multiplies by one and which is described as a filter (1), there is, in effect, no filtering at all. The resulting noise is calculated as follows. The impulse response of such a filter may be described as having the following values at successive digital or sample times... 00100. The expression within the brackets 55 represents the slope at any digital time L because the digital times are uniformly separated. The slopes 55 for such a filter can be expressed as the difference in response at one digital time and the response at the previous time, so that slopes for the filter just described are 0,0, 1, —1,0,0 and the sum of the squares of these slopes is 12+(—1 )2=2, so that expression (1) becomes

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GB 2 030 393 A 3

E0\/2 - E0

2= -41 eo- (2)

/I2 ^6

It can also be shown that the RMS noise of a sample-and-hold A/D followed by a digital filter may be expressed as

Eo

. / £h2(L) (3)

y/T2 \ L

5 If this filter (1), which is no filter at all, is connected to the output of a sample-and-hold A/D, the 5 RMS noise is

E0 E0

. V^= = -29 E0. (4)

y/Tl y/T2

Accordingly, a sample-and-hold A/D is inherently less noisy than an integrating A/D, but if we apply the same calculations to each of the A/D's followed by the digital filters described in the chart below, the 10 results will be as tabulated.

Sample St Hold Integrating o o

15 (1,3,7,13,16,13,7,3,1) 7.7 E0 3.3 E° 15

o o

By way of example, the slopes for the last filter are 1,2,2,3,2,0,0,—2,—3,—2,—2,-1, the sum of the individual squares is 44, and the value of expression (1) for an integrating A/D becomes

En\/44 6-6

20 ^™=Eo =E0:1-9- (5)20

\f\2 3.45

The value of expression (3) for the sample-and-hold A/D when coupled to this same filter becomes

Eo ^

. V33B=E06.4.

\Zl*2

This noise is 3.4 times greater.

The following table indicates the ratio of filter gain to digitization noise, the filter gain being the 25 sum of the multiplications of the separate sections.

(1)

•29 E0

.41 E,

(1,1)

•41 E0

.41 E,

(1,1,1,1,1,1,1,1)

■82 E0

.41 E,

(1,3,7,13,16,13,7,3,1)

7.7 E0

3.3 E,

(1,2,4,7,11,14,16,18,16,14,11,7,4,2,1)

11.6 E0

2.8 E(

(1,3,5,8,10,10,10,8,5,3,1)

6.4 E0

1.9 E,

25

(1)

(1,1)

(1,1,1,1,1,1,1,1)

30 (1,3,7,13,16,13,7,3,1) 30

(1,2,4,7,11,14,16,18,16,14,11,7,4,2,1)

(1,3,5,8,10,10,10,8,5,3,1)

Sample 8- Hold

Integrating

3.45

2.45

E0

*0

4.9

4.9

E0

E0

9.76

19.51

E0

E0

8.31

19.39

E0

E0

11.03

45.71

E0

E0

10

33.68

E0

E0

GB 2 030 393 A

Thus, if digitization noise is a problem and if no filtering is to be done, the sample-and-hold A/D should be used, but if digitization noise is a problem or filtering is to be used, the integrating A/D should be used.

Anti-Aliasing

5 The frequency response of a sample-and-hold A/D is the same for all frequencies as indicated by 5

the horizontal line 58 of Figure 4, i.e., whatever the sampling frequency, the beat with any other frequency has the same amplitude. Therefore, alias frequencies produced by heterodyning between some undesired input frequencies and the sampling frequency of the A/D would lie in the bandwidth of the desired signals. It is for this reason that the low pass filter 6 is used in the prior 10 art system of Figure 1. 10

The frequency response for an integrating A/D can be derived as follows. If an analog circuit has an impulse response of <w_1(t)<w_1(—t+t0) wherein o>_,(t) is a step function having zero value up to t and unity value thereafter, and wherein &>_■,(—■t+t0) is a step function having unity value from —oruntil (t+t0) and zero thereafter, the frequency response is jwtQ (Wtg

2e— sin—

2 2

15 H„= <6> 15

O)

If we apply a signal i(t) to this circuit and integrate over a period of t0, we see that the result is the same as for a continuously integrating A/D such as shown in Figure 3. Accordingly, we can say that such an A/D has a frequency response Hw as given in equation (6). This is illustrated by the line of Figure 4. Examination of equation (6) shows that HM=0 when

2n

20 eo= 20

so that the line goes to zero at this frequency. Another way of realizing that this occurs with an integrating A/D converter such as shown in Figure 3 is to observe that t0 is the sampling interval of one second and the sampling frequency is

2n to

25 If in that particular circuit, VIN has a frequency of one cycle per second, the output will be zero as 25

integration over a complete cycte is zero. The line Hw will also pass through zero at all harmonics of the sampling frequency

2n to

There will not be a great reduction aliasing because most of the frequencies between

30

7T

30

and

2n to have significant amplitude.

The impulse u_,(t)u_1(—t+t0) describes each of the samples SV..S7 of Figure 5. Now, however, if 35 we couple the output of an integrating A/D to a two-point boxcar filter, the output will be impulses 35 St+Sj, S2+S3, S3+S4, etc.. The frequency of sampling is the same, but the samples now have a duration of 2t0 and have an impulse response u.^tju.^—t+2t0). The frequency response H'(w) of the integrating A/D followed by a two-point boxcar the filter is given by the expression

2e—ja»t0 sin(a)t0)

(7)

a)

40 and is illustrated by the line H'(tu) of Figure 4. Such a response will reduce the aliasing because the 40 response to frequencies above

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GB 2 030 393 A 5

is quite low.

71

to

Digital IMoise and Aliasing

It can be seen from the tables of noise figures for the sample-and-hold A/D and the integrating 5 A/D that a two-point boxcar filter does not reduce the noise, although it does improve the gain-to-noise 5 ratio of the filter. If filters other than boxcar filters are used, however, the noise figures are better for the integrating A/D. A good noise figure and anti-aliasing can be attained by using a filter such as the last one in the charts. This is the filter illustrated in Figure 2. Its frequency response is indicated by the dotted line 60. The more stages there are in a filter, the greater is the duration of a sample, and the 10 lower is the frequency of the first zero response. 10

Furthermore, if the dotted line 60 was accurately plotted on a large scale, the response at line frequencies of 50 and 60 Hz would be very low for some distance on either side, so that these frequencies would produce very little interference, even if they varied.

It will be undestood that Figure 2 could have the number of sections and the required multipliers 15 for any filter, e.g., fifteen sections would be required to form the filter having the best gain-to-noise 15 ratio of

45.71

E0

Claims (4)

Claims

1. A system for digitizing an analog signal in such manner as to reduce noise and provide anti-

20 aliasing comprising a continuously integrating A/D converter, and a digital filter coupled to the output 20 of said converter, said digital filter having more than two sections and a gain greater than two.

2. A system according to claim 1, wherein the digital filter 1,2,4,7,11,14,16,18,16,14,11,7,4,2,1 is used.

3. A system according to claim 1 wherein the digital filter 1,3,5,8,10,10,10,8,5,3,1 is used.

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4. A system according to any one of the preceding claims substantially as hereinbefore described 25

with reference to Figures 2,4 and 5 of the accompanying drawings.

Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1980. Published by the Patent Office,

25 Southampton Buildings, London, WC2A 1 AY, from which copies may be obtained.