GB2027300A

GB2027300A - Memory address scanning circuits

Info

Publication number: GB2027300A
Application number: GB7926525A
Authority: GB
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 1978-07-29
Filing date: 1979-07-30
Publication date: 1980-02-13
Also published as: NL191134B; JPS6120952B2; NL191134C; AU532363B2; GB2027300B; AU4931679A; DE2930884C2; JPS5522225A; FR2433807A1; FR2433807B1; NL7905797A; DE2930884A1

Abstract

A memory address scanning circuit includes a clock pulse oscillator 14, an address counter 12 supplied with the output pulse signal from the clock pulse oscillator 14, a memory 1 supplied with the output signal of the address counter 12 so as to control the address of the memory 1, a scanning control circuit 21 connected to the clock pulse oscillator 14 on ON/OFF control the output of the clock pulse oscillator 14, and a further separate scanning control circuit 22 connected to the address counter 12 to shift the count value thereof step by step. Momentarily closing 16 initiates scan, 17 terminates scan. Delay 15 determines the step duration. Operating 16 during scan advances counter 12 by one step and does not reset 12 to a predetermined state as in a prior arrangement. <IMAGE>

Description

SPECIFICATION Memory address scanning circuits This invention relates to memory address scanning circuits.

In a previously proposed FM stereo tuner using a phase locked loop (PLL), a memory circuit, which memorizes a code corresponding to a specific broadcast station is provided.

In the memory circuit, address numbers are given to digital codes corresponding to about six to eight broadcasting stations, and the digital codes are written in and read out from the memory circuit by utilizing their address numbers. In general, in order to select an address number in the memory, an address counter is used, and by supplying a clock pulse signal to-the address counter the count value thereof is changed by one step at a time. When the address counter is scanned by the clock pulse signal, the scanning time, which is a multiple of the period of the clock pulse signal (which is generally required to be 4 to 5 seconds so as to check a selected broadcasting station) by the number of preset broadcasting stations, is necessary. Thus, the time for selecting a broadcasting station becomes unduly long.

According to the present invention there is provided a memory address scanning circuit comprising: a clock pulse oscillator; an address counter supplied with the output pulse of said clock pulse oscillator; memory means supplied with the output signal of said address counter so as to control the address of said memory; scanning control means connected to said clock pulse oscillator to ON/OFF control the output of the clock pulse oscillator; and further separate scanning control means connected to said address counter to shift the count value thereof step by step.

The invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 is a circuit block diagram showing a previously proposed memory address scanning circuit; Figure 2 is a circuit block diagram showing an embodiment of memory address scanning circuits according to the invention; and Figure 3 is a circuit block diagram showing another embodiment of the invention.

In order to assist understanding of the invention, a previously proposed memory address scanning circuit will first be described with reference to Fig. 1.

A memory 1 memorizes data, which may be a received frequency in, for example, a tuner of a stereo receiver, or a set time of a timer associated with the receiver. The memory 1 may, for example comprise a RAM, a ROM, or MNOS transistors. When a read-out control signal from a write-in and read-out (W/R) control circuit 2 and an address control signal from an address register 3 are applied to the memory 1, the date memorized in the memory 1 is transferred to a data register 4, and the content or data thereof is fed to a display circuit 5 and displayed thereon. The address register 3 is supplied with a 3-bit address control signal such as from "000" to "111" from an address counter 12. This address control signal is provided in the following manner.

When an operating switch or memory scan switch 6 is momentarily pushed down, hereinafter referred to as closed, a voltage appearing across a resistpr 8, which is supplied with a voltage from a power supply source 7 such as a dcvoltage source through the switch 6, is applied to an OR-gate circuit 9. The output therefrom is applied to the address counter 1 2 at a reset terminal R thereof as the reset signal, so that the address counter 1 2 is reset and the 3-bit output becomes "000".At the same time, the voltage across the resistor 8, which is provided by closing the memory scan switch 6, is applied to a set terminal S of an R-S flip-flop circuit 1 3. Then, the output is supplied to a clock pulse generator or oscillator 1 4 and the output therefrom is supplied to a pre-settable counter 1 5 at the clock input terminal C. Since the voltage appearing across the resistor 8 on the switch 6 being closed is supplied to an OR-gate circuit 20 at one input terminal and the output is supplied to a reset terminal R of the pre-settable counter 15, this pre-settable counter 1 5 is put into the reset state.The output of the pre-settable counter 1 5 is delayed by a predetermined value, which is determined by the set condition of terminals 1 6 connected thereto, for example, about 4 to 5 seconds (in practice, the delay time is determined by the setting N of an Nscale counter), and the delayed output from the pre-settable counter 1 5 is supplied to a clock input terminal C of the address counter 12. In response to the clock signal, the address counter 1 2 sequentially applies the 3-bit address data signals to the address register 3, and then the address signal is fed from the address register 3 to the memory 1. When the memory scan switch 6 is closed, a control signal is supplied to the W/R control circuit 2.Then, a read-out control signal is applied from the W/R control circuit 2 to the memory 1. In accordance with this operation, the data signals such as the frequency received by the FM stereo receiver, timer setting time and so on, which are written in the memory 1 in well-known manner, are fed through the data register 4 to the display circuit 5 and displayed thereon sequentially.

Next, when a scanning stop switch 1 7 is closed, a voltage appearing across a resistor 19, which is connected in parallel with a power supply source 1 8 such as a voltage source through the closed switch 17, is applied to a reset terminal R of the R-S flip-flop circuit 1 3. Thus, the R-S flip-flop circuit 1 3 is put into the reset state. As a result, the supply of the clock pulse from the clock pulse oscillator 14 to the pre-settable counter 1 5 is stopped.When the 3-bit output from the address counter 1 2 becomes "111" , a reset signal is applied to the reset terminal R of the counter 1 2 through an AND-gate circuit 10 and an OR-gate circuit 9, and hence the counter 1 2 is reset to the initial state of "000''. Also, when the pre-settable counter 1 5 counts up to a predetermined preset value, a reset signal is applied from the output terminal to the reset terminal R through the OR-gate circuit 20. As a result, the presettable counter 1 5 is reset and returns to the initial count state.

With this memory address scanning circuit, every time the memory scanning switch 6 is closed, the output from the address counter 1 2 starts from "000" and the scanning in the memory 1 starts from a first address corresponding to "000", proceeding by one step every 4 to 5 seconds. Thus, the data memo rized in the memory 1 near the first address is read out fairly rapidly, but the data memorized in the memory 1 near the last address cannot be read out rapidly. There is therefore delay in reading out the data memorized in the memory 1, and moreover unnecessary addresses are sequentially scanned.

An embodiment of the invention will now be described with reference to Fig. 2, in which the parts and elements corresponding to those of Fig. 1 are marked with the same references and their detailed description will be omitted.

A memory scan signal generating circuit 21 comprises the operating switch 6, the power source 7 and the resistor 8. When the operating switch 6 serving as the memory scan switch is closed, the voltage appearing across the resistor 8 is applied, as a memory scan signal, to a memory scan control circuit 22 which comprises the R-S flip-flop circuit 13, the clock pulse generator or oscillator 14, the pre-settable counter 15, and OR-gate circuits 20 and 23. When the memory scan signal is applied to the set terminal S of the R-S flipflop circuit 1 3 as the set signal, the output therefrom is supplied to the clock pulse generator 14 as the drive signal. Thus, the clock pulse generator 14 supplies the clock pulse signal to the pre-settable counter 1 5 at the clock input terminal C.The condition of the terminals 1 6 determines whether the pre-settable counter 1 5 functions as an N-scale counter. The clock pulse signal from the clock pulse generator 14 is delayed in the- presettable counter 1 5 by a predetermined amount, for example, 4 to 5 seconds. Prior to the count operation of the pre-settable counter 15, the predetermined voltage is applied to one input terminal of the OR-gate circuit 20 by closing the operating switch 6, and the output from the OR-gate circuit 20 is fed to the reset terminal R of the pre-settable counter 1 5 to put it in the reset state.When the count operation of the pre-settable counter 1 5 is over, the output is fed to the reset terminal R through the OR-gate circuit 20 to put the pre-settable counter 1 5 in the reset state. The output voltage from the memory scan signal generator 21 and the clock pulse signal, which is delayed by the pre-settable counter 15, are both fed to the OR-gate circuit 23 at respective input terminals, and the output thereof is applied to the clock terminal C of the address counter 12. Thus, the address counter 1 2 starts the count operation, and the 3-bit output therefrom is fed to the address register 3 as the address control signal and also to a data register 25.The data from the data register 25 is fed to an address indicator circuit 26 so that the address of the data is displayed on the address indicator 26.

When the count of the address counter 1 2 is filled and the 3-bit output therefrom becomes "111", the reset signal is applied to the reset terminal R of the address counter 1 2 from the output terminal through the ANDcircuit 10. Thus, the address counter 1 2 is put in the reset state.

The address register 3 supplies the address signal to the memory 1 in response to the address control signal for the address counter 12, while the W/R control circuit 2 supplies the read-out control signal to the memory 1.

Thus, the memorized data or contents in the memory 1 are sequentially supplied through the data register 4 to the display circuit 5 so that the frequency or time is displayed on the display circuit 5 as in the example shown in Fig. 1.

With the embodiment of Fig. 2, if the operating switch 6 is closed again during the memory scan operation, the signal is again applied from the memory scan signal generator 21 through the OR-gate circuit 23 to the clock terminal C of the address counter 1 2.

Therefore, the address counter 1 2 counts up.

That is, every time the operating switch 6 is closed, the data or content stored in the memory 1 is read out regardless of the operation of pre-settable counter 15, so that the content stored in the memory 1 can be substantially instantly ascertained.

If it is desired that the display of the data stored in the memory 1 on the display circuit 5 is stopped, it is sufficient that the stop switch 1 7 is closed to apply the voltage appearing across the resistor 1 9 to the reset terminal R of the R-S flip-flop circuit 1 3 to put it in the rest state. That is, if the stop swtich 1 7 is closed, the clock pulse generator 14 stops generation of the clock pulse signal and hence no clock pulse signal is supplied therefrom to the address counter 1 2.

Fig. 3 is a circuit block diagram showing another embodiment of the invention in which references the same as those of Figs. 1 and 2 designate the same parts or elements and the description of which will be omitted.

In the embodiment of Fig. 3, the data from the memory 1 is sequentially fed through the data register 4 to a register 36. The output therefrom is applied to a control output circuit 24, which is formed of the programmable counter of a PLL frequency synthesizer and so on (not shown), and also to the display circuit 5. The register 36 is supplied, in addition to the output from the data register 4, with the output from an UP/DOWN control circuit 37 to be controlled. This UP/DOWN control circuit 37 is in turn controlled by an UP/DOWN control switch 31.

With the embodiment of Fig. 3, when the operating switch or memory scan switch 6 is closed, the voltage appearing across the register 8 is applied to the set terminal S of the R S flip-flop circuit 1 3 as the signal ''1 ''. Thus, the output "1" from the R-S flip-flop circuit 1 3 is applied to the clock pulse generator 1 4.

Thus, this clock pulse generator 1 4 supplies the clock pulse signal to the pre-settable counter 1 5 at the clock input terminal C. The clock pulse signal is delayed in the pre-settable counter 1 5 by the predetermined amount and then fed to the OR-gate circuit 23 at one input terminal as the signal "1 ''. The output "1" from the OR-gate circuit 23 is applied to the address counter 1 2 at the clock input terminal C, and the 3-bit output from the address counter 1 2 is then fed to the address register 3 as the address control signal and also to the data register circuit 25. The output therefrom is applied to the address indicator circuit 26 and hence the address is indicated thereon.

Between a power supply source 32, such as a dcvoltage source, and the UP/DOWN control circuit 37 there is connected an UP/ DOWN control switch 31 for controlling the data of the register 36, and a resistor 33 is connected in parallel with the power supply source 32 through the switch 31. When the switch 31 is closed, the voltage appearing across the resistor 33 is applied to the UP/ DOWN control circuit 37 to a reset terminal R of an R-S flip-flop circuit 34, to the reset terminal R of the R-S flip-flop circuit 1 3 through an OR-gate circuit 35, and to the reset terminal R of the address counter 1 2 through the OR-gate circuit 1 9. Thus, the supply of the clock pulse signal from the memory scan control circuit 22 to the OR-gate circuit 23 is stopped, so that the scanning of the memory 1 is stopped.When the UP/ DOWN control switch 31 is closed, the address indication on the address indicator 26 becomes meaningless. Therefore, at this time the R-S flip-flop circuit 34 is reset and the output is fed to the data register 25, so that the address indicated on the address indicator 26 is reset. When the memory scan switch 6 is closed, the R-S flip-flop circuit 34 is supplied with the set signal at the set input terminal S. Thus, usually the data register 25 is in operative state and the address, which is the output of the address counter 12, is indicated on the address indicator 26.

In the above state, when the memory scan switch 6, forming the operating switch, is closed, similar to the above case, the clock pulse signal from the memory scan control circuit 22 and the memory scan signal from the memory scan signal generator 21 are fed through the OR-gate circuit 23 to the address counter 1 2. Thus, the scanning of the memory 1 is sequentially started from the first address corresponding to the output "000" of the address counter 1 2. If the memory scan switch 6 is again closed, the following address is appointed and hence the data stored in the memory 1 are sequentially displayed on the display circuit 5 rapidly.

With embodiments of the invention, it is not necessary that every time the operating switch is closed, the memory is scanned from the first address at every predetermined time, but when the operating switch is closed several times sequentially, the scan in the memory is shifted to an address next to the address which is now scanned at each closure of the operating switch. Therefore, the memory scan operation can be carried out rapidly and hence data such as the received frequency stored in the memory can be rapidly read out regardless of the position of the address stored in the memory. Accordingly, there is no unnecessary scanning or displaying and hence no unnecessary waste of time.

Moreover, in the embodiment of Fig. 3, the UP/DOWN control switch 31 is pushed down to apply the control input to the UP/DOWN control circuit 37 and selectively to supply the output of the memory 1 or that of the UP/ DOWN control circuit 37 to the register 36, so that embodiments of the invention are suitable for use with, for example, a PLL frequency synthesizer receiver having a programmable frequency divider. In this case, it is easy to select whether the receiving frequency is determined by the UP/DOWN switch or automatically set by the memory scan.

In the above embodiments, the pre-settable counter 1 5 is employed merely in order to delay the clock pulse signal and hence it can be replaced by a circuit such as a mono-stable multivibrator or the like which has the delay function.

Claims

1. A memory address scanning circuit comprising: a clock pulse oscillator; an address counter supplied with the output pulse of said clock pulse oscillator; memory means supplied with the output signal of said address counter so as to control the address of said memory; scanning control means connected to said clock pulse oscillator to ON/OFF control the output of the clock pulse oscillator; and further separate scanning control means connected to said address counter to shift the count value thereof step by step.

2. A circuit according to claim 1 wherein said scanning control means comprises: a dc voltage source; bistable circuit means; a memory scanning switch connected between said dcvoltage source and the input of said bistable circuit means; circuit means for connecting the output of said bistable circuit means to said clock pulse oscillator so as to start the operation of said clock pulse oscillator when said memory scanning switch is closed.

3. A circuit according to to claim 2 wherein said bistable circuit means comprises an R S flip-flop having reset and set terminals, a set terminal of which is connected to said memory scanning switch and the output of which is connected to the input of said clock pulse oscillator.

4. A circuit according to claim 3 further comprising a memory scanning stop switch connected between a further voltage source and the reset terminal of said R-S flipflop.

5. A circuit according to claim 4 further comprising a pre-settable counter connected between the output of said clock pulse oscillator and the input of said address counter so as to count up said address counter after the count value of said pre-settable counter arrives within a predetermined value.

6. A circuit according to claim 2 wherein said further separate scanning control means comprises: an OR-gate circuit having a pair of input terminals and an output terminal; circuit means for connecting one input terminal of said OR-gate circuit to said dovolt- age source through said memory scanning switch; circuit means for connecting the other input terminal of said OR-gate circuit to the output of said clock pulse oscillator; and circuit means for connecting the output terminal of said OR-gate circuit to the input of said address counter.

7. A circuit according to claim 6 further comprising: a data register connected to said address counter; and an address indicator connected to the output of said data register.

8. A circuit according to claim 7 further comprising an AND-gate circuit connected between the input and output of said address counter.

9. A circuit according to claim 6 further comprising: register means having a pair of input terminals, one of which is connected to the output of said memory means; UP/DOWN control means having an output connected to the other input terminal of said register means; and switching means for selectively supplying either one of the outputs of said memory and said UP/DOWN control means to said register means.

1 0. A circuit according to claim 9 further comprising display means connected to said register means so as selectively to indicate frequency data in said memory or said UP/ DOWN control means.

11. A memory address scanning circuit substantially as hereinbefore described with reference to Fig. 2 of the accompanying drawings.

1 2. A memory address scanning circuit subs;antially as hereinbefore described with reference to Fig. 3 of the accompanying drawings.