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GB201719355D0 - Reconfigerable logic circuit - Google Patents

Reconfigerable logic circuit

Info

Publication number
GB201719355D0
GB201719355D0 GBGB1719355.8A GB201719355A GB201719355D0 GB 201719355 D0 GB201719355 D0 GB 201719355D0 GB 201719355 A GB201719355 A GB 201719355A GB 201719355 D0 GB201719355 D0 GB 201719355D0
Authority
GB
United Kingdom
Prior art keywords
reconfigerable
logic circuit
logic
circuit
reconfigerable logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
GBGB1719355.8A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Universita Della Svizzera Italiana
Katholieke Universiteit Leuven
Ecole Polytechnique Federale de Lausanne EPFL
Original Assignee
Universita Della Svizzera Italiana
Katholieke Universiteit Leuven
Ecole Polytechnique Federale de Lausanne EPFL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universita Della Svizzera Italiana, Katholieke Universiteit Leuven, Ecole Polytechnique Federale de Lausanne EPFL filed Critical Universita Della Svizzera Italiana
Priority to GBGB1719355.8A priority Critical patent/GB201719355D0/en
Publication of GB201719355D0 publication Critical patent/GB201719355D0/en
Priority to US16/766,170 priority patent/US11309896B2/en
Priority to EP18804322.8A priority patent/EP3714545B1/en
Priority to PCT/EP2018/081673 priority patent/WO2019101660A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17768—Structural details of configuration resources for security
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Logic Circuits (AREA)
GBGB1719355.8A 2017-11-22 2017-11-22 Reconfigerable logic circuit Ceased GB201719355D0 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GBGB1719355.8A GB201719355D0 (en) 2017-11-22 2017-11-22 Reconfigerable logic circuit
US16/766,170 US11309896B2 (en) 2017-11-22 2018-11-19 Reconfigurable logic circuit
EP18804322.8A EP3714545B1 (en) 2017-11-22 2018-11-19 Reconfigurable logic circuit
PCT/EP2018/081673 WO2019101660A1 (en) 2017-11-22 2018-11-19 Reconfigurable logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB1719355.8A GB201719355D0 (en) 2017-11-22 2017-11-22 Reconfigerable logic circuit

Publications (1)

Publication Number Publication Date
GB201719355D0 true GB201719355D0 (en) 2018-01-03

Family

ID=60805441

Family Applications (1)

Application Number Title Priority Date Filing Date
GBGB1719355.8A Ceased GB201719355D0 (en) 2017-11-22 2017-11-22 Reconfigerable logic circuit

Country Status (4)

Country Link
US (1) US11309896B2 (en)
EP (1) EP3714545B1 (en)
GB (1) GB201719355D0 (en)
WO (1) WO2019101660A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11386204B2 (en) * 2020-09-24 2022-07-12 Intel Corporation Agile reconfigurable approach for real-time replacement of on-chip safety-critical modules

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6140839A (en) * 1998-05-13 2000-10-31 Kaviani; Alireza S. Computational field programmable architecture
US7317331B2 (en) 2004-11-08 2008-01-08 Tabula, Inc. Reconfigurable IC that has sections running at different reconfiguration rates
JP4438000B2 (en) 2005-11-15 2010-03-24 株式会社半導体理工学研究センター Reconfigurable logic block, programmable logic circuit device having reconfigurable logic block, and method for configuring reconfigurable logic block
JP5200949B2 (en) * 2009-01-16 2013-06-05 富士通株式会社 Cryptographic processing device
CN101782893B (en) * 2009-01-21 2014-12-24 上海芯豪微电子有限公司 Reconfigurable data processing platform

Also Published As

Publication number Publication date
EP3714545B1 (en) 2023-01-04
US11309896B2 (en) 2022-04-19
EP3714545A1 (en) 2020-09-30
US20200366294A1 (en) 2020-11-19
WO2019101660A1 (en) 2019-05-31

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Legal Events

Date Code Title Description
AT Applications terminated before publication under section 16(1)