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GB201305400D0 - Cache - Google Patents

Cache

Info

Publication number
GB201305400D0
GB201305400D0 GBGB1305400.2A GB201305400A GB201305400D0 GB 201305400 D0 GB201305400 D0 GB 201305400D0 GB 201305400 A GB201305400 A GB 201305400A GB 201305400 D0 GB201305400 D0 GB 201305400D0
Authority
GB
United Kingdom
Prior art keywords
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
GBGB1305400.2A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lancaster University Business Enterprises Ltd
Original Assignee
Lancaster University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lancaster University filed Critical Lancaster University
Priority to GBGB1305400.2A priority Critical patent/GB201305400D0/en
Publication of GB201305400D0 publication Critical patent/GB201305400D0/en
Priority to PCT/GB2014/050906 priority patent/WO2014155073A1/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90—Details of database functions independent of the retrieved data types
    • G06F16/95—Retrieval from the web
    • G06F16/957—Browsing optimisation, e.g. caching or content distillation
    • G06F16/9574—Browsing optimisation, e.g. caching or content distillation of access to content, e.g. by caching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/50—Network services
    • H04L67/56—Provisioning of proxy services
    • H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Mining & Analysis (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GBGB1305400.2A 2013-03-25 2013-03-25 Cache Ceased GB201305400D0 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GBGB1305400.2A GB201305400D0 (en) 2013-03-25 2013-03-25 Cache
PCT/GB2014/050906 WO2014155073A1 (en) 2013-03-25 2014-03-24 Cache

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB1305400.2A GB201305400D0 (en) 2013-03-25 2013-03-25 Cache

Publications (1)

Publication Number Publication Date
GB201305400D0 true GB201305400D0 (en) 2013-05-08

Family

ID=48326594

Family Applications (1)

Application Number Title Priority Date Filing Date
GBGB1305400.2A Ceased GB201305400D0 (en) 2013-03-25 2013-03-25 Cache

Country Status (2)

Country Link
GB (1) GB201305400D0 (en)
WO (1) WO2014155073A1 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4315312A (en) * 1979-12-19 1982-02-09 Ncr Corporation Cache memory having a variable data block size
EP1095373A2 (en) * 1998-05-15 2001-05-02 Storage Technology Corporation Caching method for data blocks of variable size
US9201677B2 (en) * 2011-05-23 2015-12-01 Intelligent Intellectual Property Holdings 2 Llc Managing data input/output operations

Also Published As

Publication number Publication date
WO2014155073A1 (en) 2014-10-02

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Legal Events

Date Code Title Description
COOA Change in applicant's name or ownership of the application

Owner name: LANCASTER UNIVERSITY BUSINESS ENTERPRISES LTD

Free format text: FORMER OWNER: UNIVERSITY OF LANCASTER

AT Applications terminated before publication under section 16(1)