GB2011669A - Improvements in programmable logic array adders - Google Patents

Abstract

A programmable logic array has a separate two bit decoder 10 for receiving each like order pair of digits Ai, Bi of two n digit binary numbers A0, Ai....An-1 and B0, B1....Bn-1 plus a carry Cin. The decoders 10 generate an output signal called a min term on a different line for each of the four possible combinations AiBi, AiBi, AiBi; and AiBi of the true and complement of each pair. The min terms from the decoders are fed to an array 12 called the product term generator or AND array which generates product terms fp = f0(A0, B0) f1(A1, B1)....fn-1(An-1,Bn-1) fn(Cin> The product terms are fed to a second array 18 called a sum of product term generator or OR array that sums product terms fp. The output lines 21 of the array 18 are connected in pairs to respective ones of a series of latches 22 forming the last in the sequence of logic elements making up the PLA. These latches each perform an Exclusive-OR function to generate a sum bit Si that is an Exclusive-OR of two functions supplied by the OR array to the inputs of the latches to generate a sum S0, S1....Sn-1 plus a carry Cout, for the adder at the output of the PLA. The adder is optimized for a PLA with latches that perform an Exclusive-OR function and is more efficient than known adders embodied in PLAs, in which the output latches perform an AND function.