[go: up one dir, main page]

GB2000651A - Master clock arrangement - Google Patents

Master clock arrangement

Info

Publication number
GB2000651A
GB2000651A GB7828251A GB7828251A GB2000651A GB 2000651 A GB2000651 A GB 2000651A GB 7828251 A GB7828251 A GB 7828251A GB 7828251 A GB7828251 A GB 7828251A GB 2000651 A GB2000651 A GB 2000651A
Authority
GB
United Kingdom
Prior art keywords
phase
locked loop
master oscillator
clock signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7828251A
Other versions
GB2000651B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Standard Electric Corp
Original Assignee
International Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Standard Electric Corp filed Critical International Standard Electric Corp
Publication of GB2000651A publication Critical patent/GB2000651A/en
Application granted granted Critical
Publication of GB2000651B publication Critical patent/GB2000651B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G7/00—Synchronisation
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G9/00—Visual time or date indication means
    • G04G9/0005—Transmission of control signals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1604—Error detection or correction of the data by redundancy in hardware where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The arrangement includes a first, a second and optionally a third phase-locked loop and a single master oscillator, the first phase-locked loop being externally controlled by the master oscillator, the second phase-locked loop being externally controlled via a first change-over contact either by the clock signal provided at the output of the first phase-locked loop or by the master oscillator, and the third phase-locked loop being externally controlled via a second change-over contact either by the clock signal generated at the output of the first phase-locked loop or by the clock signal provided at the output of the second phase-locked loop. The master oscillator may be constituted by one of the phase locked loop oscillators in its free running mode. The arrangement employs a reduced number of master oscillators. <IMAGE>
GB7828251A 1977-06-30 1978-06-29 Master clock arrangement Expired GB2000651B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7707260A NL7707260A (en) 1977-06-30 1977-06-30 MOTHER CLOCK DEVICE.

Publications (2)

Publication Number Publication Date
GB2000651A true GB2000651A (en) 1979-01-10
GB2000651B GB2000651B (en) 1982-05-06

Family

ID=19828807

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7828251A Expired GB2000651B (en) 1977-06-30 1978-06-29 Master clock arrangement

Country Status (8)

Country Link
AU (1) AU3727178A (en)
BE (1) BE868559R (en)
BR (1) BR7804221A (en)
DE (1) DE2828300A1 (en)
ES (1) ES471307A1 (en)
FR (1) FR2396453A1 (en)
GB (1) GB2000651B (en)
NL (1) NL7707260A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0108284A3 (en) * 1982-11-08 1987-04-08 Siemens Aktiengesellschaft Berlin Und Munchen Clock current supply for a multimicrocomputer system in railways safety equipments
EP0365819A3 (en) * 1988-10-25 1991-09-18 International Business Machines Corporation Synchronized fault tolerant clocks for multiprocessor systems
EP0653845A1 (en) * 1993-10-15 1995-05-17 AT&T Corp. A method for synchronizing the reference frequency oscillator to a master oscillator
GB2348555A (en) * 1999-03-30 2000-10-04 Infineon Technologies Corp Clock synchronization

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1159887A (en) * 1966-12-09 1969-07-30 Varian Associates Sequential Frequency Combiner for Frequency Standard Systems
US3402362A (en) * 1966-12-21 1968-09-17 Varian Associates Apparatus for generating a signal having a frequency equal to the average frequency of a plurality of frequency sources
GB1263276A (en) * 1969-04-14 1972-02-09 Marconi Co Ltd Improvements in or relating to clock oscillator arrangements
GB1238582A (en) * 1969-08-15 1971-07-07
GB1253309A (en) * 1969-11-21 1971-11-10 Marconi Co Ltd Improvements in or relating to data processing arrangements
FR2315736A1 (en) * 1975-06-25 1977-01-21 Materiel Telephonique PERIODIC SIGNAL TRANSMISSION SYSTEM

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0108284A3 (en) * 1982-11-08 1987-04-08 Siemens Aktiengesellschaft Berlin Und Munchen Clock current supply for a multimicrocomputer system in railways safety equipments
EP0365819A3 (en) * 1988-10-25 1991-09-18 International Business Machines Corporation Synchronized fault tolerant clocks for multiprocessor systems
EP0653845A1 (en) * 1993-10-15 1995-05-17 AT&T Corp. A method for synchronizing the reference frequency oscillator to a master oscillator
US5469467A (en) * 1993-10-15 1995-11-21 At&T Corp. Method for synchronizing the reference frequency oscillator of a metallic-based microcell to a master oscillator
GB2348555A (en) * 1999-03-30 2000-10-04 Infineon Technologies Corp Clock synchronization
US6188286B1 (en) 1999-03-30 2001-02-13 Infineon Technologies North America Corp. Method and system for synchronizing multiple subsystems using one voltage-controlled oscillator
GB2348555B (en) * 1999-03-30 2003-08-06 Infineon Technologies Corp Clock synchronization

Also Published As

Publication number Publication date
GB2000651B (en) 1982-05-06
FR2396453A1 (en) 1979-01-26
NL7707260A (en) 1979-01-03
DE2828300A1 (en) 1979-01-11
ES471307A1 (en) 1979-01-16
BE868559R (en) 1978-12-29
BR7804221A (en) 1979-05-15
AU3727178A (en) 1980-01-03

Similar Documents

Publication Publication Date Title
AU503854B2 (en) Phase-locked loop phase detector
DE69112477D1 (en) Frequency synthesizer with phase locked loop.
GB2000651A (en) Master clock arrangement
JPS5299054A (en) Phase locked loop circuit
AU2409677A (en) Phase-locked loop arrangements
SE9600726D0 (en) Digital phase locked loop
JPS5335462A (en) Crystal watch
JPS5335415A (en) Phase locked loop synthesizer for transmitter*receiver
JPS53144243A (en) Lock detection circuit for phase synchronous loop in receiver of synthesizer
JPS53135507A (en) Transceiver
JPS52123854A (en) Generator of variable frequency signal
DE3060712D1 (en) Phase-locked oscillator circuit and system for generating a clock signal using this circuit
JPS5360152A (en) Phase synchronous oscillator
JPS5346255A (en) Pll circuit
JPS5355908A (en) Phase locked loop frequency synthesizer
JPS5331942A (en) Phase locked loop frequency synthesizer
JPS5394167A (en) Digital phase synchronous loop
JPS5333090A (en) Phase synchronizing oscillator
JPS5363957A (en) Pll oscillator
CH614344GA3 (en) Monolithically integrated circuit for battery-powered alarm clocks
JPS5357732A (en) Phase lock circuit
JPS5387124A (en) Signal processing unit
JPS53106555A (en) Modulator
JPS5240051A (en) Frequency compound system
JPS52123112A (en) Demodulator automatic phase control unit of multi-direction multiple c ommunication system

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee