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GB2098799B - Multi-level interconnection system for integrated circuits - Google Patents

Multi-level interconnection system for integrated circuits

Info

Publication number
GB2098799B
GB2098799B GB8115463A GB8115463A GB2098799B GB 2098799 B GB2098799 B GB 2098799B GB 8115463 A GB8115463 A GB 8115463A GB 8115463 A GB8115463 A GB 8115463A GB 2098799 B GB2098799 B GB 2098799B
Authority
GB
United Kingdom
Prior art keywords
integrated circuits
interconnection system
level interconnection
level
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB8115463A
Other versions
GB2098799A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to GB8115463A priority Critical patent/GB2098799B/en
Publication of GB2098799A publication Critical patent/GB2098799A/en
Priority to GB08424243A priority patent/GB2144580B/en
Application granted granted Critical
Publication of GB2098799B publication Critical patent/GB2098799B/en
Expired legal-status Critical Current

Links

Classifications

    • H10W20/40—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
GB8115463A 1981-05-20 1981-05-20 Multi-level interconnection system for integrated circuits Expired GB2098799B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB8115463A GB2098799B (en) 1981-05-20 1981-05-20 Multi-level interconnection system for integrated circuits
GB08424243A GB2144580B (en) 1981-05-20 1984-09-25 }interconnection system for integrated circuits}

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8115463A GB2098799B (en) 1981-05-20 1981-05-20 Multi-level interconnection system for integrated circuits

Publications (2)

Publication Number Publication Date
GB2098799A GB2098799A (en) 1982-11-24
GB2098799B true GB2098799B (en) 1985-08-21

Family

ID=10521936

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8115463A Expired GB2098799B (en) 1981-05-20 1981-05-20 Multi-level interconnection system for integrated circuits

Country Status (1)

Country Link
GB (1) GB2098799B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3380548D1 (en) * 1982-03-03 1989-10-12 Fujitsu Ltd A semiconductor memory device
GB8410101D0 (en) * 1984-04-18 1984-05-31 Gen Electric Co Plc Semiconductor devices
EP0349021B1 (en) * 1985-01-30 1994-12-28 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
FR2616966B1 (en) * 1987-06-22 1989-10-27 Thomson Semiconducteurs STRUCTURE OF POWER MOS TRANSISTORS

Also Published As

Publication number Publication date
GB2098799A (en) 1982-11-24

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Effective date: 20010519