GB2096331A - Signal processors - Google Patents

Abstract

A test signal generator for multi- frequency excitation of a system under test is arranged to permit each of a multiplicity of discrete frequency components to be included or omitted as desired (for example, to avoid excitation of the system under test at a resonant frequency within the frequency band of interest) during preselection of the spectrum of the signal. The signal is then generated as an aggregate of the selected components and so as to have a low peak factor. <IMAGE>

Description

SPECIFICATION Signal processors This invention relates to signal processors, and particularly, though not exclusively, to spectrum analysers.

Spectrum analysers are used to identify and measure the frequency components of a signal spectrum for a wide variety of purposes, including the study and testing of the dynamic behaviour of electronic, electrical, mechanical and electromechanical apparatus and systems. The signal spectrum to be analysed may arise spontaneously from operation of the equipment under test, or may be generated by the equipment as the result of the application thereto of a predetermined excitation signal.

One of the simplest excitation signals is a single-frequency sine-wave signal, which is easily specified and generated. However, if thorough testing of the equipment necessitates characterising its behaviour at many different excitation frequencies, involving repetition of the spectral analysis procedure for each frequency of interest, the complete test becomes extremely time-consuming and laborious. Simple superimposition of several signals at different frequencies is likely to yield an excitation signal with an excessive dynamic range for the signal generator, the system under test or both.

Various suggestions have been made to alleviate this problem. Thus, M. R. Schroeder, in a paper entitled 'Synthesis of low peak-factor signals and binary sequences of low auto correlation', IEEE Transactions on Information Theory, pp 85-89, January 1976, suggested a way of synthesising a test signal with a predefined spectrum comprising a multiplicity of evenly-spaced harmonically-related components and also having a low peak-factor (a measure of the extent of variation in amplitude of the signal); this suggestion has been developed by Flower, Knott and Forge in "Application of Schroederphased harmonic signals to practical identification', Measurement and Control, pp 6973, Vol. 11, February 1978.Basically, the peakfactor is limited by appropriate selection of the relative phase-angles of the harmonics making up the test signal spectrum.

According to one aspect of this invention there is provided a signal processor, for example a spectrum analyser, for spectral analysis of the response of a system under test to a predetermined excitation signal, including means for generating said excitation signal as a low peak factor waveform comprising the aggregate of signals at a plurality of preselected discrete frequencies; and means for enabling said discrete frequencies to be preselected from a predetermined multiplicity of such frequencies; whereby a chosen one or more of said frequencies may be omitted from said excitation signal.

With such a processor, the system under test can be excited at many different frequencies simultaneously, thus saving considerably on test duration, but excitation at one or more specific frequencies, corresponding for example to resonant frequencies of the system, can nonetheless optionally be avoided.

A signal processor in accordance with this invention for use in spectral analysis will now be described, by way of example with reference to the accompanying drawings, in which: Figure 1 is a block schematic diagram of the processor; Figure 2 is a block schematic diagram of a signal synthesiser forming part of the processor; and Figure 3 is a flow diagram illustrating the sequence of operation of the synthesiser.

Referring to Figure 1, there is shown the general arrangement of a signal processor 10 operating as a spectrum analyser for the spectral analysis of the response of a system 12 under test to an excitation signal applied thereto.

The excitation signal is generated in the processor 10 by a signal synthesiser 14 and is applied to the system 1 2 (after being shifted by the frequency of an oscillator 1 6 in a heterodyne circuit 18) by a power amplifier 20. The response of the system 12 is applied as an input signal in the processor 10, via an attenuator and preamplifier 22, to an analogue-to-digital converter 24. The attenuator is continuously responsive to an overload output of the ADC 24, and operates to maintain the amplitude of the signal applied to the pre-amplifier at the optimum value for maximum resolution, whilst the signal is actually being received and digitised.To this end, the attenuator monitors the proportion of time for which the signal has exceeded the current range setting during the most recent, constant duration portion of the signal. if the range setting is consistently exceeded, it is increased. Thus the sensitivity of the processor is continuously varied to follow fluctuations in the overall amplitude of the input signal as they occur.

Successive digitised values of the input signal are supplied by the ADC 24 to a discrete Fourier transform circuit 26 which stores them and, when an appropriate number of successive values has been received, calculates the frequency spectrum.

The calculated spectrum is supplied, via a circuit 28 for timing and control of the processor circuitry, to be displayed on a video display/keyboard unit 30. The operation of the heterodyne circuit 18, ADC 24, DFT circuit 26 and unit 30, and the associated operation of the timing and control circuit 28, can be based on conventional known techniques and need not be discussed further here.

In order to reduce the time taken to test the system 12 at many different excitation frequencies, the signal synthesiser 14 is arranged to generate an excitation signal which is the aggregate of a large number (typically 500) of harmonically-related sine waves. However, these sine waves are not merely superimposed at the same initial phase angle (for example, 0 degrees), but instead each has a respective and different phase angle chosen to limit variations in the amplitude of the aggregate signal (that is, to limit the peak factor) and to avoid in particular, sudden large excursions in the signal amplitude which would otherwise be liable to occur. In addition provision is made for any two band, within the overall band of 500 frequencies, to be omitted: the limits and width of each of these bands can be chosen at will.Thus, for example, the advantages of multi-frequency testing can be obtained even when testing a system which has a resonance at a frequency within the overall band of 500 frequencies, by omitting the components of the multi-frequency signal having frequencies at or close to the resonant frequency.

The synthesiser 14 is shown in more detail in Figure 2.

Referring to Figure 2, the timing and control circuit 28 has associated with its a store 32 to which it is connected by a data bus. Another data bus couples the circuit 28 to an arithmetic unit 34 for calculating a value (7rn2/N)/27r/mod 2rrx 1000 where N is the total possible number (here 500) of component sine waves making up the multifrequency signal, and n is the value in a counter 36. The counter 36 has a clock input controlied by the circuit 28.

The value in the counter 36 is also supplied to a modulo-1 000 address adder 38 where it can be added to the current value in the adder 38 in response to a clock signal from the circuit 28. This current value can itself be preset to the value supplied by the arithmetic unit 34, in response to an enable signal from the circuit 28.The current value in the adder 38 is supplied to the address input of a read-only memory (RoM) 40 which contains the data for generating the values of 100 equi-spaced samples of a single cycle of a sine wave, starting at a phase angle of nor/2. The RoM 40 can either contain a full 1000 sample values, or, for example, 250 samples values representing one quadrant of a sine wave plus the logic circuitry required to reverse the addressing sequence and/or invert the sample values to derive the values of the other three quadrants.

Another possibility is to replace the RoM 40 by a circuit for calculating the required values from an appropriate power series approximating the sine function.

Each value supplied by the RoM 40 is fed to a second adder 42, which adds the value to that received from a specific location in a random access memory (RAM) 44, and then suppiies the sum to be stored in the same location. The location is identified by the value supplied on the address bus of the RAM 44 by a counter 46 arranged to be clocked synchronously with the address adder 38. The same value is supplied to the address bus of a RoM 48, and the counter 46 has an output indicating a count of 1000 to the circuit 28.The data busses of both the RAM 44 and the RoM 48 are coupled to the input of a digital-to-analogue converter 50, the output of which is coupled to the heterodyne circuit 1 8. The counters 36 and 46 also have reset inputs; the RoMs 40 and 48, the RAM 44, the adder 42 and the DAC 50 all have enable inputs; and the RAM 44 has a read/write input; all of these inputs are controlled by the circuit 28, but the connections involved have been omitted from Figure 2 for the sake of clarity.

The operation of the circuit of Figure 2 will now be described, with additional reference to the flow diagram of this operation in Figure 3.

Referring to Figure 3, the first step in the procedure is the definition of the power spectrum of the desired multi-frequency signal (100). This step involves the entry into the processor 10, via the keyboard/display unit 30, of the characteristics of the required signal-that is, the minimum and maximum frequency components and the upper and lower frequency limits of any band of frequency components which are to be omitted from the multi-frequency signal. This information is retained by the timing and control unit 28 in the associated store 32.

The unit 28 then examines the information at step 102 to determine whether or not a full 500 components are required. If not, the unit commences the procedure for synthesising the necessary waveform, starting at step 1 04. At this step the counters 36 and 46 are reset to zero and the RAM 44 is cleared. The counter 36 (which in effect counts the number n of components so far accumulated into the waveform, and their relative frequency) is then incremented to advance its count to a value of 1, at step 106. The value of n is compared with that of N at step 108, after which the wave form definition data in the store 32 is checked at step 110 to determine whether the component for the current value of n is required in the multi-frequency signal.

Assuming that it is, the current value generated by the arithmetic unit 34 is pre-set into the address adder 38 at step 112. As noted earlier, and explained in more detail in the aforementioned papers, the peak factor of the multi-frequency signal can be limited by appropriate choice of the relative initial phase angles of the various component sine waves. An approximation to the optimum phase angle for each component is given by 7rn2/N This value can be limited to the range 0 to 2x (that is, one full cycle) by division modulo 2rr, and multiplying the result by 1000 expresses the phase angle value in terms of the position of the sample having that phase angle within the set of 1000 samples in the RoM 40. Thus applying the contents of the adder 38 to the address bus of the RoM 40, and then enabling the RoM 40 at step 114, causes the value of the sine wave for that initial phase angle to appear at one input of the sine adder 42.

At step 11 6, the contents of the RAM 44 location identified on its address bus by the counter 46 (that is, location 0) are output to the other input of the sine adder 42, after which the sine adder 42 sums the values on its inputs, at step 11 8, and stores the result back in the same location of the RAM 44 at step 120.

The address adder 38 and the counter 46 are then clocked at step 122, causing the counter 46 to advance its count by 1, and the address adder 38 to advance its contents by the current count in the counter 36 (in this case, also 1). Thereafter the new count in the counter 46 is checked at step 124 to see if it has reached 2N (1000).

Assuming it has not, the procedure returns to step 114, to access the next sample value at the address in the RoM 40 specified by the new value in the address adder 38.

For the first sine wave component (as described in this illustrative case), this next sample value will be the one stored at the RoM address immediately following the address previously accessed, since the address adder 38 has been incremented by 1. This sample value is thus accumulated into location 1 of the RAM 44.

This procedure continues until each of the 1000 sample values for a complete sine wave cycle has been accumulated into a respective location of the RAM 44.

At that point the test at step 124 will yield a 'yes' result, causing the counter 46 to reset to zero at step 126 before control returns to step 106 to increment the frequency component counter 36, which thus advances (in this case) to a count of 2.

Assuming that the second frequency component is required the arithmetic unit 34 then evaluates a new preset value for the adder 38, corresponding to the initial phase angle for the second frequency component. This preset value identifies the address of the first RoM 40 location to be accessed, and the sine wave sample value at that address is then aggregated with the value already present in location 0 of the RAM 44.

When the counter 46 and the address adder 38 are clocked at step 122, the counter 46 advances its count to 1 as before, but the address adder 38 is incremented by 2, the new count in the counter 36. Thus one sample value in he RoM 40 is skipped, and the following sample value is aggregated into location 1 of the RAM 44.

Similariy alternate following sample values in the RoM 40 are aggregated into successive locations in the RAM 44, so that the complete set of values added into the existing values in the RAM 44 represent a sine wave at twice the frequency of the sine wave represented by those existing values.

When the counter 46 is next reset to zero, the frequency component counter 36 is clocked to a count of 3. Thus, another new preset value for the address adder 38 will be generated by the arithmetic unit 34, and the adder 38 will be incremented in steps of 3, thereby aggregating sample values of a sine wave at three times the frequency of the first sine wave into the RAM 44.

(The adder 38 is arranged to subtract 1000 whenever its incremented contents exceed 1000).

For those sine wave components which are not required, the test at step 110 will yield a 'no' result, causing the procedure to revert immediately to step 106 to clock the counter 36 again. Thus the sample-value aggregation process is skipped for the counter 36 values corresponding to the sine wave components to be omitted.

The procedure continues up to and including a counter 36 value of 500, at which the only sample values taken from the RoM 40 are those at locations 0 and 500, for aggregation into alternate locations of the RAM 44. The need for 1000 samples of the multi-frequency signal (that is, 1000 locations in the RAM 44, and the RoM 40) is set by the choice of a maximum of 500 harmonic frequency components and the constraints of sampling and information theory, which require at least two samples per cycle of the highest-frequency component, and thus 2x500=1000 components of the lowest frequency component.

When the value reaches 501, the test at step 108 causes the operation to advance to step 128, at which the read input of the RAM 44 is enabled, whereafter the counter 46 is reset to zero, at step 130, before the DAC 50 is enabled to step 132.

The counter 46 is then repeatedly cycled from 0 to 999, by steps 134, 136 and 130, the DAC 50 being enabled at the appropriate times by step 1 32, so that the contents of the RAM 44 are cyclically read out to the DAC 50 to generate the aggregate low peak factor multi-frequency waveform represented by the 1000 sample values in the RAM 44.

The heterodyne circuit 1 8 and the oscillator 1 6 are used to shift the baseband multi-frequency waveform to whatever finai frequency band is required.

The cyclic clocking of the counter 46 during generation of the final multi-frequency signal is advantageously synchronised with the measurement sampling procedure of the ADC 24 (Figure 1), so that the multi-sine frequencies are synchronised with the spectral analysis measurement period. Consequently, these frequencies will coincide exactly with the frequencies for which the discrete Fourier transform analysis will generate results, thereby avoiding the need to 'window' the measurements (for example using the Hanning method).

It will be noted that omission of some components from the multi-frequency waveform violates the assumption of a regular spectrum upon which is based the derivation of the quoted initial phase angle formula for a low peak factor.

However, it has been found in practice that this departure from the theoretical constraint results in only a slight, and acceptable, degradation of the peak factor. Furthermore, by avoiding any change in the phase angle formula to compensate for the selective omission of some frequency components, testing can be repeated both with and without those components under otherwise identical conditions, the relative phase angles of those components which are always present remaining unchanged.

Since it is anticipated that the complete multifrequency signal containing a full 500 harmonics will most often be required initially, the 1000 sample values of this particular signal are stored permanently in the RoM 48 (Figure 2). Thus, when no component is to be omitted, tstep 102 of Figure 3) the procedure passes to step 138 to enable the RoM 48 and then directly to the signal output routine as steps 130 to 136, thereby avoiding repetitive and time-wasting synthesis of the same standard multi-frequency signal.

As an altemative to the step-by-step synthesis of the multi-frequency waveform as described above, it is of course possible to use the inverse discrete Fourier transform.

Claims (1)

1. Claims

   1. A signal processor for spectral analysis of the response of a system under test to a predetermined excitation signal, including means for generating said excitation signal as a low peak factor waveform comprising the aggregate of signals at a plurality of preselected discrete frequencies: and means for enabling said discrete frequencies to be preselected from a predetermined multiplicity of such frequencies; whereby a chosen one or more of said frequencies may be omitted from said excitation signal.