GB2082025A - Clock extraction - Google Patents

Abstract

In a PCM digital transmission system, clock is conveyed by a pilot tone sent with the PCM, the pilot tone frequency fp having a preset relation to the PCM bit rate. This PCM + fp signal is applied via a sample and hold circuit (3) to one input of a subtraction circuit (4). The PCM + fp signal is also applied via a narrow pass-band filter 1 to a phase locked loop 2 whose output fo has a preset relation (e.g. one quarter) to the fo, and is a square wave. This is applied to two adaptive coefficient generators, in one case direct and in the other case via a one unit delay (7). Each coefficient generator is also fed with the circuits' PCM output, and includes the sequence of a multiplier (8), integrator (9) and multiplier (10). The outputs of the coefficient generators are summated by a summation circuit (5) whose output is applied to the other input of the subtraction circuit, whose output is thus the PCM minus the pilot tone. <IMAGE>

Description

SPECIFICATION Clock extraction This invention relates to a digital transmission system, one example of which is a pulse code modulation (PCM) system, and to the provision of a clock signal in such a system.

In such systems it is desirable that both ends of the system, together with any repeaters or other nodes between the ends should be maintained in synchronisation. To achieve this, it is known to extract the clock signal at a receiving station from the incoming signal, and this may be done by the use of a pilot tone transmitted with the digital signal. An object of the invention is to provide an improved system of this type.

According to the present invention, there is provided a clock pulse extraction and pilot tone elimination circuit for use in a digital transmission system, in which the digital signal as received is accqmpanied by a pilot tone having a frequency which has a predetermined relation to the digital bit rate, in which the incoming signal is applied to a sample and hold circuit which samples the signal at the transmitted bit rate or an integral multiple thereof, the output from the sample and hold circuit being applied to one input of a subtraction circuit, in which the incoming signal is also applied via a filter tuned to the pilot tone frequency to a phase locked loop whose output is a clock signal at a frequency with a preset relation to the incoming pilot tone frequency, in which the clock signal is applied via a plurality of coefficient generation circuits each of which derives an adaptive coefficient from the digital signal output and the clock signal, the clock signal being applied to the coefficient generation circuits with different time delays (one of which may be zero) and in which the coefficient signals from the coefficient generating circuits are applied to the other input of the subtraction circuit, so that the output of the subtraction circuit, which is the digital output, is the digital signal without the pilot tone.

An embodiment of the invention wiil now be decoded with reference to the accompanying highly simplified block diagram.

In the arrangement shown, the digital signals to be dealt with are PCM, where it is desirable to sample each bit of the signal at or near its mid-point. This sampling is effected under clock signal control, using a clock derived from the signals as received. For this purpose a pilot tone 'p is transmitted in AC form with the digital signals, either in-band or out-band. This pilot tone fp has its frequency a predetermined relation to the digital bit rate.

To extract the clock signal, the incoming signals are applied to clock recovery circuits which include a narrow-band filter 1 whose pass-band is centred on the pilot tone frequency, and a phase-locked loop 2. The loop 2 is fed from the filter 1 and derives therefrom a clock signal fo, whose frequency has a preset relation to the frequency of the pilot tone, and which is a square wave. In the example described the frequency of fp is one quarter that of fo.

This clock signal is applied to a sample and hold circuit 3 and so controls that circuit that it samples each digital bit at its mid-point.

Hence the output of the circuit 3 is the result of sampling the PCM BITS, plus the pilot tone amplitudes at each sampling time. These are applied to a subtraction circuit 4, which could be an operational amplifier arrangement. A signal derived from the pilot tone is applied to the negative input of the circuit 4 to be subtracted from the "composite" signal which reaches the circuit 4. Hence the output from circuit 4 is the received PCM with the pilot tone removed at the sampling times.

The remainder of the circuit shown is used to develop the signal to be subtracted from the "composite" signal, the timing of this signal being fixed by that of the clock signal and its amplitude being regulated in accordance with the amplitude of the PCM signals as produced at the output of the subtraction circuit 4.

The process of generating the signal to be subtracted involves producing a number of adaptive coefficients which are then summated in a summation circuit 5 for application to the negative input of the circuit 4. The number of such coefficients needed depends on the relation between the frequencies fp and fo of the pilot tone and the clock frequency, being given by fo = = n, n being an integer.

2fp Thus is the present case where the pilot tone frequency fp is a quarter of that of the clock fo, it could be seen that these coefficients are needed.

To produce these coefficents the clock frequency fo is applied to a divide by n circuit 6, n being 2 in the present case, from which it is applied to the two coefficient generators, in one case direct and in the other via a unit delay 7, which introduces a delay 1/fro, i.e.

one unit delay for the clock frequency.

The two coefficient generators are similar to each other, so we discuss one of them. This has a first multiplier 8 to one input of which is applied the PCM output while to the other input is applied the output of the circuit 6, i.e.

fo/2. Thus the output of this multiplier is derived both from the clock signal and from the output PCM, and this is applied to an integrator 9, which integrates its input with an integration constant 1/A, where -A is the systems loop gain. Note that this loop gain constant A is relatively high, in the interests of high accuracy. The integrated output is applied to another multiplier 1 0 where it is combined with fo/2. Thus a first coefficient is generated, and this is applied to the summation circuitry 5.

The other coefficient is derived in a similar manner but with a one-unit delay, 1 /fo, defined by the circuit unit 7, but is the result of this summation that is subtracted from the incoming signal at the sampling time for the PCM signal.

Thus the combined effect of the summation of the two coefficients is that we have an adaptive transversal filter which is adjusted by minimisation of the cross-connections between the recovered clock and the sampled data after cancellation.

In the arrangement described, the sampling for clock extraction is effected at the midpoints of the received bits and is thus at the transmitted bit rate. However, it could also be effected at a rate which is an integral muplti ple of the transmitted bit rate.

Claims (3)

1. A clock pulse extraction and pilot tone elimination circuit for use in a digital transmission system, in which the digital signal as received is accompanied by a pilot tone having a frequency which has a pedetermined relation to the digital bit rate, in which the incoming signal is applied to a sample and hold circuit which samples the signal at the transmitted bit rate or an integral multiple thereof, the output from the sample and hold circuit being applied to one input of a subtractor circuit, in which the incoming signal is also applied via a filter tuned to the pilot tone frequency to a phase locked loop whose output is a clock signal at a frequency with a preset relation to the incoming pilot tone frequency, in which the clock signal is applied via a piurality of coefficient generation circuits each of which derives an adaptive coefficient from the digital signal output and the clock signal, the clock signal being applied to the coefficient generation circuits with different time delays (one of which may be zero) and in which the coefficient signals from the coefficient generating circuits are applied to a summation circuit, the summated signals from the summation circuit being applied to the other input of the subtraction circuit, so that the output of the subtraction circuit, which is the digital output, is the digital signal without the pilot tone.

2. A circuit as described in claim 1, and in which each said coefficient generation circuit includes a multiplier circuit to which the digital output and the clock signal are applied, followed by an integrator, followed by another multiplier circuit to which the clock signal is also applied.

3. A clock pulse extractor and pilot tone elimination circuit substantially as described with reference to the accompanying drawing.