GB2066024A - Multiplexed line signalling - Google Patents

Abstract

In a fully digital telecommunication system in which speech in PCM (eight-bit word) form and data are handled, it is also necessary to deal with signalling intelligence. To do this, PCM and data are each assembled into blocks (e.g. 1280 bits for PCM and 240 bits for data) in temporary stores (5, 10) each such block when completed is sent out after a header and a suffix are attached to the block. Signalling intelligence is similarly assembled in a temporary store (13) in which it is assembled into a fixed length block and sent out as soon as a PCM block ends. The receiving arrangements are in effect the inverse of the above in that each received block is routed, under control of a header detector (22) which responds to the information in the header identifying the block, into one of a number of stores (24, 25, 26). The intelligence is sent out from these stores at the appropriate bit rate. Error detection facilities (6, 27) are also provided. <IMAGE>

Description

SPECIFICATION Multiplexed line signalling The present invention relates to a telecommunications system of the type in which intelligence and signalling are conveyed in digital form.

Such a system usually deals with speech in TDM-PCM form, using the standard format of 8bit PCM words conveyed in TDM manner, usually using a 32 channel system. One proposed method of dealing with signalling, especially in a digital local area, involves the use of 1 O-blt PCM words in which the ninth bit is used for synchronisation, PCM signalling, data signalling and telemetry, while the tenth bit is used for conveying data.

Such a system requires complex demultiplexing arrangements at the receiving end to extract ninth bits and the tenth bits. Further the use of a number of bits in a word which is not a power of two is inconvenient in respect of standard integrated circuitry and microprocessors. It is also inconvenient in respect of test gear since much commercial test gear is based on the use of eightbit words, so that the use of ten bit words would call for the development of additional test gear.

An object of the invention is to provide a telecommunication system in which the above disadvantages are minimised or even overcome.

According to the invention there is provided a telecommunication system in which intelligence which includes speech and/or data, with signalling information, is conveyed in digital form, in which the intelligence is transmitted in a block interleaved multiplex form with each said block preceded by a prefix identifying its said block and followed by a suffix conveying further information appropriate to its said block, in which speech and/or data blocks are assembled for transmission and transmitted successively, and in which signalling information is assembled and when a block of such information has been assembled it is interleaved into the intelligence bit stream being transmitted.

An embodiment of the invention will now be described with reference to the accompanying drawings, in which Fig. 1 is a highly simplified block schematic of a telecommunications system embodying the invention, while Fig. 2 shows the receiving equipment in a slightly different format.

The system to be described herein is based on a block-interleaved multiplex arrangement, and involves transmitting blocks of information preceded by a prefix and followed by a suffix. The prefix consists of an eight-bit flag and an eight-bit class of service (COS) word. Note that additional COS words can be added if necessary. Detection of the flag in the receiver gives a means of synchronising the information in the remainder of the block, as will be seen later. The suffix consists of one or two eight-bit words forming an errorcheck facility and an eight-bit flag. Thus a formatted block of PCM data is followed by other blocks or messages in similar formats.

Various transmissions "protocols" can be used, and one preferred protocol which is relatively economical in line time will now be considered. In this, it is assumed that a single block of data or signalling is interposed between each pair-of consecutive PCM blocks. Here we are assuming that voice PCM uses 64 Kb/s, while data signalling use 12 Kb/s, and each is transmitted with a prefix/suffix of 40 bits with a data line transmission rate of 80 Kb/s. Hence we have the formula: (64+12)T + 2x40 T = -~ 20 ms.

80 the period T being the time in which blocks/messages are repeated at regular intervals when the system is operating at full capacity.

Hence we have the number of voice bits in a block as 20 x 64, + 1280,.with the number of data/signalling bits in a block 20 x 12 + 240.

Thus a message length of 240 bits, i.e. 30 eight-bit words, is more than adequate for any conceivable signalling message. When the system operates at maximum capacity, the transmission consists of: PCM-data-PCM-data-PCM-data-PCM-data PCM-data-PCM-Signalling.

When voice intelligence is to be conveyed it must be given priority over other traffic since time integrity is more important. Thus in the absence of other traffic PCM bits are stored until enough have been accumulated to ensure a suitable size of block. This would then be sent until the store is empty. When there is a demand to send other traffic in addition to voice, that other traffic is stored until the transmission of the voice block is complete. The other traffic is then transmitted, but after 240 bits it is interrupted to transmit another block of PCM.

The intelligence transmitted is, on reception, stored and submitted to an appropriate rate change to give an uninterrupted PCM bit stream.

Naturally some delay is introduced to permit manipulation of the bits, but this only amounts to 4 milliseconds.

When a signalling message has to be transmitted, it is given the highest priority after voice traffic, i.e. it is sent in the next slot between voice blocks, giving a maximum delay for such a message of 23.5 milliseconds. If data is the only traffic to be transmitted, it can be stored and sent in longer blocks if this is more convenient. Such a block would be terminated when voice traffic or a signalling message is to be transmitted.

The check block referred to above gives the facility for checking the error rate of all forms of traffic. In the present system the following uses may be made of this facility: (a) Voice traffic -- monitoring for line quality only.

(b) Signalling -- rejection of message and termination of all if an error is detected.

(c) Telemetry -- acknowledgement sent in reverse direction if correctly received.

(d) Data -- automatically request repeat transmission if an error is detected.

Fig. 1 shows in simplified form an embodiment of the invention. Here information relating to the sources of intelligence transmissions, including COS information, is received over an input 1 for reception by the block 2, which assembles message headers for transmission when required, under control of the control block 3, which may include a microprocessor.

PCM traffic, assumed to be voice traffic, arrives over an input 4 to a FIFO (i.e. first-in-first-out) register 5, where it is assembled into blocks of intelligence bits for transmission when sufficient have been assembled When this condition exists, the block receives its header from the header block 2 and its suffix from the error-check assembler 6, all this occurring under the control of the control block 3. The other input 7 to the FIFO register 5 is a clock input.

Data arrives over an input 9 to another FIFO register 10, where it is assembled into blocks of the appropriate size, either of 240 bits or larger if preferred, the other input 11 being a clock input.

This data, which may include telemetry data, is also assembled and sent under the control of the control block 3. Here also the message header and the suffix are supplied trom the header block 2 and the error-check assembler 6, as for a voice block.

Signalling messages arrive over an inpuL 12 to a third FIFO register 13, whose other input 14 is a clock input. Message transmission, as a block of 240 bits, occurs when enough signalling information has been assembled, again with the addition of the header and suffix, under the control of the block 3.

Note that in some cases where traffic is slack, a message block may have to refilled up with stuffing bits.

Message blocks as assembled with headers and suffixes are passed, under control of the block 3, to the line transmitter 15, which sends them out over the line.

At the receiving end, the bit stream arrives at a line receiver 20, with which there is associated a clock recovery circuit 21, which provides clock pulse strains for use by the receiver equipment, which in most respects is functionally the inverse of the sending end equipment. Thus each message header is detected by a header detector 22 with which there is associated a control block 23. This latter may, like the block 3, include a microprocessor.

The header detector 22 recognises from the message header what sort of message is involved, and routes it to the appropriate one of three FIFO registers 24, 25 and 26, dependent on whether it is PCM, data and signalling, or voice signalling respectively. Each message received and its suffix are routed to the error check block 27, and the latter indicates to the control block 23 whether there is an error, whereupon the block 23 uses that indication as appropriate for the message to which it relates. Thus if a message is correct, the control block 23 causes it to be sent from its FIFO over the appropriate output, with the necessary rate change in the case of PCM to give a continuous stream of PCM data.In the event of an error which calls for transmission to the originating end of the line, an indication to this effect is applied over a connection (not shown) to the appropriate transmission equipment (not shown).

Fig. 2 shows the receiving arrangement in slightly different format, with an input 30 from an associated digital switch, and outputs, shown by one line 31, to that digital switch and its central means for PCM, data and signalling. The connections at the left-hand side of Fig. 1 can also come from a digital switch and its control means.

Since all traffic is stored prior to transmission, and is also stored on reception for reconstitution at the correct rate, both ends of the system are relatively simple, consisting basically of FIFO register and a control circuit. Another advantage of the present arrangement is that it does not need a framing pattern since each frame is synchronised by the first flag in a header, and the system remains in synchronisation within the constraints of clock recovery and jitter. Thus there is very little circuitry and no time delay associated with frame acquisition.

To deal with the problem of flag simulation by "non-header" intelligence one method is to use for the flag a code such as 01111110, aiid to insert an 0 into the traffic when six consecutive 1's occur. The extra 0 is removed on reception. This is fairly simple but as the eight-bit structure is destroyed, microprocessor implementation is restricted. A preferred solution is to introduce an extra word to indicate such a "non-flag" occurrence of six consecutive 1 's but this increases pressure on bandwidth.

Claims (13)

1. A telecommunication system in which intelligence which includes speech and/or data, with signalling information, is conveyed in digital form, in which the intelligence is transmitted in a block-interleaved multiplex form with each said block preceded by a prefix identifying its said block and followed by a suffix conveying further information appropriate to its said block, in which speech and/or data blocks are assembled for transmission and transmitted successively, and in which signalling information is assembled and when a block of such information has been assembled it is interleaved into the intelligence bit stream being transmitted.

2. A system as claimed in claim 1, in which speech words and data bits are assembled in respective first-in-first-out (FIFO) registers until a preset number of bits have been assembled, which number may be different for speech and data, and in which the detection that such a block contains enough bits causes it to be sent with its said prefix and suffix.

3. A system as claimed in claim 1 or 2, in which signalling intelligence is assembled into a further FIFO register and is, when assembled, provided with a prefix and a suffix, and sent immediately after the next currently assembling voice block to be sent.

4. A system as claimed in claim 3, and in which on reception the content of the header causes each block to be sent into an appropriate FIFO register, wherefrom it is sent out in suitable format.

5. A system as claimed in claim 1, 2, 3 or 4, and in which the suffix contains error detection information.

6. A system as claimed in claim 1, in which when non-speech intelligence is to be conveyed that intelligence is assembled into message blocks of a predetermined size, and each such block when assembled is interleaved into the bit stream so as to temporarily replace the speech data in the transmitted bit stream.

7. A system as claimed in claim 6, and in which the sizes of the blocks to be transmitted is adjustable in accordance with prevailing traffic conditions.

8. A system as claimed in any one of the preceding claims, and in which the various types of traffic which can be handled are allocated different priorities, with traffic being dealt with in priority order.

9. A system as claimed in any one of the preceding claims, and in which speech is conveyed as eight-bit PCM words.

10. A system as claimed in any one of claims 1 to 8, in which speech is conveyed as plural-bit non-PCM words.

11. A telecommunication system substantially as described with reference to the accompanying drawings.

12. A transmitter arrangement for a system as claimed in any one of claims 1 to 6.

13. A receiver arrangement for a system as claimed in any one of claims 1 to 6.