GB2054204A - Apparatus and method for calibrating a fluid flow control system - Google Patents

Abstract

An apparatus is provided for calibrating a fluid control system 25 which has a flow regulating device responsive to signals from a control circuit 15 which includes a microprocessor having an associated programmable- read-only memory. The apparatus includes a test rig 20 for supplying selected input values of temperature and pressure, and a computer which is responsive to these values to provide flow control signals 37 to the system 25 through the circuit 15. The computer also calculates desired fluid flows from the input values, compares the desired flows with actual values 43 sensed by a device 42 in the rig 20, and adjust the flow control signals until the desired and sensed flows are equal. The input values and the corrected flow control signals are stored in a memory of the computer, and subsequently transferred to a programmable read- only memory which is then inserted in the circuit 15 for use. <IMAGE>

Description

SPECIFICATION Method and apparatus for calibrating a fluid flow control system This invention relates to methods and apparatus for calibrating fluid flow control systems.

It is known to provide fluid flow control systems, for example the fuel control systems for engines, in which a fuel flow regulating valve is wholly or partly under control of a digital computing device which is itself responsive to sensed operating parameters in respect of which flow is to be controlled. In the case of an engine these sensed parameters are, for example, temperatures and pressures associated with the engine.

In order that fluid flow shall correspond accurately to that required for the sensed parameters, notwithstanding tolerances on the hydromechanical and electromechanical components of the fluid control system, it is necessary that the system shall be calibrated.

In the past it has been the practice to perform this calibration by adjustment and trim of the hydromechanical and electromechanical units.

Such a procedure is disadvantageous in that it is time consuming and costly, and may require repeated dismantling of the respective units.

It is an object of the present invention to provide a method and apparatus by means of which calibration of a computer controlled fluid flow control system may be carried out, without incurring the aforementioned disadvantages.

According to one aspect of the invention there is provided a calibration apparatus for a fluid flow control system which includes a flow regulating means and an electrical control circuit having a programmable memory which is responsive to an input parameter for controlling said regulating means, said calibration apparatus comprising means for supplying fluid at a regulated pressure to said control system, means for providing an electrical output signal which is a function of sensed mass flow of said fluid through the control system, means for supplying predetermined values of said input parameter to said programmable memory, computing means responsive to said predetermined values for calculating corresponding desired values of mass flow of said fluid through said flow control system, said computing means also being responsive to differences between said calculated and sensed values of mass flow to program said memory in such a way that response of said memory to said input parameter results in a desired mass flow through said regulating means.

A further aspect of the invention relates to a method of calibrating a fluid flow control system which includes a flow regulating means and an electrical control circuit having a programmable memory which is responsive to an input parameter for controlling said regulating means, said method including the steps of supplying fluid at a regulated pressure to said control system, sensing the mass flow of said fluid through the control system, supplying predetermined values of said input parameter to said memory, calculating, for said predetermined values, corresponding desired values of mass flow of said fluid through said control system, and programming said memory in accordance with differences between said calculated and sensed values, so that response of said memory to said input parameter causes said regulating means to provide a desired mass flow.

An embodiment of the invention will now be described by way of example only and with reference to the accompanying drawings in which Figure 1 is a block diagram of a fuel flow control system for an engine, Figure 2 is a block diagram of a calibration apparatus for parts of the system of Fig. 1, Figure 3 is a block diagram of a fuel flow test rig forming part of the apparatus of Fig.

2, Figure 4 is a block diagram of a digital computer forming part of the apparatus of Fig. 2, Figure 5 is a diagram of an interface unit forming part of the computer of Fig. 4, Figure 6 shows a synchronising circuit forming part of the interface unit of Fig. 5, Figure 7 shows a delay circuit forming part of the test rig of Fig. 3, Figure 8 shows the signal pulses present at several locations of the circuits shown in Figs.

5 and 6, Figure 9 shows the time relationship between clock pulses and address and data signals from a conventional digital computing device, and Figure 10 shows how the relationship shown in Fig. 9 is modified by the delay circuit of Fig. 7.

Fig. 1 shows a fuel flow control system for an engine 10, the flow control system corresponding generally to that described in British patent application 41906/78. The system includes a pump 11, a variable metering device 1 2 which is responsive to an engine intake pressure P1, a servo pressure operated throttle valve 1 3 in series with the device 12, a servo pressure control 14 which is responsive to a pressure difference across the metering device 1 2 and to electrical signals from a control circuit 1 5. The control circuit 1 5 is responsive to engine temperature T, intake pressure P1 and a signal 8 which corresponds to an angle of incidence between the fore and aft axis of the engine 10 and its direction of movement through the surrounding atmosphere.The circuit 1 5 includes a digital microprocessor unit (mpu) 1 6 which is con trolled by a clock 1 7 and which has an associated programmable read-only memory (prom) and which also includes an analog to digital converter for the input signals T, P1, 8 and also a digital to analog converter for providing output signals to the servo pressure control 14.

In the above system the throttle valve 1 3 assumes full control of fuel flow at predetermined levels of 0 and T, subsequent control being in accordance with B, T and P1. In order that fuel flow shall, in these conditions, correspond accurately to that required for the sensed input values, in spite of tolerances in the hydromechanical and electromechanical components of the throttle 1 3 and servo pressure control 14, it is necessary to calibrate the system.

The calibration apparatus shown generally in Fig. 2 includes a fuel flow test rig, indicated generally at 20, and described in more detail with reference to Fig. 3. The rig 20 includes a metering device 12, throttle valve 13, servo pressure control 14 and circuit 1 5 from the fuel system to be calibrated, the programmable read-only memory associated with the microprocessor 1 6 being removed therefrom and being inserted in a computer 21 which is described in more detail with reference to Figs. 4, 5 and 6 and which has an input/output control panel 22 which may include a printer 1 9 for providing a record of calibrations supplied from the computer 21.

As shown in Fig. 3, and as previously indicated, the test rig 20 includes the circuit 1 5 and a flow control 25 which includes the devices 12, 1 3 and 14 previously described.

The flow control 25 is supplied with fuel from a tank 26 by a positive displacement pump 27, by way of an accumulator chamber 39 and a fuel pressure regulator 28 which is controlled by an analog electrical signal on line 29 from the computer 21, and which provides a fuel delivery pressure signal PD on a line 30 to the computer 21. Excess fuel is returned to the tank 26 through a non-return valve 40.

The flow control 25 and circuit 1 5 are responsive to a test air pressure which corresponds to pressure P1 and which is derived from pressure sources 31, 32 by a pressure regulator 33 which is responsive to an analog signal on line 34 from the computer 21. A transducer 35 provides a signal P1t on a line 36 indicative of the magnitude of the test air pressure. The computer 21 provides an analog test signal Ot, corresponding to the aforementioned incidence signal 8, on a line 37 to the circuit 1 5. An air heater 38 provides a temperature signal Tt, corresponding to the aforementioned engine temperature T.

As shown in British Patent 41906/78 the fuel flow control 25 has four outlet passages 41, and in the test rig 20 flow from these passages is combined to pass through a mass flow meter 42 before return to the tank 26.

The flow meter 42 provides an analog output signal on a line 43 to the computer 21. A buffer circuit 44 is interposed in an address and data bus 45 and in a plurality of control lines 46 between the control circuit 1 5 and the computer 21. The buffer circuit 44 includes a delay circuit 47, later to be described with reference to Fig. 7.

As shown in Fig. 4 the computer 21 includes a microprocessor 50, a random access memory (RAM) 51 and a programmable readonly memory (PROM) 52. The signals on lines 29, 34 and 37 are provided from the microprocessor 50 through an analog output circuit 53. The input signals on lines 30, 36 and 43 pass to the microprocessor 50 through an analog input circuit 54.

The RAM 51 is accessible to the microprocessor 1 6 in the circuit 1 5. This access is controlled by an interface unit 55, to be described in more detail with reference to Figs. 5 and 6. The interface unit 55 communicates with the microprocessor 1 6 by way of the bus 45 and with the microprocessor 50 by way of a bus 57. Signals between the control panel 22 and microprocessor 50 pass through an input/output circuit 56 and a programmer circuit 58 for a programmable read-only memory 48 which is to be used in the circuit 1 5. A further RAM 49 is provided for storing calibrated data for later transfer to the memory 48.The microprocessor 50 includes a clock 59 which in the present example has a frequency of 1 MHz and the clock 1 7 in the fuel system control circuit 1 5 has a frequency of .9MHz. It is necessary that the RAM 51 is accessible by only one of the microprocessors 1 6 or 50 at any time. It is also required that the output of the circuit 1 5 shall not be interrupted, whereby access to the RAM 51 by the microprocessor 50 may be permitted only in those intervals in which access by the circuit 1 5 does not occur.

As shown in Figs. 5 and 6 the interface unit 55 includes an address and data multiplexer 60, of the type available from Texas Instruments under the designation SN 74LS1 58N, for controlling flow of addresses and data on the buses 45 and 57 to and from the RAM 51 on a bus 61. Since the circuit 15 is required to operate uninterruptedly, it is arranged that normal operation of the multiplexer 60 is such that the microprocessor 1 6 can obtain access to the RAM 51. The multiplexer 60 is responsive to a signal (L) on a line 62 from a synchronising circuit 63, shown in more detail in Fig. 6. the circuit 63 is responsive to a pulse train (A) on a line 64.

This pulse train (A) is derived from the pulses (A) of the clock 1 7 in the circuit 15, in a manner to be described. The circuit 63 is also responsive to signals (C) and (F) on respective lines 66, 65. Signal (C) is provided by an AND gate 67 when signals on lines 68, 69 indicate that the microprocessor 50 requires to address the RAM 51, and that the required address is valid. If necessary the pulse train (B) on a line 70 from the clock 59 of the microprocessor 50 is applied to the clock terminal of a D-type bistable 71 through an inverter 72. The D terminal of the bistable 71 is responsive to a signal (D) on a line 73 from the synchronising circuit 63. The signal at the Q output of the bistable 71 is applied, together with the (B) signal on line 70, to a NAND gate 74, to provide the signal (F) on the line 65.The arrangement of the bistable 71, inverter 72 and gate 74 is such that when the signal (D) on line 73 is high, the signal (F) on line 65 is the inverse of the signal (B) on line 70 from the clock 59 and that when the signal (D) on line 73 is low the signal (F) on line 65 is maintained high, commencing at the next subsequent low level of the signal (B). This relationship of the signals is seen more clearly in Fig. 8.

As shown in Fig. 6 the synchronising circuit 63 includes 3D-type bistables 80, 81, 82 each of which forms part of a dual unit of type number SN74LS74AN, three monostables 83, 84, 85 each of which forms part of a dual unit of type number SN74LS123N, two AND gates 86, 87, a NAND gate 88 and an inverter 89. The (F) and (C) signals on lines 65, 66 are applied to AND gate 86, whose output is applied to the D input of the bistable 80. The clock input of bistable 80 is supplied with the pulse train (A) on the line 64.Pulses (H) at the 0 output of the bistable 80 are applied to the B input of the monostable 83, to provide, at the Q output of the monostable 83, low-going pulses (J) of a predetermined duration, the pulses (J) being applied to the B input of the monostable 84, to an inverting preset terminal PR of the bistable 81 and to an inverting clear terminal CLR on the bistable 82. The (J) signal at the B input of monostable 84 provides a high pulse (K) of predetermined duration at its Q output, and a low pulse of corresponding duration at the Q output.The pulse (K) is applied on a line 90 to a selector circuit 91 (Fig. 5) whose outputs on lines 1 29 cause the ram 51 to be placed in a state in which data may be entered or obtained, which effective comprises gates which are selectively responsive to the pulse (K) or a low level timing signal on a line 128, to provide signals on lines 1 29 which cause the RAM 51 to be placed in a state in which data may be entered or obtained. The signal on line 128 indicates that a valid address in the RAM 51 has been selected by the microprocessor 16, and this timing signal is extended, in a manner to be described, by the delay circuit 47.

A pulse at the Q of the monostable 84 is applied to the clock terminal CK of the bistable 81, whose D terminal is maintained at a low level. A "reset" pulse can be applied on a line 92 to the clear terminal CLR of the bistable 81, to an inverting preset terminal PR of the bistable 82, and also to one input of the AND gate 87. The output of the AND gate 86 is applied through the inverter 89 to the clock input CK of the bistable 82, whose D input is maintained at a high level. A pulse at the Q output of bistable 82 is applied to the other input of the AND gate 87, whose output is applied to the clear terminal CLR of the bistable 80 and to the CLR terminal of the monostable 85. The B input of the monostable 85 is responsive to the (C) pulses on the line 66. The NAND gate 88 has as inputs the (C) pulse on line 66 and the pulses at the Q output of the monostable 85.The low level output signals on the line 73 from NAND gate 88 provide the (D) pulses on line 73 to the bistable 71 in Fig. 5.

The circuits shown in Figs. 5 and 6 provide pulses as shown in Fig. 8, which indicates the signal sequence by means of which access to the RAM 51 by the microprocessor 50 is initiated during a high-level portion of the pulses (A) and also during a low-level portion of those pulses. It is arranged that the microprocessor 1 6 shall have access to the RAM 51 when the pulses (A) derived from the clock 1 7 are at a low level. The microprocessor 50 may therefore be permitted to have access to the RAM 51 only when the pulses (A) are at a high level. When the signals on lines 68, 69 indicate that a valid address for the RAM 51 has been selected by the microprocessor 50, the signal (C) on line 66 goes high at a time t1, as shown in Fig. 8.The signal (C) generates a high level pulse at the Q output of the monostable 85, causing the signal (D) on line 73 to go low. As previously indicated, the low (D) signal at time t1 at the D input of bistable 71 causes the (F) signal on line 65 to be maintained high, commencing at the next lowgoing part of the pulses (B). At time t2 the next high going part of pulses (A) on line 64 produces the pulse (H), causing the monostable 83 to provide the low-going pulse (J) at its Q output, the pulse (J) persisting until time t4. The low-going pulse (J) also sets the 0 output of the bistable 81 to provide the pulse (L) on line 62 to the multiplexer 60, allowing the address on the bus 57 from the microprocessor 50 to be applied to the RAM 51.The pulse (J) also clears the bistable 82, causing the output signal (N) of AND 87 to become low at a time t3 which is slightly later than time t2, as a result of delays imposed by operation of the bistable 82 and the gate 87.

The low level signal (N) clears the monostable 85, setting the output (D) of the NAND gate high, also at time t3. The monostable 85 will also clear at a preset interval (e.g. 4 microseconds) after time t1, so that the signal (D) will become high after this preset interval, even in the absence of pulses (A) on line 64. The signal (N) is also applied to the clear terminal CLR of bistable 80 and terminates the (H) pulse at time t3. For the duration of the low period of signal (N) the combination of a high portion of pulses (A) and the signal (C) will now result in initiation of signals (H), (J), (L) or (K).

When the signal (J) goes high at time t4, the signal (K) on line 90 goes high until time t5, during which period the microprocessor 50 can obtain access to the ram 51. At time t5 the Q signal from monostable 84 causes the bistable 81 to send the signal (L) low.

The pulse (K) enables access to the ram 51 to be obtained, after the multiplexer 60 has been set by the signal (L) to allow an address and data to be sent to the RAM 51 from the microprocessor 50, and the pulse (K) occurs wholly within a high level of the pulses (A), that is during a time in which access to the RAM 51 by the microprocessor 1 6 is not required. The arrangement thus provides that when the microprocessor 50 requires access to the RAM 51, this access can be obtained during the next high level of the pulses (A) even though the frequency of the clock 1 7 is different from that of the clock 59.

It will, however, be apparent that the apparatus would be equally effective if the clocks 17, 59 have the same frequencies but are of different phase. The apparatus moreover, may also be used for controlling access to stored information by devices having clock pulses of identical frequency and phase.

Since the test rig 50 of Fig. 2 includes the engine fuel control of Fig. 1, and the computer 21 is a separate item of equipment, it is convenient that they are interconnected by electrical cables which provide the bus lines 45 and control lines 46. Information passing between the microprocessor 1 6 and RAM 51 is, as previously indicated, under control of pulses (A) from the clock 1 7 in the microprocessor 1 6. As indicated in Fig. 9, address information 100, which is provided by the microprocessor 1 6 at the beginning of a lowgoing part of the pulse train (A) from the clock 17, does not stabilize for approximately 275 nanoseconds thereafter.Data 101 to be supplied to an indicated address is provided at the beginning of a high going portion of the clock pulse train, but does not stabilize for approximately 225 nanoseconds thereafter.

Both the address information 100 and data 101 persist for a period which cannot be assumed to exceed 20 nanoseconds after the beginning of the next low going part of the pulse train (A).

Delays imposed by a cable length of, for example, 6 metres will be at least 20 nanoseconds, and this delay may vary from line to line of the address and data bus 45. Synchronism, at the computer 21, of the information on the bus 45 and the clock pulses on one of the lines 46 cannot therefore be guaranteed, and this information may have become inaccurate before the end of the pulse (L) which controls its access to the RAM 51.

In the present invention any such lack of synchronism is prevented from affecting transfer of information, by retaining this information on the bus 45 for a predetermined period after the end of the high part of the clock signal (A).

As previously described the clock 1 7 has a frequency of .9 MHz, whereby each half cycle of the pulse train (A) has a duration of approximately 550 nanoseconds. As shown in Fig. 7 the delay circuit 47 includes an inverter 110 responsive to the pulses (A) from the clock 17, these pulses being re-inverted by an inverting buffer 111, and transmitted to the interface unit 55 (Fig. 4) on a line 121 which forms one of the lines 46.The output from the inverter 110 is also applied to the present terminal PR of a D-type bistable 11 2 whose D terminal is maintained at a low potential and whose Q output is connected to one input of a NAND gate 11 3. The other input of the NAND gate 11 3 is connected to the output of the inverter 11 0. The output of the NAND gate 11 3 is connected to one input of each of two NAND gates 114, 11 5. The other input of the NAND gate 11 5 is provided by the output of an inverter 11 6 whose input is provided by a control signal on a line 11 7 which indicates that the microprocessor 1 6 has selected a valid address in the RAM 51.

The other input of the NAND gate 114 is provided through an inverter 11 8 which is supplied by the output of the inverter 11 6. A bistable 11 9 has its preset terminal PR and clear terminal CLR supplied with output signals from the NAND gate 115 and NAND gate 114 respectively. An inverting buffer 1 20 is supplied from the 0 output of the bistable 119, and the output terminal of gate 1 20 communicates with a line 1 28 which forms one of the lines 46.

The signal on line 1 21 is applied to an inverting buffer 1 22 which forms part of the interface unit 55 (Fig. 5), the output of buffer 1 22 providing the (A) signal on the line 64.

Also as shown in Fig. 5 the (A) signal is further modified by successive inverters 123, 124, 1 25 to provide a signal (P) which is returned to the delay circuit 47 by a line 1 26 which forms one of the lines 46. In the circuit 47 the (P) signal is applied, through an inverting buffer 1 27 to the clock terminal of the bistable 112.

Thus as indicated in Fig. 10, a high going part of the pulse train (A) from the clock 1 7 sets the signal (R) at the output Q of the bistable 11 2 to a high level. The high going part of the returned signal (P) is delayed by 100 nanoseconds as a result of its transit through the lines 121, 126, inverters 123, 1 24 and buffers 122, 1 25. The (R) signal is thus set low by the (P) signal approximately 100 nanoseconds after the pulse train (A) from the clock 1 7 goes low.The (R) signal at the Q output of the bistable 11 2 is maintained high for 100 nanoseconds after the (A) pulse train has gone low, and (S) pulse output of NAND gate 11 3 ensures that the "valid address" control signal (T) on line 11 7 is extended for the the additional 100 nanoseconds, and is applied as a timing signal (V) through a line 1 28 to the selector circuit 91 (Fig. 5) to maintain a read/write signal on one of a plurality of control lines 1 29 to the RAM 51. The timing signal (V) on line 128 is also applied to the remainder of the buffer circuit 44 to maintain the data on the bus 45 for an additional 100 nanoseconds.

The address and data from the microprocessor 16 are thus available to the RAM 51 for an additional period which is indicative of the time taken for a pulse from the clock 1 7 to pass to the computer 21 and to be returned to the circuit 47.

As indicated in Fig. 10, both the address and data from the microprocessor 1 6 are available to the RAM 51 during a high level part of the pulse train (A), that is during a low level part of the pulse train (A). The microprocessor 50 may thus have access to the RAM 51 for periods which lie wholly within the high level parts of the pulse train (A) as indicated in Fig. 8. It will be seen from Fig.

10 that extension by 100 nanoseconds, by means of the pulse (S), of the time during which address information and data from the microprocessor 1 6 are present on the bus 45 causes this information and data to be extended into the period of the next subsequent low level part of the pulse train (A). However, as indicated above, new address information initiated by the microprocessor 1 6 at the lowgoing edge of the pulse train (A), does not stabilise for approximately 275 nanoseconds thereafter. Address information and data may thus be retained in the buffer circuit 44 during the stabilisation interval of the microprocessor 16, without prejudice to the next succeeding data and information.

The use of the delay introduced by the lines 121, 1 26 in addition to the fixed delays imposed by the components 122, 123, 1 24, 1 25 and 127, has the effect that any increase in the lengths of the lines 121, 1 26 results in a corresponding increase in the duration of the pulses (S).

Claims (5)

1. A calibration apparatus for fluid flow control system which includes a flow regulating means and an electrical control circuit having a programmable memory which is responsive to an input parameter for controlling said regulating means, said calibration apparatus comprising means for supplying fluid at a regulated pressure to said control system, means for providing an elelctrical output signal which is a function of sensed mass flow of said fluid through the control system, means for generating predetermined values of said input parameter, computing means responsive to said predetermined values for calculating corresponding desired values of mass flow of said fluid through said flow control system, said computing means also being responsive to differences between said calculated and sensed values of mass flow to program said memory in such a way that response of said memory to said input parameter results in a desired mass flow through said regulating means.

2. A calibration apparatus as claimed in claim 1 in which said control circuit comprises a first digital processor and said computing means comprises a second digital processor and a further memory, and which includes means for transferring data between said memories.

3. A calibration apparatus as claim 1 or claim 2 in which said means for generating said predetermined values is responsive to said computing means to generate a series of said values.

4. A method of calibrating a fluid flow control system which includes a flow regulating means and an electrical control circuit having a programmable memory which is responsive to an input parameter for controlling said regulating means, said method including the steps of supplying fluid at a regulated pressure to said control system, sensing the mass flow of said fluid through the control system supplying predetermined values of said input parameter to said control circuit, calculating, for said predetermined values, corresponding desired values of mass flow of said fluid through said control system, and programming said memory in accordance with differences between said calculated and sensed values, to that response of said memory to said input parameter causes said regulating means to provide a desired mass flow.

5. A method of calibrating a fluid flow control system, substantially as hereinbefore described with reference to the accompanying drawings.