GB2050730A - Television horizontal oscillator synchronizing phase detector - Google Patents

Abstract

A phase-lock (AFPC) loop maintains a horizontal oscillator 450 in synchronism with horizontal synchronizing signals in the presence of noise and includes a phase detector (30). The oscillator 450 output signals exhibit successive transitions of first and second polarities. During the vertical synchronizing and equalizing pulse intervals, the frequency of the synchronizing signals applied to the AFPC phase detector is greater (doubled) than during the vertical scanning interval. The increase in frequency may decrease the AFPC loop gain or unsynchronize the loop. This effect is overcome by selectively controlling the coupling of the oscillator signals or of the synchronizing signals to the input terminals of the phase detector, or the coupling of the phase detector output to the oscillator control input, so that the phase detector controls the oscillator in response to synchronizing signals occurring in substantial time coincidence with only first polarity outputs of the coupled oscillator signals. The invention is of particular importance when the television is used with a video tape recorder. <IMAGE>

Description

SPECIFICATION Improved-gain television horizontal phase detector This invention relates to a television horizontal frequency automatic frequency and phase control (AFPC) loop in which the loop gain or speed is improved during the vertical deflection cycle.

Television displays of broadcast television signals are generated by repetitively scanning an electron beam over the surface of a picture tube viewing screen to form a lighted raster area. The beam intensity is modulated by video signals to form images on the screen representative of the picture to be displayed. Conventional television provides a high-speed horizontal scanning in conjunction with a relatively low-speed vertical scanning. The scanning in the vertical and horizontal directions is synchronized with synchronizing signals included in a composite video signal with the video signal to be displayed.

The synchronizing signals are extracted from the composite video, and the synchronizing signals thus extracted are used to synchronize the vertical and horizontal-direction scanning apparatus.

The synchronizing signals are extracted from the composite video by use of synchronizing signal separator circuits. A sync separator for separating the horizontal synchronizing signal from the composite video includes a differentiating circuit and a threshold circuit. The dfflerentiating circuit selectively couples signals at and above the horizontal synchronizing frequency to the threshold circuit. The threshold circuit responds to the differentiated synchronizing-signal portions of the composite video to produce a sequence of constant-width pulses representing horizontal frequency, synchronizing portions of the composite video.

The vertical synchronizing signals contained in the composite video are high-amplitude pulses having low-frequency components. The vertical synchronizing signal proper has a duration of three horizontal lines. In order to maintain the flow of horizontal synchronizing information during the vertical synchronizing interval, the vertical synchronizing pulse includes serrations by which the horizontal oscillator may be synchronized. In the NTSC television system, vertical scanning of an image is accomplished during two successive field intervals, the horizontal scanning lines of which are interlaced. Interlacing requires that the vertical oscillator timing be maintained in an exact relationship with the horizontal frequency.In order to help the vertical sync detector to maintain exact timing in extracting the vertical synchronizing pulses, equalizing pulses are provided in the composite video during a period of three horizontal lines preceding and following the vertical synchronizing intervals. The equalizing pulses recur at twice the rate of the horizontal synchronizing pulses.

In television systems in which the composite video signals are modulated onto a carrier and broadcast, many of the television receivers are in areas far from the transmitting station, where a weak signal can be expected. Due to the presence of unavoidable thermal noise, and also due to various forms of interference signals which may occur in the vicinity of the receiver, it may be expected that the compositie video as received and the synchronizing signals derived therefrom will be intermingled with electrical noise. This electrical noise is manifested as random variation of the desired signal amplitude, and can severely disturb the operation of the display device.

Commonly, noisy synchronizing causes "rolling" or "tearing" of the image displayed on the raster.

As transmitted, the synchronizing signal pulses recur at a rate which is carefully controlled and extremely stable. Since the presence of noise obscures the synchronizing signals in a random manner, it has become common practice to obtain synchronization of the horizontal deflection circuit with the horizontal synchronizing pulse signal by the use of an oscillator, the free-running frequency of which is near the horizontal scanning frequency, and the exact frequency and phase of which is controlled in an indirect manner by a phase-iock loop (PLL) known as an AFPC (automatic frequency and phase control loop) to equal the synchronizing signal frequency and phase. Thus, when any one synchronizing pulse is obscured by noise, the rate of the oscillator remains substantially unchanged, and the deflection circuits continue to receive regular deflection control pulses.

In a PLL, a phase detector compares the output of the horizontal oscillator with the horizontal synchronizing pulses from the sync separator and produces a pulsating control signal representative of the frequency and phase difference between the two. The control signal is then filtered and applied to the oscillator in such a manner as to maintain the oscillator in frequency and phase synchronism with the average frequency and phase of the received synchronizing pulses.

However, periods of loss of horizontal sync pulses prevent the loop from responding to changes in phase between the deflection and video signals. it is desirable to make use of all horizontal sync pulses not masked by noise, including those in the vertical sync and equalizing intervals.

Since the PLL is a feedback system, there is an undesirable residual phase error between the oscillator signal and the synchronizing signal. High loop gain is desirable in order to minimize error, but, the loop then becomes more responsive to perturbing noise. This can be offset by reducing the closed-loop bandwidth of the PLL, which may undesirably reduce transient response time. Thus, a compromise between loop gain and bandwidth is often necessary.

With the advent of integrated circuits for lowpower signal processing in television devices, it has become convenient in a PLL to -compare the horizontal synchronizing signals from the sync separator with a square wave as produced by the controlled horizontal oscillator rather than with a sawtooth signal. During the synchronizing pulse interval, the PLL phase detector gates a first current source which charges a storage capacitor in a first polarity when the oscillator square wave output is high, and which turns off the first current source and turns on a second current source poled to discharge the capacitor when the oscillator output is low. Thus, when the transition time of the square-wave oscillator output is centered on the synchronizing pulse, the charging and discharging effects are equal and the net capacitor voltage does not change.This maintains the oscillator frequency constant.

With the described type of phase detector, the phase detector gain and therefore the loop gain of the PLL may decrease during the equalizing and vertical synchronizing pulse intervals. The phase detector gain drops because during the vertical synchronizing and equalizing pulse intervals the sync signal occurs twice during each VCO output square wave, and thus the phase detector compares during both the rise and fall times of the square wave. Changes in oscillator phase which change the phase detector output during one half of the square wave result in an equal and opposite change during tha other half of the square wave and no net change in output results. Thus the oscillator may drift in an uncontroiled manner during the vertical synchronizing and equalizing pulse intervals.

Such a decrease in gain of the PLL may be disadvantageous when rapid slewing of the horizontal oscillator frequency or phase is required during the vertical blanking interval. This may be the case, for example, when the television receiver is to be used to display information which has been recorded on a home-type video tape recorder. Such tape recorders often have a plurality of reproduction heads, each of which is mechanically scanned across the tape. In one common scheme, two heads are used, which alternately scan the tape for a duration equal to that of a vertical field. In order to avoid loss of, or breaks in, the displayed information, scanning of the succeeding field is commenced by the second head substantially concurrently with the end of scanning in the first head.However, slight differences in tape tension or in the dimensions of the mechanical tape transport acting on the tape for playback compared with the tension and dimensions when the tape was recorded results in differences in the time between succeeding horizontal synchronizing pulses in the information as recorded as compared with playback, especially during the switchover between heads. This results in a discontinuity or step change in the phase of the horizontal synchronizing pulses available for synchronizing the horizontal oscillator, which step normally occurs about five horizontal lines before the end of a vertical scanning interval and the beginning of the vertical blanking interval.A high oscillator slew rate during the vertical blanking interval is necessary to conform the horizontal oscillator phase to the synchronizing signal phase after the step change, and this conformance must be complete before scanning begins for the next succeeding field in order to correctly reproduce the desired image. A decrease in PLL gain during the equalizing and vertical synchronizing pulse intervals as may be occasioned by the presence of equalizing pulses may prevent rapid slewing of the horizontal oscillator and therefore prevent accomodation of such a step change. This may result in an apparent bending or tearing of vertical lines in the displayed image at the top of the raster.

It is known from U.S. Patent 3,846,584 issued Nov. 5, 1974 to Itoh to disconnect the loop filter from the PLL in order to increase gain for an interval immediately following the appearance of vertical sync signal, but a decrease in phase detector gain during the equalizing and vertical synchronizing pulse intervals as may be occasioned by the presence of equalizing pulses or serrations may nevertheless prevent rapid slewing of the horizontal oscillator and may therefore result in the above-mentioned apparent bending or tearing of vertical lines in the displayed image. Even when the synchronizing signals associated with the video to be displayed do not have a step change in phase, the decrease in PLL gain during the equalizing and vertical synchrdnizing pulse intervals may be disadvantageous.This may occur, for example, in those cases in which the first and second gated current sources in the described type of phase detector have unequal amplitudes. Unequal charge and discharge currents results in a progressive change in the horizontal oscillator control signal and may result in driving the oscillator off-frequency during the equalizing and vertical synchronizing intervals in which the PLL gain is low. If the loop filter is disconnected during this interval as suggested by Itoh, the oscillator may drift off-frequency very quickly, and there may then be insufficient time remaining before the beginning of the next following scanning interval for correction, resulting in an apparent bending or tearing of vertical lines in the displayed image.

In a preferred embodiment a television phase lock loop apparatus for the horizontal oscillator of a television receiver, includes a controllable oscillator having an output terminal at which oscillator signals exhibiting successive transitions of first and second polarities are generated and a control input terminal. A phase detector has a first input terminal coupled to the output terminal of the controllable oscillator, a second input terminal, and an output terminal coupled to the control input terminal of the controllable oscillator. The television receiver includes a source of horizontal synchronizing signals including horizontal-rate pulses and intermediate pulses occurring in the interval between the horizontal rate pulses. The intermediate pulses occur during a portion of the vertical blanking interval. A phase-lock loop responsive to the synchronizing signals for locking the frequency and controlling the phase of said oscillator includes a switch for selectively controlling the coupling of one of the oscillator or the synchronizing signals to the input terminals of the phase detector such that the synchronizing signals occur in substantial time coincidence with only the first polarity transitions of the coupled oscillator signals.

In the Drawings: FIGURE 1 illustrates in block and schematic diagram form a television receiver including an AFPC loop according to the prior art; FIGURES 2 and 3 illustrate as amplitude-time diagrams certain voltage and current waveforms illustrating the operation of the arrangement of FIGURE 1; FIGURE 4a illustrates in block and schematic diagram form another television receiver including an AFPC loop according to the prior art; FIGURE 4b illustrates in schematic diagram form a switchable loop filter time constant, suitable for use in the AFPC loop of FIGURE 4a; FIGURE 5 is a block diagram of a television receiver embodying the principles of the invention; FIGURE 6 is a schematic diagram of a portion of the arrangement of FIGURE 5; FIGURE 7 illustrates as amplitude-time plots certain voltage and current waveforms occurring in the arrangement of FIGURE 5 during operation;; FIGURE 8 illustrates in block and schematic diagram form another television receiver constructed in accordance with the principles of the invention; FIGURE 9 illustrates as amplitude-time plots a timing diagram illustrating the operation of the arrangement of FIGURE 8; and FIGURE 10 illustrates another alternative embodiment of the invention.

In FIGURE 1, a television receiver includes an antenna 10 for receiving broadcast television signals. Antenna 10 is coupled to a tuner, intermediate-frequency (sF) amplified and video detector illustrated together as a block 12, for producing composite video which is coupled by way of a conductor I to appropriate luminance and chrominance processing circuits illustrated as a block 14 and also to a synchronizing signal separator illustrated as a block 1 6. The luminance and chrominance information generated by processing circuits 14 is coupled to a kinescope 20 by means of appropriate luminance and chrominance drive circuits illustrated as a block 18.

Synchronizing signal separator 1 6 separates the vertical synchronizing signals from the composite video and couples them by way of a conductor V to a vertical deflection circuit illustrated as a block 28. Deflection circuit 28 produces recurreni sawtooth current drive signals which are applied in synchronism with the vertical synchronizing signals to vertical deflection windings 29 associated with kinescope 20.

Synchronizing signal separator 1 6 also separates the horizontal synchronizing signals from the composite video and applies them by way of a conductor A to a phase detector designated generally as 30. Phase detector 30 includes first and second AND gates 32 and 34, respectively, each having an input coupled to conductor A. A phase detector integrating or filter capacitor 41 has one end connected to ground and receives charging current from B+ through a gated current source 42. A second gated current source 44 is coupled in parallel with capacitor 40 for discharging the capacitor. Gated current source 42 is controlled by the output of AND gate 32 and gated current source 44 is controlled by the output of AND gate 34. The voltage across capacitor 40 is the output of phase comparator 30.This output voltage is coupled to a frequencycontrollable horizontal oscillator (VCO) illustrated as a block 50. Oscillator 50 produces output signals which are coupled to the input of a horizontal deflection circuit 51. Deflection circuit 51 produces horizontal deflection current under the control of oscillator 50. The deflection current is coupled to horizontal deflection windings illustrated as 58 associated with kinescope 20.

Horizontal deflection circuit 51 also drives a high voltage generator illustrated as 56 which produces a direct ultor voltage for energizing the kinescope.

The output of horizontal oscillator 50 is also applied by way of a conductor B to a second input of AND gate 34 and, by way of an inverter 36, to a second input of AND gate 32.

In operation, the tuner of FIGURE 1 selects a broadcast carrier signal, mixes it to an IF frequency, amplifies and detects it to produce a composite video signal representative of the information in the selected broadcast signal. The color and luminance portions of the composite video are coupled to the control elements of the kinescope by processing circuits 14 and drive circuits 18 as mentioned and the vertical synchronizing signals separated by separator 1 6 control the vertical deflection.

An amplitude-time plot of the composite video on conductor I near the vertical blanking interval is illustrated in FIGURE 2. The vertical blanking interval extends from time TO at which the vertical blanking interval begins to time T8, and has a duration approximately equal to that of 1 9 horizontal lines. The vertical scanning interval before time TO and extending from time T8 to the next following time TO contains video information and horizontal synchronizing signals. The horizontal synchronizing signals such as pulses 220, 221 are separated by intervals such as 230 which contain the video information at a lower amplitude than the synchronizing pulses.

The vertical synchronizing information in the composite video illustrated in FIGURE 2 occurs in the interval between times T2 and T4 of the vertical blanking interval. During interval T2-T4, six wide pulses separated by five serrations allow the RC integrator portion (not shown) of the synchronizing signal separator to charge to a threshold. Because of the half-horizontal line difference in the starting time of each successive vertical field, the horizontal synchronizing pulses such as 220, 221 if carried through the interval TO--T2 would cause the RC integrator to assume slightly different charges in successive fields at time T2 at which the synchronizing interval begins.This might cause recurrent changes in the triggering of the synchronizing signal separator threshold device and might result in erratic interlace. In order to avoid this problem, the composite video in time TOT2 includes equalizing pulses such as 240, which recur at twice the horizontal rate. Thus, there is no difference in the interval TOT2 preceding the vertical synchronizing interval between an even field and an odd field, and the charge on the RC integrator at time T2 tends to remain constant.

Because successive fields have a one-half line difference in vertical sync phasing, interlace also requires that the serrations occur at twice the H frequency to maintain the phasing of the integrator output constant relative to the start of the vertical sync pulses.

In operation during the vertical scanning interval, sync signal separator 16 produces on conductor A synchronizing signal pulses illustrated by the solid-line waveform in FIGURE 3a. Pulse 300 has a duration from time TO to time T2 of FIGURE 3, which substantially coincides with the time of a horizontal pulse such as pulse 220 illustrated in FIGURE 2. The PLL responds to the pulses, and oscillator 50 produces at its output a square wave illustrated as 310 in Figure 3b, which square wave has a transition centred art a rime T1 between times TO and T2. AND gates 32 and 34 are enabled to respond to the signals at their second inputs when a sync pulse such as 300 is produced on conductor A. Thus, gates 32 and 34 are enabled for conduction in the interval TO-T2 of FIGURE 3.In the interval TO-T1 when square wave 310 is low, inverter 36 applies a high signal to the second input of gate 32, producing at the output of gate 32 a current source gating pulse illustrated as 320 in FIGURE 3c. Current source 42 responds with a current pulse which charges capacitor 40, which current pulse may also be illustrated by pulse 320.

n the interval T1--T2, both sync pulse 300 and square wave 310 are high, which enables gate 34 to produce a gating pulse illustrated as 338 in FIGURE 3d. With square wave 310 high, inverter 36 drives an input of gate 32 low and gating pulse 320 produced by AND gate 32 ends.

Thus, in the interval T1-T2 charging current source 42 does not conduct and discharging current source 44 conducts. So long as time T1 at which the transition of square wave 310 occurs remains centered in the interval TO-T2, gating pulses 320 and 330 will have equal duration, and gates 32 and 34 conduct alternately. If current sources 42 and 44 have equal magnitude, zero net change in charge on capacitor 40 results.

If, as illustrated in the interval T6-T9, the phase of oscillator square wave output signal 310 deviates, the transition of the square wave occurs at a time T7 which is not centered in the interval T6-T9. This results in charging current pulse 320 and discharging current pulse 330 having unequal durations, and will cause a net change in the capacitor voltage, whereby the frequency and phase of horizontal oscillator 50 are slewed in a feedback manner to maintain the transition centered on the synchronizing pulse.

During the vertical synchronizing and equalizing pulse intervals TO-T6 as illustrated in FIGURE 2, the equalizing pulses and the serrations at twice the horizontal rate cause a double-rate response of synchronizing signal separator 1 6. Thus, in addition to pulses 300, 304 as illustrated in FIGURE 3a, additional intermediate pulses such as 302 are produced on conductor A. The effect of an additional pulse 302 in the interval T3-T5 is to enable gates 32 and 34 for conduction. Square wave 310 may have a transition in this interval, as illustrated by FIGURE 3b. In the interval T3-T4, pulse 302 and square wave 310 enable discharging current source 44 to produce a further discharging current illustrated as 332, and in the interval T4-T5 produce a gating pulse such as 322 which enables charging current source 42.A change in phase of the oscillator waveform illustrated in FIGURE 3b would produce a change in duration of pulse 322 equal in size and opposite in polarity to the change in duration of pulse 320.

This is also true of pulse 332 relative to pulse 330.

The result of this additional response during the vertical synchronizing and equalizing pulse intervals is to render the phase detector relatively unresponsive to changes in phase.

As pointed out above, FIGURE 4a illustrates in block diagram form another prior art television receiver similar to that of FIGURE 1. Those elements of FIGURE 4a corresponding to elements of FIGURE 1 are designated by the same reference numerals.

In FIGURE 4a synchronizing signal separator 16 separates the vertical synchronizing signals from the composite video and couples them by way of a conductor V to the logic portion 22 of a vertical count-down arrangement designated generally as 24, which also includes a divide-by-525 counter 26. Vertical count-down arrangement 24 produces counter-derived vertical drive signals which are synchronized by the vertical synchronizing pulses accepted as such by logic circuit 22. Such count-down arrangements are known and are described for example in U.S. Pt.

3,688,037 issued Aug. 29, 1972 to Ipri and in U.S. Pt. 3,878,335 issued Apr. 15, 1975 to Balaban.

Oscillator 50 produces output signals at a high frequency such as 503kHz, which are coupled to the input of a divide-by-1 6 counter 52. The twicehorizontal frequency (2fH) output of counter 52 is applied to counter 26 as a clock input and to a divide-by-2 counter 54 to generate horizontal deflection drive signals at the horizontal frequency (fH). The fH signals from counter 54 are applied to a horizontal deflection and high voltage generating circuit designated 56 which produces ultor voltage for kinescope 20 and also produces a sawtooth deflection current through horizontal deflection coils 58 associated with kinescope 20.

In operation, the television receiver of FIGURE 4a operates similar to that of FIGURE 1 and the discussion of the FIGURE 1 operation with respect to the waveform of FIGURES 2 and 3 is equally applicable to the operation of FIGURE 4a.

FIGURE 4b illustrates a loop filter which may be substituted for capacitor 40 and which is switchable between a low-speed and a highspeed condition.

As mentioned, lack of response to phase changes corresponds to a low-gain conditions of the phase detector, which is particularly disadvantageous when the PLL must operate upon the video signals produced by a tape recorder wherein the oscillator must slew at a high rate at some time near the vertical blanking interval. Moreover, the low PLL gain may allow the oscillator to slew away from the correct phase even when there is no step change in the phase of -the input signal. This can happen, for example, if as previously mentioned current sources 42 and 44 are not perfectly matched in amplitude. There will be a net unbalance in current which will change the charge on capacitor 41 and result in oscillator slewing, which will require time to recover to the correct phase after the end of the equalizing pulse interval.The rate of slewing away from the correct phase may be exceptionally large during the low gain condition of the phase detector when the switchable loop filter, as illustrated in FIGURE 4b, is switched to a high speed condition. Such switching is described in the aforementioned Itoh patent and in United States Patent No. 4,144,544 issued to Fernsler.

FIGURE 5 illustrates in block diagram form a television receiver embodying the invention. Those elements of FIGURE 4 corresponding to elements of FIGURE 1 are designated by the same reference numbers. In FIGURE 5, a horizontal oscillator 450 is controlled by a direct control voltage from phase detector 30. Oscillator 45Q operates at a high frequency such as 503 kHz. A divide-by-1 6 counter 452 receives the oscillator output and reduces it to approximately 32 kHz, which is twice the horizontal deflection frequency (2fH). The 2fH output of counter 452 is applied to a divide-by 525 counter 454 of a vertical count-down arrangement.The vertical count-down arrangement includes a logic circuit 456 which responds to the various states of counter 454 and to vertical synchronizing pulses from separator 1 6 to produce a vertical drive signal for vertical deflection circuit 28. Such a vertical count-down arrangement as previously mentioned compensates for the excessive sensitivity of the sync separator to noise by excluding all separated sync signals but those positively identified as vertical sync signals, and supplies counter produced vertical drive pulses to deflection circuit 28 continuously, regardless of the presence or absence of identifiable sync from separator 1 6.

Additional counter outputs at preselected times may be obtained in a known manner by means of logic circuit 456.

The 2fH output of counter 452 is also applied to a divide-by-2 multivibrator 458, which produces signals at the horizontal deflection frequency (fH) for application to horizontal deflection circuit 51. The fH output of multivibrator 456 is also applied to an input of a controlled switch circuit 460. The 2fH output of counter 452 is applied to another input of controlled switched circuit 460.

Switch circuit 460 selectively applies fH or 2fH square waves to phase detector 30 under control of a vertical-frequency signal illustrated as 630 in FIGURE 7d produced by logic circuit 456.

FIGURE 6 illustrates in schematic form a circuit suitable for use as controllable switch 460 of FIGURE 5. In FIGURE 6, a controllable switch designated generally as 560 includes first and second input terminals or jacks 510 and 512 to which signals at fH and 2fH are applied from multivibrator 458 and counter 452, respectively. Controllable switch 56a includes a further input terminal 514 coupled to logic circuit 456 for receiving a verticalfrequency switching control signal illustrated as signal 630. The positive-going portion of signals 630 has a duration encompassing at least the synchronizing and equalizing pulse portions of the vertical blanking signal.Controllable switch 560 produces at an output jack 516 signals at fH during those intervals in which control signal 630 is negative-going or low and signals at 2fH during those intervals in which control signal 630 is positive or high.

Controllable switch 560 includes an NPN transistor 520 having its base coupled to jack 510 and its emitter coupled to ground. A transistor 522 has its base coupled to jack 512 and its emitter coupled to ground. The collector of transistor 520 is coupled to a source B+ of operating potential by means of a resistor 524, and the collector of transistor 522 is coupled to B+ by means of a resistor 526. The base of an NPN transistor 530 is connected to the collector of transistor 52O, and its emitter is connected to ground. The collector of transistor 530 is connected to one end of a summing load resistor 532, the other end of which is connected to B+.

An NPN transistor 534 has its base connected to the collector of transistor 522 and its emitter connected to ground. The collector of transistor 534 is connected to the collector of transistor 530 and to output jack 51 6. The base transistor 530 is connected to the collector of an NPN transistor 536, the emitter of which is coupled to ground and the base of which is connected to input jack 514. The base of transistor 534 is connected to the collector of an NPN transistor 538, the emitter of which is connected to ground and the base of which receives biasing current from B+ through a resistor 540. An inverting NPN transistor 542 has its collector connected to the base of transistor 538, its emitter connected to ground and its base connected to jack 514.

In operation during the vertical scanning interval, oscillator signals at fH and 2fH are applied to jacks 510 and 512, respectively, and the input signal to jack 514 is low. With jack 514 low, transistors 536 and 542 are deprived of base-emitter bias and are nonconductive.

Consequently, transistor 538 is conductive and holds the base of transistor 534 near ground, regardless of the 2H drive from transistor 522.

Thus, transistor 534 cannot respond to 2fH signals. With transistor 536 nonconductive, the base of transistor 530 is switched by the fH signal, which appears noninverted at output jack 516 for application to phase detector 30. During the equalizing and vertical synchronizing pulse portions of the vertical blanking signal, control signal 630 applied to input jack 514 is high. With signal 630 high, transistors 536 and 542 become conductive. Transistor 542 deprives transistor 538 of base drive, and it becomes nonconductive and allows transistor 534 to be driven at 2fH by transistor 522 to produce a noninverted 2fH output at jack 516. At this same time, conductive transistor 536 maintains the base of transistor 530 low regardless of the fH drive from transistor 520, and prevents appearance of fH signals at output jack 51 6.

In operation of the arrangement of FIGURE 5, separator 16 produces on conductor A synchronizing signals illustrated as 620 in FIGURE 7c. As illustrated in FIGURE 7, synchronizing signals 620 recur at horizontal frequency fH in the interval TO-T6 and at 2fH in the interval T6-T24.

Thus, the time S'O--T24 for which waveforms are illustrated in FIGURE 7 represents a time interval encompassing the end of the vertical scanning interval and the beginning of the vertical blanking interval.

Before time TO, switch 460, in response to gating signal 630, allows the fH output of multivibrator 458 to be applied over a conductor E to the input of phase detector 30. The signal on conductor E is represented by signal 640 of FIGURE 7e. During several horizontal lines preceding time TO, phase detector 30 compared synchronizing signals 620 with signal 640 to produce discharging and charging gated current pulses illustrated as signals 650 and 660, respectively, in FIGURES 7f and 7g. The filtered output of phase detector 30, illustrated as 680 in FIGURE 7H, was applied to horizontal oscillator 450 to force signal 610 into consonance with sync signal 620, in a manner similar to that described in conjunction with FIGURE 1.

Phase detector 30 is enabled in the interval TO T4 by sync pulse 620, and responds with a discharging current pulse 650 in the interval in which signal 640 is low and with a charging current pulse 660 when signal 640 is high. This results in a discharge of the control signal capacitor in the interval Td-T2 and a charge in the interval T2-T4, which in turn results in a perturbation illustrated in exaggerated form in FIGURE 7h. Because the. durations of pulses 650 and 660 are equal, control voltage 680 assumes the same value after the sync pulse as it had before, and the PLL does not slew the oscillator.

At a time illustratively at T6 but which may range widely, counter 454 reaches a predetermined count and logic circuit 456 responds with a positive-going portion of gating signal 630. With gating 630 positive, switch 460 couples to conductor E the 2fH signals 600 from counter 452 rather than the fH signals 610 from multivibrator 458. Thus, from time T6, until after the end (not shown) of the positive going portion of pulse 630, signal 640 applied over conductor E to phase detector 30 for comparision with sync signals 620 is at twice the horizontal frequency.

In the interval after time T6, phase comparisions occur twice as often, and the gain of the PLL is thus increased, and the oscillator can if required be slewed more rapidly. For example, in the interval T8-T1 2 the transition of the oscillator signal 600 and the corresponding signal 640 applied to phase detector 30 are centered on sync signal 620, whereby current drive signals 650 and 660 have equal durations and oscillator control signal 680 remains unchanged. Assuming that the oscillator phase changes after time T1 2 because of temperature or voltage changes, time T1 6 at which the transition occurs in signal 600 and corresponding signal 640 is not centered on interval V14--T18 in which a sync pulse 620 occurs.Consequently, discharging current pulse 650 decreases in duration and charging current pulse 660 increases in duration, resulting in a net increase in control voltage 680. Similarly, during the next synchronizing pulse interval T20-T24, the control voltage is again increased to increase the correction signal. If the phase comparison in phase detector 30 had been between sync signals 620 and signal 610 as in the prior art rather than between sync signal 620 and signal 600 in accordance with the invention, the oscillator control signal illustrated in FIGURE 7h would have responded as illustrated by dashed portion 682, producing not net correction in response to the phase error.

It is not necessary to switch the signal applied to the phase detector from 2fH to fH as illustrated in FIGURE 5. If 2fH signals are continuously applied to phase detector 30, the gain of the PLL will automatically increase during the equalizing and vertical synchronizing pulse intervals. Such an arrangement, without more, permits a 1 800 phase ambiguity, which might occur any time the signal source is momentarily interrupted, as when changing stations. The ambiguity may be resolved, as here, by a switching arrangement which applies fH signals to the phase detector for an interval sufficient to force the PLL to lock.

FIGURE 8 illustrates in block diagram form another embodiment of a television receiver constructed in accordance with the principles of the invention. Those elements of FIGURE 8 corresponding to elements of FIGURE 4 are designated by the same reference numbers. In FIGURE 8, a logic circuit designated generally as 60 acts as a switch interposed between the sync signal separator 1 6 and phase detector 30.

Generally speaking, gated circuits 60 allow synchronizing pulses to flow to phase detector 30 for locking the horizontal deflection drive to the synchronizing signals. Alternate equalizing pulses, however, are not allowed to pass to the phase detector (i.e., the switch is opened during alternate equalizing pulses), so the phase detector and the PLL do not respond to the alternate equalizing pulses so that full PLL loop gain is maintained through the vertical synchronizing and equalizing pulse intervals.

Gating circuit 60 includes a data-type (D) flipflop (FF) 62, the D input of which is connected to conductor B to receive fH signals from counter 54.

The clock input of FF62 is connected by way of a conductor C to the 2fH output of counter 52. The Q output of FF 62 is coupled to an input of a NAND gate 64 by a conductor D. The other input of NAND 64 is coupled to a logic circuit 22 ofer a conductor E. The output of NAND 64 is coupled to an input of AND gate 66 by a conductor F. The other input of AND 66 receives sync pulses from separator 16 by conductor A. The output of AND 66 is coupled to phase detector 30 by a conductor G.

In operation, sync separator 1 6 produces on conductor A recurrent sync pulses illustrated as 300 in FIGURE 9a. The sync pulses recur at twice the horizontal rate in the interval between TO and T6, corresponding to the vertical synchronizing and equalizing pulse intervals, as described in conjunction with FIGURE 2. The fH output of counter 54 on conductor B is illustrated by voltage waveform 310 in FIGURE 9b. The 2fH output of counter 52 applied to FF 62 over conductor C is illustrated as waveform 500 of FIGURE 9c. During each negative-going transition of waveform 500, the logic level applied to the D input of FF62 is transferred to the 0 output and held until the next negative-going transition of waveform 500. The signal at the Q output is illustrated by waveform 510 of FIGURE 9d.It will be noted that waveform 510 is similar to waveform 310 but is shifted in phase by 900. The input to NAND 64 on conductor E is illustrated as waveform 520 in FIGURE 9e. Waveform 520 remains low during the entire vertical scanning interval, and goes high at a time near time 0, the time at which the vertical scanning interval ends and the vertical blanking interval begins. Waveform 520 remains high until a later time such as T6 at which the equalizing pulses end. The exact starting and ending time of waveform 520 is not critical to the invention. Generation of signals such as 520 in a vertical count-down are well-known in the art as previous mentioned and required no further description here.NAND 64 is inhibited by signal 520 during the vertical scanning interval preceding time TO, and can respond to phaseshifted signal 5,10 on conductor D only during the interval TO-T6 during which signal 520 is high.

In the interval TO--T6 NAND 64 produces on conductor F a signal illustrated as 53O in FIGURE 9f, which in that interval is the inverse of phaseshifted waveform 510. When signal 530 is high, AND gate 66 is enabled and can pass sync pulses.

During those intervals in which signal 530 is low, AND 36 is inhibited, and cannot pass synchronizing pulses from separator 16 to phase detector 30. Since waveform 530 is shifted in phase with respect to fH signal 310 it is also shifted in phase relative to sync pulses 300. That is, rather than the transition in signal 530 coinciding with the transitions of sync pulses 300, sync pulses 300 occur when signal 530 is either high or low. Thus, every other sync pulse 300 is prevented from reaching phase detector 30 in the interval TO--T6, as illustrated by signal 540 in FIGURE 9g. In FIGURE 9g, solid line 540 illustrates the signals passing through conductor A to conductor G through AND 66, and the dotted pulses 542 illustrate the alternate equalizing pulses which are gated out.

With the arrangement shown in FIGURE 8 during the vertical sync and equalizing intervals, the phase detector receives synchronizing pulses only in the region of positive-going transitions of fH signal 310, and not in the region of negativegoing transitions. Thus, the gain of the PLL is maintained even during the equalizing intervals. It should be noted that the pulse waveforms illustrated in FIGURE 9 is exaggerated for clarity and is therefore not exactly to scale.

Other arranyements can inhibit the effect of the phase detector on the PLL during alternate equalizing pulses. FIGURE 10 illustrates a portion of a television receiver including an alternative embodiment of the invention. In FIGURE 10, a phase detector designated generally as 30 and identical with those described in conjunction with FIGURES 1, 4 and 8 receives separated horizontal synchronizing pulses such as signals 300 over a conductor A. A switch illustrated as a relay 668 includes a normally-open switch contact 669 coupling the output of phase detector 30 to loop filter capacitor 41 for filtering the control signal for application to VCO 50. A gating circuit designated generally as 660 includes a D FF 662 and a NAND 664. FF 662 receives fH pulses over a conductor B from the output of a counter chain (not shown).

A clock input of FF 662 receives 2fH signals over a conductor C from the 2fH output of the counter chain (not shown). A signal similar to signal 510 of FIGURE 9d is coupled to NAND 664 over a conductor D. A signal similar to signal 520 of FIGURE 9e is coupled to the other input of NAND 664 over a conductor E. NAND 664 applies a signal similar to 530 of FIGURE 9f to the coil of relay 668 over a conductor F. During the intervals in which signal 530 is high, the coil of relay 668 is energized and the switch is closed. This allows the flow of charge and discharge currents through filter capacitor 41 in response to sync pulses 300.

During those intervals in which signal 530 is low, which intervals correspond with alternate equalizing pulses in the interval T0-T6, the relay coil is deenergized and the normally open contacts open thereby preventing current from flowing in capacitor 41 notwithstanding that the current sources are energized. Thus, the arrangement of gating circuit 660 and relay 668 prevents an output from being generated by phase detector 30 during alternate equalizing pulses.

Other embodiments of the invention will be apparent to those skilled in the art. In particular, with respect to a modified FIGURE 5 embodiment when 2fH is applied to the phase detector continuously it will be apparent that the phase ambiguity may be resolved in other ways than by applying fH signals to the phase detector for a portion of the vertical scanning interval. For example, a gating circuit may be used to compare the fH output of the VCO with horizontal sync signals from the separator, and a 1 800 phase shifter may be coupled between the output of the divide-by-two flip-flop producing the fH signal and the horizontal deflection circuit. The phase shifter is toggled when the fH drive to the horizontal deflection circuit is improperly phased relative to the separator output.

Other embodiments of the FIGURE 8 embodiment will also be obvious to those skiled in the art. For example, the actual operating components of phase detector 30 can be disabled during the alternate equalizing pulses, as for example by breaking the connection between AND gates 32 and 34 and the controlled current sources 42 and 44. The relay illustrated in FIGURE 10 may be replaced by an appropriate transmission gate. The VCO output signal applied to the phase detector may be derived from horizontal deflection circuit 56 rather than from counter 54. The VCO may operate directly at the H frequency, thereby avoiding the need for counters.

Claims (8)

1. A television phase-lock loop apparatus for the horizontal oscillator of a television receiver, comprising: controllable oscillator means including an output terminal at which oscillator signals exhibiting successive transitions of first and second polarities are generated and also including a control input terminal; phase detection means including a first input terminal, a second input terminal, and an output terminal coupled to the control input terminal of said controllable oscillator means; a source of horizontal synchronizing signals having an output terminal, said synchronizing signals including horizontal rate pulses, said synchronizing signals also including intermediate pulses occurring in the intervals between said horizontal rate pulses, said intermediate pulses occurring during at least a portion of the vertical blanking interval; and forminy means for providing coupling between the ouput of said controllable oscillator means and the first input terminal of said phase detection means and between the output terminal of said source of horizontal synchronizing signals and the second input terminal of said phase detection means for forming a phase-lock loop responsive to said synchronizing signals for locking the frequency and controlling the phase of said oscillator means, wherein said forming means includes switch means fdr selectively controlling the coupling of said oscillator signals or said synchronizing signals to said input terminals of said phase detection means, or the coupling of the phase detector output to the oscillator control input, in such manner that the phase detection means will control the oscillator in response to synchronizing signals occurring in substantial time coincidence with only first polarity transitions of the coupled oscillator signals.

2. Apparatus according to Claim 1 wherein said switch means is coupled between said source of synchronizing signals and said phase detection means for gating said horizontal-rate signals to said second input terminal of said phase detection means and for preventing said intermediate pulses from reaching said second input terminal of said phase detection means.

3. Apparatus according to Claim 1 wherein said means inhibits operation of said phase detection means, at least during the occurrence of said intermediate pulses for preventing said phase-lock loop from responding thereto.

4. Apparatus according to Claim 1 wherein said switch means is coupled with said phase detection means for preventing generation of a phase detector output signal in response to said intermediate pulses, and timing means coupled to said switch means for operating said switch means at a time related to the anticipated arrival time of said intermediate pulses.

5. Apparatus according to Claim 4, wherein said timing means includes means coupled to said output terminal of said controllable oscillator means for phase-shifting said oscillator signals, means for gating said switch means in response to said phase-shifted oscillator signals, and means for inhibiting said gating except during the expected time of arrival of said intermediate pulses.

6. Apparatus according to Claim 1 wherein said oscillator means includes a second output terminal for providing oscillator signals at a second frequency related to and greater than said first frequency; and said switch means couples said first input terminal of said phase detection means to said first and second output terminals of said controllable oscillator means for applying said second frequency oscillator signals to said first input terminal of said phase detection means substantially during the portion of said vertical blanking interval when said intermediate pulses occur and for applying said first frequency oscillator signals to said first input terminal of said phase detection means during substantially all other times.

7. An arrangement according to Claim 6 wherein said switch means comprises: first and second cascaded inverters, including a first juncture therebetween, the input of said first inverter being coupled to said first output terminal of said controlled oscillator means for receiving oscillator signals at said first frequency, the output of said second inverter being coupled to a summing output terminal; third and fourth cascaded inverters including a second juncture therebetween, the input of said third inverter being coupled to said second output terminal of said controlled oscillator means for receiving said oscillator signals at said second frequency; and gating means coupled to said first and second junctures for alternately enabling said second and fourth inverters for alternately passing said first and second frequency oscillator signals, respectively, to said first input terminal of said phase detection means.

8. Television phase-lock loop apparatus substantially as hereinbefore described with reference to Fig 5, Fig 8 or Fig 10 of the accompanying drawings.