GB2040089A - Queuing controller - Google Patents

Abstract

A queuing controller stores strings of data and transmits them to a computer when required. The controller 1 is coupled to receive data passing between the computer and its operator's terminal and receives and transmits data from and to the computer via serial/parallel input/output device 11. The controller has a keypad 2 coupled to the rest of the device via a wire or ultrasonic link. A keypress queue store 6 stores codes corresponding to the keystrokes and accesses a store 7 containing initial addresses of associated data stored in a main memory 8. Memory 8 may contain permanently stored data or may be loaded from the computer. The controller can supply to the computer instructions and data normally supplied via the operator's terminal and can for example search for a string of data received from the computer and supply a response thereto or issue an audible bleep when operator intervention is required. <IMAGE>

Description

SPECIFICATION Queuing controller This invention relates to a queuing controller for use in conjunction with a computer and an operator's terminaj.

The application of computers to most fields, but particularly to scientific instrumentation, requires an easy means for the user to interact with the system as a whole. Such interaction is usually via a printing or a visually displaying terminal and much ingenuity is usually exercised in trying to ensure that the system as a whole can easily be made to perform adequately under a wide variety of different circumstances. In the past this has usually meant paying particular attention to the design of the system programming (the software) and making it conform to the particular idiosyncracies of the computer, its storage system, printer and terminal (the hardware).

If particularly complex actions have to be performed then operation of the system via the terminal usually necessitates a fairly lengthy operator interaction, via a keyboard, to ensure that a list of questions is answered by the user before operation can com mence.

A number of devices has been employed in the past to minimise such lengthy 'operator-system conversation' and of these the prestorage of standard answers is perhaps the best known. In the particu lar field of the application of computers to organic mass spectrometry, for example, a number of complete sets of answers (or parameters) may be stored for each major system function.

Other software devices have also been employed to allow specific jobs to be queued to give substantial unattended operation.

However, all of these approaches have the basic fault that they have limitations in use. Prestorage of parameters requires a re-edit process to be gone through if any change is required and considerable time can be spent in trying to set up a job queue, or batch, for the particular sequences of interest.

This invention seeks to overcome many of these limitations by providing a means of response queu ing which can still be used in conjunction with all standard system software facilities so supplement ing the overall system capability without introducing any additional restrictions.

According to the invention, we provide a queuing controller for use in conjunction with a computer and an operator's terminal of the computer, compris ing means for receiving signals which pass between the computer and its terminal and for transmitting signals to the computer, means for storing a plurality of strings of data for controlling the operation of the computer, and means for storing a plurality of codes corresponding to instructions input from an operator's input device, each said data string corresponding to one of said instructions, and the apparatus being arranged to supply automatically to the computer when required by the computer the data strings corresponding to the input instructions.

Preferably, the apparatus is provided with an operator's input device in the form of a keypad, which may be coupled to the means for storing the instruction codes via a wire connection or an ultrasonic link. The stored instruction codes may each correspond to an address in a main memory for storing the data strings.

The main memory may be a preprogrammed read only memory, but preferably it consists at least in part of a programmable memory which may be loaded by a user with control data to suit a particular system. Advantageously, the main memory is loadable from the computer.

The controller provides extra facilities in hardware in such a way that they can be applied to any system regardless of the way in which it may have been originally programmed.

The controller is designed in such a way as to intercept the signals which pass between a computer processor and its terminal. Such signals are usually transmitted in an internationally agreed way (known as serial transmission) of 8-bit characters to one of a number of different codes. As presently embodies ASCII (American Standard Code for Information Interchange) is used, but any text code could be used.

In its presently preferred embodiment the queuing controller does not communicate directly with the terminal although this is a possible extension which could have certain additional advantages even though additional cost would be involved.

In the preferred embodiment, pressing a single key on a hand held keypad activates the controller to send out a prestored character string to the computer to initiate a particular system function. Any remaining characters needed to provide the system with all necessary information to perform the task are then issued in sequence and at the correct time intervals since the controller monitors the characters sent back by the computer to the terminal and can be set to look for particular character sequences corresponding to the questions requested by the computer.

A normal system function is then performed entirely automatically and the operator's terminal still displays the full question and answer sequence - albeit at a much greater speed than if manual operation was involved-to allow an operatorto see exactly what is happening. If, for example, a number is still required to be set by the operator, or if an error occurs, the transmission sequence of the controller stops and corrective action can still be made by the operator via the terminal keyboard in the ordinary way. Automatic operation then resumes immediately. Where it may be necessary to prompt the operator for a response, the controller can issue an audible bleep.

A further feature of the controller is its ability to retain a memory (or queue) of keys on the pad that have been pressed. In this way up to e.g. 64 keypad operations can be set up and operated in sequence so giving automatic unattended operation of the system.

The controller may have facilities to allow the meanings of the different keys on the pad to be changed and this is done by loading text characters into the controller either by the user himself using a small high level language (e.g. BASIC) program on his computer or by the transfer of a file containing the appropriate text from the computer into the main memory. No special knowledge or skill is needed for this - only an ability to use the computer to write such text on the existing terminal screen. Use of a special character code prior to transmission of the actual text data sets the controller into a memory storage mode. Alternatively, some of the controller memory can be preprogrammed in ROM (read only) memory so that specific keys have permanentfunc- tions assigned to them.An attractive use of such a facility is the automatic loading of the controller memory from a file on the computer's main store. In this way the controller can effectively load itself. One of the keys on the pad is pre-defined to act as a reset.

When pressed this terminates the current sequence and clears the key queue.

An embodiment of the invention will now be described by way of example and with reference to the accompanying drawings, in which: Figure 1 shows schematically the connection of a queuing controller according to the invention to a computer and an operator's terminal of the computer; Figure 2 is a functional block diagram of the controller of Figure 1; Figure 3 illustrates the arrangement of the stored data strings in the controller; and Figure 4 is a more detailed block diagram of the controller of Figure 1.

Referring to Figure 1 the queuing controller 1 is provided with an associated keypad 2 and is arranged to receive signals passing from a computer 3 to its terminal 4. The controller 1 is also arranged to send data signals to the computer 3. The keypad 2 is coupled to the controller 1 via an ultrasonic or cable iink 5 and may be provided with 16 keys, for example.

As shown in Figure 2 the controller 1 includes a key press queue store 6 which is arranged to store binary codes corresponding to the keys pressed on the keypad. For example, the store 6 may comprise a FIFO (first in first out) store having the ability to store up to 64 binary numbers each 4 bits wide and representative of one of the 16 keys of the keypad. The store 6 is coupled to another store 7 which contains a list of addresses each corresponding to one of the keys of the keypad. For example the store 7 may be a PROM (Programmable Read Only Memory) capable of storing 16 words each of 12 bits. The addresses stored in the store 7 are used to access addresses in a 4k main memory 8 which contains a plurality of character strings for controlling the computer as described below.The main memory 8 may comprise a ROM (Read Only Memory) section 9 containing fixed information and a RAM (Random Access Memory) section 10 which may be loaded by the user. The controller 1 also includes input'output logic 11 for sending and receiving data to and from the computer 3 in serial form. The input'output logic 11 may comprise a UART (Universal Asynchronous Receiver and Transmitter) circuit, for example.

In operation, a sequence of keys of the keypad 2 may be pressed and corresponding codes are stored in the store 6. When the controller is running the codes in the store 6 are removed in sequence as required and each code is used by the store 7 to identify the appropriate address in the main memory 8 to identify the corresponding data string. The data string is then supplied to the computer as required.

As indicated in Figure 2 there is no constraint that certain keys may only control permanently stored data in the ROM section 9. Any key may be assigned to customer loaded data held in the RAM section 10 orto permanently stored data.

Figure 3 illustrates howthe data in the main memory 8 may be set out. Each data string corresponding to a single key of the keypad starts and finishes with a control character such as the control characters 15, 16 and 17. Strings of characters 18, e.g. in 8-bit ASCII code, are stored for access between the control characters. The control characters 17 represent the information that the data string corresponding to a particular key is finished and will initiate the removal of another code from the key press queue store 6. The other control characters 15 and 16 are used by control logic within the controller as instructions to define the operation to be performed on or with the character strings 18. For example, the control characters 15 and 16 may represent the following instructions: Output the following string to the computer.

Search for the following character string in the data received from the computer.

Issue a bleep tone to prompt the operator.

Data may be loaded into the RAM section 10 from the computer3 and in ordert nablethis a unique data code may be allocated to set the data storage mode. The controller 1 will include a circuit for continuously searching forthe unique data code so that the data storage mode may be operated at any time.

Further, one of the keys of the keypad may be assigned to cause a reset function such that when pressed the current sequence of operations is terminated and the key press queue store 6 is cleared.

Referring now to Figure 4, the circuit includes control logic 12 for controlling the operation of the other components. A 12-bit reversible binary counter 13 is connected between the store 7 and memory 8 and is presettable to one of the words in the store 7.

The outputs from the counter 13 are used as an address in 4096 word memory 8 which contains the plurality of character strings for controlling the computer. The memory8 is composed offoursegments each having a size of 1024 words, each eight bits wide. Each segment may be a ROM 9 or a RAM 10.

The 8-bit characters contained in the memory 8 are used by the input'output logic 11 to communicate with the computer 3. The input'output logic 11 comprises a UART (Universal Asynchronous Receiver and Transmitter) 19 which converts the 8-bit characters held in the memory 8 into a serial data string.

This data string is then combined with data from the terminal 4 in an OR gate 26. The combined data string passes through an interface circuit 25 to the computer 3. There are four interface circuits 25 in the controller, each providing level conversion and optical isolation of the signals passing between the terminal, the controller, and the computer.

Serial data passing from the computer to the terminal is also monitored by the UART 19 and converted into 8-bit characters.

The speed of operation of the UART is matched to that of the computer and its terminal by a Baud Rate Generator 20. This is a crystal controlled circuit which allows selection of most of the commonly used data transmission rates.

The 8-bit characters provided by the UART 19 are compared with those in main memory 8 by a comparator 21. The received characters are also monitored by a PROM 23 which is programmed to identify the unique data code which is used to set the controller 1 into the data storage mode. In this mode a gate 24 is enabled to allow 8-bit ASCII characters received by the UART to be written into the RAM memory 10.

An additional PROM 22 identifies the control characters 15,16, 17 held in the memory 8.

The control logic 12 accepts signals from, and generates control signals to, each of the individual components within the controller. It consists primarily of a PROM 28 and a latch 29 connected as a sequence controller. The outputs from the latch 29 define the current control conditions and the inputs to the latch define the next control conditions and are transferred to the outputs when a signal is supplied by OR gate 30. PROM 28 stores a series of binary numbers representing various control conditions which numbers are selected by the input addresses.

The input addresses of PROM 28 are defined by some of the outputs of latch 29 (which serve to indicats the current control condition) and by the outputs of comparator 21 and PROMS 22 and 23.

The inputs to OR gate 30 respectively indicate (i) data is available in FIFO 6 (i.e. a key has been pressed); (ii) a character has been received by the UART 19 from the computer 3; and (iii) a character has been transmitted by the UART 19 to the computer 3.

The inputs to PROM 28 are three bits indicating the current output of latch 29, three bits from PROM 22 indicating a detected control character, one bit from PROM 23 indicating a detected unique 'load' data code, and one bit from comparator 21 indicating that the latest received character is the same as the currently addressed character in main memory 8.

The outputs from latch 29 are as follows: (i) a signal to the FIFO 6 to allow removal of key entries; (ii) a signal to the counter 13 to load the address generated by the PROM 7; (iii) two signals to allow incrementing and decrementing of the counter 13; (iv) a signal to the memory 8 to control reading or writing of data; (v) a signal to enable the gate 24 during data storage mode; (vi) a signal to the UART 19 to initiate transmission of data from the memory 8 to the computer 3; and (vii) a signal to bleeper 27.

The internal signals from latch 29 to PROM 28 may be separate outputs of latch 29 or may be decoded from the other outputs, or alternatively some of the other outputs may be decoded from the internal signals.

In operation, when one of the keys on the keypad 2 is pressed, a 4-bit code is entered into the FIFO 6.

This code appears at the output of the FIFO and selects one of the 12-bit words in the store 7. The control logic 12, when it detects an entry in the FIFO, generates a load signal for the counter 13. This causes the counter to be preset with the contents of the selected word in the store 7. The output of the counter 13 is used as an address in the memory 8.

The contents of the addressed location is a control character 15. This control character is recognised by the PROM 22 which generates a control signal to the logic 12. This signal informs the logic what to do with the character string 18 as follows:~ 1. Output the Following String The control logic 12 increments the counter 13 to select the first character in the string. This character is then transferred to the UART 19. The UART then transmits the character to the computer 3. When this transmission is complete a signal from the UART 19 informs the logic 12 which then increments the counter 13 thus presenting the next character. This process is repeated until the next character presented is a control character.

2. Search for the Following Character String The control logic 12 increments the counter 13 to select the first character in the string. When a character is received by the UART from the computer it is compared, in the comparator 21, with the selected character from the memory 8. If the two characters are identical the counter 13 is incremented. The process is then repeated until the next character selected is a control character. If, at any time, the compared characters are not identical, the counter 13 is decremented to the start of the character string and the comparison starts again.

3. Issue a Bleep Tone The control logic increments the counter 13 and triggers a bleeper 27 to generate a short tone.

4. Finished the Operation of this Key The logic 12 removes the core from the FIFO 6 and checks to see if there are any more. If there are the counter 13 is reloaded. If not the logic waits forthe next key to be pressed.

At any time the PROM 23 may recognise the special load code. When this happens the gate 24 is enabled and the counter 13 is reset. Each character which is then received by the UART 19 passes through the gate 24 and is written into the memory 8. After each character the counter 13 is incremented to select the next address to be written. When the PROM 23 recognises the load code a second time the load mode is terminated. In this way the operator is able to define the function of each of the keys on the keypad to suit his particular requirements.

It is possible to implement direct communication of the controller 1 with the terminal 4 as well as with the computer3 if required. Further, some limited form of decision making could be implemented so that different text strings can be sent according to whatever string is received by the controller from the computer.

The invention could be embodied as a microprocessor in which codes representing the keystrokes are stored in a random access memory and the data strings are stored in RAM or ROM and it is intended that the claims be construed so as to include such embodiment.

Claims (12)

1. A queuing controller for use in conjunction with a computer and an operator's terminal of the computer, comprising means for receiving signals which pass between the computer and its terminal and fortransmitting signals to the computer, means for storing a plurality of strings of data for controlling the operation of the computer, and means for storing a plurality of codes corresponding to instructions input from an operator's input device, each said data string corresponding to one of said instructions, and the apparatus being arranged to supply automatically to the computer when required by the computer the data strings corresponding to the input instructions.

2. A queuing controller as claimed in claim 1 wherein an operator's input device in the form of a keypad is coupled to the means for storing the instruction codes via a wire connection or an ultrasonic link.

3. A queuing controller as claimed in claim 1 or 2 wherein the stored instruction codes each correspond to an address in a main memory for storing the data strings.

4. A queuing controller as claimed in claim 3 wherein said main memory consists at least in part of a programmable memory which may be loaded by a user with control data.

5. A queuing controller as claimed in claim 4 wherein said main memory is loadable from the computer.

6. A queuing controller as claimed in claim 5 arranged to detect a unique control character in data received from the computer and to initiate the loading of data into the main memory in response to the detection of said unique character.

7. A queuing controller as claimed in claim 5 or 6 in which said main memory is permanently programmed so as to enable the automatic loading of the main memory from the computer in response to an instruction from the controller.

8. A queuing controller as claimed in any preceding claim comprising a main memory for storing said strings of data, a first-in first-out store for storing a sequence of operator instruction codes, a read-only memory controlled by the output of the first-in first-out store to provide an initial address for the main memory and a counter arranged to be preset to said initial address and to be incremented underthe control of control circuitry to successively access data characters stored in said main memory.

9. A queuing controller as claimed in any preceding claim including a comparator arranged to compare a character stored in the data store with a character received from the computer so as to enable a predetermined string of characters received from the computer to be identified.

10. A queuing controller as claimed in any preceding claim including a comparator arranged to identify a unique data character received from the computer and to enable a gate allowing a subsequent string of characters to be loaded into the data store from the computer.

11. A queuing controller as claimed in any preceding claim including an audible indicator for prompting an operator.

12. A queuing controller substantially as hereinbefore described with reference to the accompanying drawings.