GB2040058A - Exposure indicator device - Google Patents

Abstract

An exposure indicator device for cameras comprises a photosensitive measuring circuit constructed as a low power integrated circuit, a liquid crystal display (55, Figure 3 not shown) driven by the measuring circuit, and a solar cell array 1 for providing power for the measuring circuit and the display. As shown, the device comprises a first oscillator 2 to 7 having a photo diode 2, a second oscillator 8 to 12 having its frequency determined by a resistor 9, and a counter 15 for counting the output pulses from the first oscillator during each period of the pulses appearing at the output of the second oscillator The output of the counter 15 is connected to a computer circuit (Figure 2 not shown), the output of which is connected to an indicator circuit (Figure 3 not shown) including a liquid crystal display (55). The device is supplied with power by a solar cell array 1 and the oscillators, the counter 15, and the computer circuit are constructed as a low power integrated circuit. The array 1 may itself comprise the photosensitive element in the first oscillator. <IMAGE>

Description

SPECIFICATION Exposure indicator device This invention relates to an exposure indicator device for a photographic camera.

In known indicator devices for photographic cameras, there are provided electronic circuit elements as well as indicator elements which are supplied with power by a battery. The battery may be connected to these elements by means of the shutter release or by means of a control lever. In order to keep demand on the battery as low as possible, a visual display is only provided when either the shutter release or the lever are operated.

However, the contacts through which the power is supplied from the battery are liable to wear and also to dirt collection.

It is an object of the present invention to provide an exposure indicator device which does not require mechanical switching contacts.

According to the present invention there is provided an exposure indicator device for a photographic camera comprising a photo-sensitive measuring circuit constructed as a low power inte grated circuit, an indicator circuit driven by the measuring circuit and including a liquid crystal display, and a solar cell array for providing power for the measuring circuit and the indicator circuit.

Such low power integrated circuits have the advantage that they consume a very small leakage current and that load current is only consumed during switching operations owing to the charge exchange which accompanies such operations. The liquid crystal display also consumes very little current because it has a very high resistance and is activated by field intensity and not by current flow.

The leakage current of integrated semi-conductors is negligible. By means of the solar cell array, which is not excessively large, the measuring and indicator circuits may be easily supplied with power and no switching contacts are required for switching the device on or off. Consequently, the chances of the device developing a fault are very low. Also, the device of the present invention is very well protected against damp conditions.

The measuring circuit may be constructed as an integrated injection logic circuit or as a complimentary metal oxide semi-conductor circuit.

Preferably, the measuring circuit comprises a first oscillator having a photo-sensitive frequency determining element, a second oscillatory having a non-photo-sensitive frequency determining element for determining the period of each measuring cycle, a digital counter responsive to the outputs of the first and second oscillators, and a computer circuit responsive to the out of the counter and including a memory stage.

The liquid crystal display may be switched off when the output voltage of the solar cell array falls below a predetermined value, said predetermined value being high enough for operating and measuring and indicator circuits.

By switching off the liquid crystal display when the output voltage of the solar cell rray falls below a predetermined value, said predetermined value being high enough for operating the measuring and indicator circuits: By switching off the liquid crystal display when the output voltage of the solar cell array falls below a predetermined value, there is provided a visual indication that the output voltage of the solar cell array is no longer high enough to operate the device.

Also, at such a voltage, hand held photography is no longer feasable. The solar cell array is therefore required only in brightness conditions which enable perfect and correctly exposed photographs to be taken.

in a development of the present invention, the liquid crystal display is switched off when the output voltage of the solar cell array falls below a level corresponding to an insufficient brightness level for taking hand held correctly exposed photographs.

Accordingly, when the liquid crystal display switches off it provides an indication to the user of the device that the brightness level is no longer adequate.

In another arrangement of the present invention the liquid crystal display includes an element for indicating under exposure which is activated when the output voltage of the solar cell array lies between said predetermined voltage and a voltage corresponding to the lower threshold value for hand held photography. In this arrangement, if the element for indicating under exposure is activated, it indicates to the user that the brightness intensity is no longer adequate for taking correctly exposed photographs.

On the other hand, if this element is not activated, this tells the user that the indicator device is no longer operating, and that the brightness level is less than the lower threshold for hand held photography.

In a further development of the present invention, the solar cell array also comprises the photosensitive element in the first oscillator and means are provided for matching the characteristics of the solar cell array to the spectral sensitivity of a film.

Advantageously, means are provided for storing the charge generator during a radiation of the solar cell array.

In a further development of the present invention, the two oscillators have frequency determining capacitors having low capacitance values so that their charge exchange current consumption is low and so that they can form part of the integrated circuit.

The present invention will now be described in more detail, by way of example, with reference to the accompanying drawings in which: Figure lisa circuit diagram of a solar cell array, first and second oscillators, and digital counter forming part of an indicator device embodying the present invention, Figure 2 is a circuit diagram of a computor circuit forming part of the indicator device of Figure 1, and Figure 3 is a circuit diagram of an indicator circuit forming part of the device of Figure 1.

Referring now to Figure 1,there is shown an array of solar cells 1 which is rigidly attached to the device.

The array 1 supplies current to a first oscillator comprising a silicon-photo-receiver 2, a timing capacitor 3, an amplifier 4, a trigger stage 5, which may be a schmitt trigger, a transistor 6 connected across the capacitor 3, and a resistor 7 connected between the base of the transistor 3 and the positive pole of the solar cell array 1.

The solar cell array 1 also supplies current to a second oscillator which comprises a capacitor 8, a resistor 9, and transistor 10 connected across the capacitor 8, a trigger stage 11, which may be a schmitt trigger, and a resistor 12 connected between the base of the transistor 10 and the positive pole of the array 1.

The output of the first oscillator is connected to one of the input terminals of a NAND-gate 13, the other input terminal of which is connected to the output of the second oscillator. The frequency of the second oscillator is determined by the resistor 9 and this oscillator determines the period of each measuring cycle. The frequency of the first oscillator is determined by the photo-receiver 2 and consequently varies in accordance with the intensity of light falling on this receiver. The frequencies of the two oscillators are matched in such a way that the frequency of the first oscillator remains high relative to the frequency of the second oscillator even in low, but still useful, light conditions.

The output of NAND-gate 13 is connected through a delay stage 14to the clock input of the digital counter 15. The output of the second oscillator is connected to an impulse forming stage 16 which comprises a NAND-gate 17, one input terminal of which is connected directly to the output of the second oscillator and the other input terminal of which is connected to the output of the oscillator through an inverting delay stage 18.

The output of the impulse forming stage 16 is connected to the reset input terminal of the digital counter 15. The digital counter 15 has nine output terminals 01, Q2, 03, 04, 05, 06, Q7, 08, and Q9.

The output of the impulse forming stage 16 is connected to a junction T.

Turning now to Figure 2, output terminal 02 of counter 15 is connected to the first input of a first AND-gate 19, terminal 03 is connected through an inverter 20 to the second input of AND-gate 19, and terminal Q4 is connected to the third input of AND-gate 19.

Terminal 03 is connected to the first input of a second AND-gate 21, terminal 04 is connected through an inverter 22 to the second input of AND-gate 21, and terminal 05 is connected directly to the third input of AND-gate 21.

Terminal Q4 is connected directly to the first input of a third AND-gate 23, terminal 05 is connected through an inverter 24 to the second input of AND-gate 23, and terminal OS is connected directly to the third input of AN D-gate 23.

Terminal 05 is connected to the first input of a fourth AND-gate 25, terminal OS is connected through an inverter 26 to the second input of AND-gate 25, and terminal Q7 is connected to the third input of AN D-gate 25.

Terminal O6 is connected directly to the first input of a fifth AND-gate 27, terminal 07 is connected through an inverter 28 to the second input of AND-gate 27, and terminal Q8 is connected directly to the third input of AND-gate 27.

Terminal Q7 is connected directly to the first input of a sixth AND-gate 29, terminal Q8 is connected through an inverter 30 to the second input of AND-gate 29, and terminal Q9 is connected directly to the third input of AN D-gate 29.

The first AND-gate 19 is associated with a memory RS flip-flop 31, the second AND-gate 21 is associated with a memory RS flip-flop 32, the third AND-gate 23 is associated with a memory RS flip-flop 33, the fourth AND-gate 25 is associated with a memory RS flip-flop 34, the fifth AND-gate 27 is associated with a memory RS flip-flop 35, and the sixth AND-gate 29 is associated with a memory flip-flop 36.

The junction T is connected through an inverter 37 to the clock inputs of the flip-flops 31 to 36. The S-inputs of flip-flops 31 to 36 are directly connected to the outputs of their associated AND-gates 19 to 29, and their R-input are connected to the outputs of their associated AN D-gates 19 to 29 through respective inverters 38 to 43.

The signals appearing at the R and S inputs of flip-flops 31 to 36 are fed to their Outputs on receiving a clock pulse from the output of inverter 37. Flip-flop 31 set when the binary number appearing at the output counter 15 reaches a value of 1010 (04,03, Q2, flip-flop 32 is set at 10100 (Q5, Q4, 03, 02, 01), flip-flop 33 is set at 101000 (Q6, 05, Q4, 03, 02, 01), flip-flop 34 is set at 1010000 (Q7, 06, Q5, 04, 03, 02, Q1), flip-flop 35, is set at 10100000 (08, 07,06, Q5, 04, Q3, 02, Q1), and flip-flop 36 is set at 101000000 (Q9, 08, Q7, Q6, 05, 04, Q3, Q2, Q1).

The Output of flip-flop 31 is connected to a terminal A, the Q-output of flip-flop 32 is connected to a terminal B, the Q-output of flip-flop 33 is connected to a terminal C, the Q-output of flip-flop 34 is connected to a terminal D, the Q-output of flip-flop 35 is connected to a terminal E, and the Q-output of flip-flop 36 is connected to a terminal F.

The AND-gates 19 to 29 and flip-flops 31 to 36 together with the associated inverters shown in Figure 2 form a computor circuit.

Referring now to Figure 3, there is shown the indicator circuit which is responsive to the signals appearing at the terminals A to F. Terminal A is connected to the first input of a NAND-gate 44, and terminal B is connected to the second input thereof through an inverter 45. Terminal B is also connected to the first input of a NAND-gate 46, and terminal C is connected to the second input thereof through an inverter 47.

Terminal C is also connected to the first input of a NAND-gate 48, and terminal D is connected to the second input thereof through an inverter 49.

Terminal D is also connected to the first input of a NAND-gate 50, and terminal E is connected to the second input thereof through an inverter 51. Terminal E is also connected to the first input of a NAND-gate 52, and terminal F is connected to the second input thereof through an inverter 53.

Terminals A to F are also connected to the input of an AND-gate 54.

The indicator circuit also includes a liquid crystal display 55. The display 55 comprises individual liquid crystal elements 56,57,58,59,60,61,62 and 63. Element 56 indicates under exposure, element 57 is associated with a shutter speed 1/30, element 58 is associated with a shutter speed 1/60, element 59 is associated with a shutter speed 1/125, element 61 is associated with a shutter speed 1/500, element 62 is associated with a shutter speed 1/000, and element 63 indicates over exposure. The output of AND-gate 54 is connected to the liquid crystal element 56.

The output of NAND-gate 44 is connected to the liquid crystal element 57.

The liquid crystal element 58 is connected to the output of a NOR-gate 64, one input of which is connected to the output of NAND-gate 44 and the other input of which is connected to the output of NAND-gate 46.

The liquid crystal element 59 is connected to the output of a NOR-gate 65, one input of which is connected to the output of an NAND-gate 46 and the other input of which is connected to the output of a NAND-gate 48. The liquid crystal element 60 is connected to the output of an NOR-gate 66, one input of which is connected to the output of NANDgate 48 and the other input of which is connected to the output of NAND-gate 50. The liquid crystal element 61 is connected to the output of a NOR-gate 67, one input of which is connected with the output of a NAND-gate 50 and the other input of which is connected to the output of a NAND-gate 52. The liquid crystal element 52 is connected directly to the output of NAND-gate 52. Terminal F is connected through an inverter 68 to the liquid crystal element 63 which indicates over exposure.

The signals which appear at the terminals A, B, C, D, E, and F are decoded in such a way that within the liquid crystal display 55, with the exception of element 56 which indicates under exposure and element 63 which indicates over exposure, there will always be two liquid crystal elements which are activated. The display device 55 could be associated with a pointer which is coupled with a shutter speed setting mechanism of the camera in which the exposure indicator device is mounted, the pointer being displaced along the elements of the display 55 during setting of the shutter speed.

The light which falls on the photo-sensitive receiver or diode 2 generates a current which is amplified in the amplifier 4. This amplifier current charges the capacitor 3. When the threshold potential of the trigger stage 5 is reached, its output goes high and consequently transistor 6 is rendered conductive and discharges the capacitor 4. The output of trigger stage 5 is connected to the base of transistor 6. The potential appearing at the input of trigger stage 5 will then fall and when it falls below the lower threshold value the transistor 6 will be rendered nonconductive. Thus, the frequency of this oscillator is determined by the charging current supplied to capacitor 3 and therefore depends on the light intensity falling on the diode 2. The frequency of this oscillator increases with increasing light intensity falling on the photo diode 2.The positive going edge of each pulse of the second oscillator enables the NAND-gate 13 thereby allowing the counter 15to count the pulses appearing at the output of trigger stage 5, which are related to the intensity of light falling on the photo diode 2, until the NAND-gate 13 is disenabled by the negative going edge of the pulse from the second oscillator. The pulses counted during each cycle of the second ascillator are available at the output of the counter 15 at terminals Q1 to Q9. These are then decoded in the computer circuit shown in Figure 2 and displayed by means of the indicator circuit shown in Figure 3.

For example, if 10 to 19 pulses are fed to the counter 15 during the time the NAND-gate 13 is enabled, the resulting shutter speed is between 1/30 and 1/60 seconds. The corresponding binary number is "1010". The binary number appearing at the end of the measuring cycle at output 01 to 09 of counter 15 is decoded in the AND-gates 19to 29 and stored in the flip-flops 31 to 36 in accordance with the pulses appearing at the output of inverter 37.

The circuit shown in Figure 1, the computer circuit shown in Figure 2, and the parts of the indicating circuit shown in Figure 3 within the chain dotted line 69 are formed as an integrated circuit, which may be complementary metal oxide silicon integrated circuit or an integrated injection logic circuit. The capacitance values of capacitors 3 and 8 in the first and second oscillators shown in Figure 1 are chosen to have a low value so that these capacitors may form part of the integrated circuit and so that their charge exchange current consumption is low.

In an alternative arrangement of the present invention, the solar cell array 1 and the photodiode 2 may be formed as a single element, and in this case filters are provided for matching the characteristics of the combined element to the spectral sensitivity of the film being used in the camera.

In another modification of the present invention, means may be provided for storing the charges generated by the solar cell array 1.

Claims (11)

1. An exposure indicator device for a photographic camera comprising a photosensitive measuring circuit constructed a a lower power integrated circuit, an indicator circuit driven by the measuring circuit and including a liquid crystal display, and a solar cell array providing powerfor the measuring circuit and the indicator circuit.

2. An indicator device as claimed in claim 1 in which the measuring circuit is constructed as an integrated injection logic circuit or a complementary metal oxide semi-conductor circuit.

3. An indicator device as claimed in claim 1 or claim 2 in which the measuring circuit comprises a first oscillator having a photo-sensitive frequency determining element, second oscillator having a non-photosensitive frequency determining element for determining the period of each measuring cycle, a digital counter responsive to the outputs of the first and second oscillators and a computor circuit responsive to the output of the counter and including a memory stage.

4. An indicator device as claimed in any one of the preceding claims in which the liquid crystal display is switch off when the output voltage of the solar cell array falls below a predetermined value, said predetermined value being high enough for operating the measuring and indicator circuits.

5. An indicator device as claimed in any one of the preceding claims in which the liquid crystal display is switched off when the output voltage of the solar cell array falls below a level corresponding to an insufficient brightness level for taking hand held correctly exposed photographs.

6. An indicator device as claimed in any one of the preceding claims in which the liquid crystal display includes an element for indicating under exposure which is activated when the output voltage of the solar cell array lies between said predetermined voltage and a voltage corresponding to the lower threshold value for hand held photography.

7. An indicator device as claimed in any one of the preceding claims in which the solar cell array also comprises the photosensitive element in the first oscillator and in which means are provided for matching the characteristics of the solar cell array to the spectral sensitivity of a film.

8. An indicator device as claimed in any one of the preceding claims including means for storing the charges generated during irradiation of the solar cell array.

9. An indicator device according to any one of the preceding claims in which the two oscillators have frequency determining capacitors having a low capacitance value so that their charge exchange current consumption is low and so that they can form part of the integrated circuit.

10. An exposure indicator device for a photographic camera substantially as hereinbefore described with reference to and as shown in the accompanying drawings.

11. A photographic camera including an indicator device as claimed in any one of the preceding claims.