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GB1502334A - Semiconductor data storage arrangements - Google Patents

Semiconductor data storage arrangements

Info

Publication number
GB1502334A
GB1502334A GB21857/75A GB2185775A GB1502334A GB 1502334 A GB1502334 A GB 1502334A GB 21857/75 A GB21857/75 A GB 21857/75A GB 2185775 A GB2185775 A GB 2185775A GB 1502334 A GB1502334 A GB 1502334A
Authority
GB
United Kingdom
Prior art keywords
silicon
layer
substrate
fets
sio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB21857/75A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1502334A publication Critical patent/GB1502334A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H10D84/813—Combinations of field-effect devices and capacitor only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)

Abstract

1502334 Integrated circuits INTERNATIONAL BUSINESS MACHINES CORP 21 May 1975 [28 June 1974] 21857/75 Heading H1K [Also in Division H3] A data store (see Division G4) is formed on a substrate 50 of P-silicon having bit lines B0, B1 formed of N-silicon and also forming the drain of FETs, the sources of which are formed of N-silicon at 51. The substrate is covered with arelatively thin layer 52 of SiO 2 /Si 3 N 4 which forms the gate dielectric of the FETs and the dielectric of the storage capacitors. A layer 54 of doped polycrystalline silicon has a resistivity of less than 1 kilohm/square and is connected to the substrate potential and serves as one of the capacitor electrodes over the source zone 51. Layer 54 also prevents undesirable inversion of the semiconductor surface. An intermediate insulating layer 56 of SiO 2 and gate metallization 55 are also applied extending as word lines WL orthogonally to the bit lines B0, B1.
GB21857/75A 1974-06-28 1975-05-21 Semiconductor data storage arrangements Expired GB1502334A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2431079A DE2431079C3 (en) 1974-06-28 1974-06-28 Dynamic semiconductor memory with two-transistor memory elements

Publications (1)

Publication Number Publication Date
GB1502334A true GB1502334A (en) 1978-03-01

Family

ID=5919184

Family Applications (1)

Application Number Title Priority Date Filing Date
GB21857/75A Expired GB1502334A (en) 1974-06-28 1975-05-21 Semiconductor data storage arrangements

Country Status (6)

Country Link
JP (1) JPS5428252B2 (en)
CH (1) CH581885A5 (en)
DE (1) DE2431079C3 (en)
FR (1) FR2276659A1 (en)
GB (1) GB1502334A (en)
IT (1) IT1038100B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4570241A (en) * 1981-10-30 1986-02-11 International Business Machines Corporation FET Storage with partitioned bit lines
EP1143453A3 (en) * 2000-02-29 2002-05-15 Fujitsu Limited Semiconductor memory device
US6449204B1 (en) * 2000-03-30 2002-09-10 Mitsubishi Denki Kabushiki Kaisha Dynamic semiconductor memory device capable of rearranging data storage from a one bit/one cell scheme in a normal mode to a one bit/two cell scheme in a twin-cell mode for lengthening a refresh interval
US7889541B2 (en) 2008-04-15 2011-02-15 Faraday Technology Corp. 2T SRAM cell structure

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5853512B2 (en) * 1976-02-13 1983-11-29 株式会社東芝 Method for manufacturing semiconductor memory device
JPS5922316B2 (en) * 1976-02-24 1984-05-25 株式会社東芝 dynamic memory device
US4040016A (en) * 1976-03-31 1977-08-02 International Business Machines Corporation Twin nodes capacitance memory
US4103342A (en) * 1976-06-17 1978-07-25 International Business Machines Corporation Two-device memory cell with single floating capacitor
CA1164710A (en) * 1978-05-09 1984-04-03 Edward J. Reardon, Jr. Phototropic photosensitive compositions containing fluoran colorformer
DE2837877C2 (en) * 1978-08-30 1987-04-23 Siemens AG, 1000 Berlin und 8000 München Method for producing a MOS-integrated semiconductor memory
DE2855118C2 (en) * 1978-12-20 1981-03-26 IBM Deutschland GmbH, 70569 Stuttgart Dynamic FET memory

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4570241A (en) * 1981-10-30 1986-02-11 International Business Machines Corporation FET Storage with partitioned bit lines
EP1143453A3 (en) * 2000-02-29 2002-05-15 Fujitsu Limited Semiconductor memory device
US6909644B2 (en) 2000-02-29 2005-06-21 Fujitsu Limited Semiconductor memory device
EP1619690A3 (en) * 2000-02-29 2007-10-17 Fujitsu Limited Semiconductor memory device
US6449204B1 (en) * 2000-03-30 2002-09-10 Mitsubishi Denki Kabushiki Kaisha Dynamic semiconductor memory device capable of rearranging data storage from a one bit/one cell scheme in a normal mode to a one bit/two cell scheme in a twin-cell mode for lengthening a refresh interval
US6925022B2 (en) 2000-03-30 2005-08-02 Renesas Technology Corp. Refresh-free dynamic semiconductor memory device
US7139208B2 (en) 2000-03-30 2006-11-21 Renesas Technology Corp. Refresh-free dynamic semiconductor memory device
US7889541B2 (en) 2008-04-15 2011-02-15 Faraday Technology Corp. 2T SRAM cell structure

Also Published As

Publication number Publication date
JPS513824A (en) 1976-01-13
DE2431079A1 (en) 1976-02-12
DE2431079C3 (en) 1979-12-13
DE2431079B2 (en) 1979-04-26
FR2276659B1 (en) 1980-01-04
IT1038100B (en) 1979-11-20
FR2276659A1 (en) 1976-01-23
CH581885A5 (en) 1976-11-15
JPS5428252B2 (en) 1979-09-14

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee