GB1593070A - Semiconductor storage devices and their operation - Google Patents

Description

(54) SEMICONDUCTOR STORAGE DEVICES AND THEIR OPERATION (71) We, INTERNATIONAL BUSINESS MACHINES CORPORATION, a Corporation organized and existing under the laws of the State of New York in the United States of America, of Armonk, New York 10504, United States of America do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to semiconductor storage devices and their operation.

According to one aspect of the invention, there is provided a method of operating a semiconductor field effect device so that it functions as a dynamic data storage device, the field effect device comprising a semiconductor substrate of one conductivity type, a source region and a drain region of opposite conductivity type disposed in said substrate and having a channel region therebetween, an interconnecting region of said opposite conductivity type disposed in said channel region extending from the surface of said substrate and interconnecting said source and drain regions, the arrangement being such that the top of said interconnecting region is nowhere contiguous with said substrate, and a gate electrode disposed in insulated spaced relationship with said channel region, the method comprising (operation 1) applying such a bias potential to said gate electrode and said substrate with respect to said source and drain regions that an inversion layer is created at the surface of said interconnecting region, thus rendering the device conductive, when the device is in a first, equilibrium state and a depletion layer is created between said source and drain regions, thus rendering the device non-conductive, when the device is in a second, quasi-equilibrium state; and (operation 2) applying a potential pulse to either said gate electrode or said source region to switch the device from said equilibrium state to said quasi-equilibrium state or vice versa.

According to another aspect of the invention, a memorycell comprises a semiconductor substrate of one conductivity type; first, second and third regions of opposite conductivity type disposed in said substrate, each of said first and second regions and said second and third regions having a channel region therebetween forming addressing and storage devices, respectively; an interconnecting region of said opposite conductivity type disposed in said channel region of said storage device extending from the surface of said substrate and interconnecting said second and third regions, the arrangement being such that the top of said interconnecting region is nowhere contiguous with said substrate; first and second gate electrodes disposed in insulated spaced relationship with the channel region of said addressing and storage devices respectively; means arranged to apply such a bias potential to said substrate and to the gate electrode of said storage device with respect to said second and third regions that an inversion layer is created at the surface of said interconnecting region, thus rendering the storage device conductive, when it is in a first, equilibrium state and a depletion region is created between said second and third regions, thus rendering the storage device non-conductive, when it is in a second quasi-equilibrium state; and means arranged to apply a potential pulse to the gate electrode of said addressing device to render it conductive and means arranged to apply such a potential pulse to the first region that when the addressing device is conductive the storage device is switched from said equilibrium state to said quasi-equilibrium state or vice versa.

How the invention can be carried into effect will now be described by way of example, with reference to the accompanying drawings, in which: Figure 1A is a partially schematic, partial cross-sectional view of a field effect transistor wherein the drain diffusion completely encircles the source diffusion and wherein the channel region extending between source and drain is ion implanted. The gate electrode which is disposed over the channel region atop an insulating layer is also concentric with the source and drain regions.

Figure 1 B is a partial cross-sectional, partially schematic view of the device of Figure 1 A showing one of two possible states into which the device can be placed with a given bias applied to the gate electrode and substrate of the device. Figure 1 B shows an equilibrium state for the device in which the channel region is conductive. An inversion layer of the same conductivity type as the substrate is shown at the surface of the device underneath the gate electrode.

Figure 1C is a partial cross-sectional, partially schematic view of the device of Figure 1 A, with the region 2 not shown, showing the other of two possible states the device may assume with a given potential on the gate electrode and substrate of the device. In Figure 1 C, the channel region is nonconducting inasmuch as a deep depletion region has been formed between the source and drain. The deep depletion state is quasi-stable and eventually decays so that the device assumes the state shown in Figure 1 B.

Figure 2A shows a band diagram which is representative of the state of the device shown in Figure 1 B. The band diagram is representative of an equilibrium state and shows the surface inversion of the semiconductor near the semiconductor oxide interface. The direction of the channel is into the page.

Figure 2B shows the energy diagram of the channel of the device of Figure 1 B which is taken along line 2B-2B of Figure 2A. This diagram clearly indicates that the channel of the device of Figure 1B is conductive.

Figure 2C is a band diagram which is representative of the state of the device shown in Figure I C when the channel thereof has been deeply depleted. Under such circumstances, the channel of the device of Figure 1C is nonconductive and a greater part of the applied voltage is dropped in the semiconductor than in the gate dielectric.

Figure 2D is an energy diagram representative of the condition of the channel of the device of Figure 1 C and is taken along the lines 2D-2D of Figure 2C. Figure 2D clearly shows the presence of a high potential barrier indicating that the channel of the device of Figure 1C is nonconductive.

Figure 3A shows the band diagrams obtained when the device of Figure 1 B is switched from its conductive state to the nonconductive state of Figure 1C. This is achieved by applying a positive pulse potential to the gate of the device of Figure 1B.

Figure 3B shows the band diagrams obtained when a negative potential is applied to the gate of the device of Figure I C converting it from its nonconducting state to the conducting state shown in Figure 1B.

Figure 4A is a schematic diagram of the device of Figure 1 A showing a circuit arrangement which permits the reading and writing of that device when positive and negative signals which turn the device off and on, respectively, are applied to the gate electrode.

Figure 4B shows the write-cycle waveforms which, when applied to the gate of the device of Figure 4A, turn the channel off and on, respectively.

Figure 5A is a schematic diagram of a circuit similar to that shown in Figure 4A except that write and read pulses are applied to the source of the device rather than the gate electrode of the device.

Figure 5B shows the write and read waveforms which are applied to the source of the device of Figure 5A.

Figure 6 is a schematic diagram which shows the utilization of the device of Figure 1 A in a memory cell environment. In addition to the device of Figure 1A, the circuit includes an addressing FET; the gate and source of which are connected to the word and bit lines of a memory array.

Figure 7 shows the layout of the memory cell of Figure 6 in a bit-organized memory array configuration wherein the extremities of the storage device channel region are isolated from the substrate by recessed oxide.

DESCRIPTION OF PREFERRED EMBODI MENTS Referring now to Figure 1 A, there is shown therein a partially schematic, partial crosssectional drawing of a buried channel MOS transistor 1 which, because of its storage capabilities, can be utilized as a nondestructive readout dynamic memory cell. Transistor 1 may be of the type that utilizes a circular configuration for source, drain and channel regions. While not the only sort of configuration available, a transistor with such a circular or annular configuration is not subject to leakage of carriers into the surface of the channel region from the substrate as would be the case with an open-channel device. The rationale behind this statement will become clear as the description proceeeds. Let it suffice to say for the present that for proper operation of the arrangements of the present application, the upper surface of the channel region of the device should be isolated from the substrate. In Figure 1A, buried channel 2 of N conductivity type is shown disposed between N+ conductivity type source and drain regions 3, 4, respectively, all of which are disposed in a P conductivity type substrate 5. Buried channel 2 interconnects source 3 and drain 4 and is spaced from a gate electrode 6 by a thin dielectric or oxide layer 7. Transistor 1 may be fabricated by techniques well known to those skilled in the semiconductor fabrication art using wellknown photolithographic and etching techniques as well as well-known difussion and ionimplantation techniques. In a representative device, substrate 5 may be made of a semiconductor such as silicon doped with with an acceptor impurity such as sodium or boron to provide a substrate having a resistivity of 1020 ohm-cm. Sodium or boron concentrations of 7 x 1014 - 1.4 x 1015 atoms/cc provide the desired resistivity. Source 3 and drain 4 are formed in the usual way by diffusing a donor impurity such as phosphorous into substrates at a concentration of 1020 atoms/cc. Buried channel 2 is conveniently formed by ion implantation using phosphorous as a dopant.

Buried channel 2 has a dosage of 5 x 101 atomslcn;2 and the implantation can be carried out at 160 keV in a well-known manner prior to the formation of gate electrode 6. The resulting implantation exhibits a maximum at an Rp X 1500 A and aARp X 600 A. It should be appreciated that the buried channel 2 may also be formed by diffusion or other techniques well known to those skilled in the semiconductor fabrication art. Gate electrode 6 may be formed of a metal such as aluminum or may otherwise be formed of polycrystalline silicon. The resulting device 1 may be characterized as a buried channel MOS device having an enclosed channel the upper surface of which is isolated from the substrate.

Any memory device must be capable of assuming at least two states which can be differentiated from each other and, in addition, must be capable of maintaining either of the states under the same conditions indefinitely or for at least a time which is sufficiently long relative to its state being changed that it can be characterized as being capable of maintaining its two states indefinitely. The device of the present application fits into the latter category to the extent that one of its states is quasi-stable and ultimately decays or returns to its other possible state which is a stable state. The stable state of the device of the present application is shown in the partially schematic, partial crosssectional view of Figure 1 B. Portions of Figure 1 B which are the same as the portions shown in Figure 1A have been identified by the same reference characters in Figure 1 B.

Gate electrode 6 and substrate 5 in Figure 1B are shown having DC biases of -10 volts applied to each of these elements. Under such circumstances, and assuming the bias has been applied for a relatively long period of time, an inversion layer 8 is formed at the surface of substrate 5 adjacent dielectric layer 7 and in buried channel 2. Inversion layer 8 is of opposite conductivity type to that of buried channel 2 and is the same as the conductivity type of substrate 5. The presence of inversion layer 8 indicates the equilibrium or stable state of device 1. Inversion layer 8 results from the fact that holes, from whatever source, are attracted into the depleted channel region and congregate at the surface of the devive forming a P-type surface inversion layer. The remainder of implanted region 2 remains N-type and interconnects the N+ conductivity type source 3 and drain 4. Device 1 of Figure 1B is now in the conducting or "ON" condition and current can flow between diffusions 3 and 4. Under the bias conditions shown, the total voltage applied to gate electrode 6 is dropped across dielectric 7 inasmuch as the applied electric field is terminated on the positive charges present in inversion layer 8.

Assuming that the ON or conducting state is a binary "1", applying a more negative bias to the gate will not eliminate the P conductivity type surface inversion layer 8 and the device remains conductive.

Another possible state is the "OFF" or non conducting or quasi-equilibrium state which is shown in Figure 1 C. Figure 1 C is similar to Figure 1B except that buried layer 2 and inver sion layer 8 are not shown and a depletion region 9 is shown between diffusions 3, 4.

Depletion region 9 contains no mobile charge carriers, the latter having been swept out of inversion layer 8 and layer 2 as a result of the formation of depletion region 9. Because of the absence of mobile charge carriers, no current can flow between diffusions 3, 4 and device 1 of Figure 1 C is nonconductive.

To form a depletion region 9, a positive voltage pulse is superimposed on the negative bias applied to gate electrode 6. The positive voltage drives out positive mobile charge car riers which are present in inversion layer 8. This action leaves the negative mobile charge carriers which have a low concentration relative to the positive charge carriers. When the pulsed posi tive voltage is reduced to the original negative bias level, the remaining negative mobile charge carriers are driven out thereby depleting the affected region of all mobile charge carriers.

Under these circumstances, the electric field applied via electrode 6 terminates on positive charges near the extremity of depletion region 9 and practically the total voltage drop appears across depletion region 9 in silicon substrate 5.

Device 1 is now nonconducting or in a quasistable state and no current flows inasmuch as no mobile charge carriers are present in the depletion region. This nonconducting state is characterized as quasi-stable because after a period of time which may amount to several minutes at room temperature, holes or positive charge enter the depletion region and device 1 returns to the stable state represented in Figure 1B with inversion layer 8 in implanted channel region 2 at the surface of substrate 5.

To change the state of the device of Figure 1 C from nonconducting to conducting, a negative pulse may be superimposed on the bias. By the injection of holes or other mechanisms, such as recombination, holes enter depletion region 9 and are accelerated to the surface of substrate 5 where they accumulate and reform inversion layer 8. The applied bias field now terminates on inversion layer 8; device 1 is in the state shown in Figure 1 B, and current can flow via negative mobile charge carriers between source 3 and drain 4.

Referring now to Figure 2A, there is shown a band diagram of the equilibrium or suface inversion condition of Figure 1B. In Figure 2A, the potential is shown vertically while distance into a silicon substrate is shown in a horizontal direction. A conductive region is depicted spaced from the silicon region by an oxide or dielectric region. To the extent that the diagram of Figure 2A represents elements shown in Figure 1 B, the equivalent regions in Figure 2A have been labeled with the same reference characters. Thus, the left-most region of Figure 2A represents gate electrode 6 while the rightmost region of Figure 2A represents P conductivity type substrate 5. These two regions are spaced from one another by dielectric or oxide layer 7. Inversion layer 8 is shown at the interface 10 between dielectric layer 7 and substrate 5. Sloping portion 11 in Figure 2A indicates that in the equilibrium or surface inversion mode of operation most of the applied potential is dropped across dielectric or oxide layer 7.

Figure 2B which shows the energy diagram of the device of Figure 1 B is taken along line 2B-2B of Figure 2A shows the energy distribution at source 3, drain 4 and buried channel 2.

From Figure 2B, it should be clear that because of the relatively low potential barrier in channel region 2, current can flow between source 3 and drain 4 with the application of a very small potential difference.

Figure 2C shows a band diagram for the deep depletion state exhibited by the device shown in Figure 1 C. Under the influence of the applied bias voltage Vg and after a positive pulse has been applied to gate electrode 6, the device of Figure 1C exhibits the band diagram shown in Figure 2C. It should be noted in Figure 2C that sloping portion 11 does not taper as sharply as it did in Figure 2A indicating that, in the deep depletion mode, only a small portion of the applied bias is dropped across dielectric or oxide layer 7. The application of positive potential on gate electrode 6 swept out the positive charges 8 of Figure 2A and, in addition, negative mobile charge carriers are removed upon the return of the pulsed positive voltage to the negative bias level. The sloped band edges 12 and quasiFermi level 13 in Figure 2D indicate that the greater part of the applied gate voltage is being dropped in the depletion region in silicon substrate 5.

Figure 2D shows an energy diagram similar to that shown in Figure 2B representative of the condition of the channel of the device of Figure 1C and is taken along lines 2D-2D of Figure 2C. Figure 2D clearly shows the presence of a high-potential barrier in the channel region 2 indicating that channel 2 of the device of Figure 1C is nonconductive. A comparison between Figures 2B and 2D clearly shows that two conditions, one conducting and the other nonconducting, can be achieved with the device of the present application. The condition shown in Figure 2B is stable and the device will remain in a conducting state as long as the required biases are maintained on the device. The state shown in Figure 2D, however, is quasi-stable and, after a long period of time (several minutes), the energy diagram of Figure 2D will decay to the energy diagram of Figure 2B by virtue of leakage, recombination or other phenomena.

Referring now to Figure 3A there is shown therein band diagrams obtained when the device of Figure 1B is switched from its conductive state to the nonconductive state of Figure 1 C. As indicated hereinabove, switching is achieved by applying a positive pulse potential to gate 6 of device 1 of Figure 1B. It should be noted that the left-most and right-most band diagrams are analogous to those shown in Figures 2A, 2C, respectively. The center band diagram in Figure 3A shows the band diagram of the devive in an intermediate state when a positive potential is applied to gate electrode 6.

The positive voltage on the gate produces a downward bending of the bands, pushing out the accumulated holes 8 and accumulating free electrons in implanted channel 2. While not specifically shown in Figure 3A, it should be appreciated that the transition of the positive potential back to the original bias level causes the free electrons in buried channel 2 to be swept out bending the bands upwardly as shown in the right-most diagram of Figure 3A under the influence of the negative potential bias. The device has now been switched from the conducting to the nonconducting state.

Figure 3B shows the band diagrams obtained in switching from the nonconducting to the conducting state under the influence of a negative pulse potential on gate electrode 6. In Figure 3B, the left-most and right-most band diagrams are analogous to the band diagrams of Figures 2C, 2A, respectively. With a device of the present application in the quasiequilibrium state as shown in the left-most band diagram of Figure 3B, buried channel 2 is totally depleted of all charge carriers and the potential applied is dropped mostly in the silicon. The electric field applied is terminated on positive charges near the boundary of the induced depletion region. Upon the application of a negative potential, the bands are bent upwardly indicating that a higher potential is being dropped in the silicon. The resulting higher field accelerates holes from whatever source toward interface 11 between oxide layer 7 and silicon substrate 5. At the same time, negative mobile charge carriers which are present as a result of recombination and leakage are driven away from the same interface 10. Upon the transition from the higher pulsed negative potential to the normal negative potential bias, the bands move downwardly indicating that a smaller amount of the applied potential is being dissipated in the silicon while a greater amount is being dropped across oxide 7. The applied field terminates on positive carriers which have accumulated at the oxide-semiconductor interface and remain there as inversion layer 8 in a stable equilibrium condition. The device of the present application has thus been switched from a nonconducting to a conducting state by the application of a negative pulse potential on gate electrode 6.

Referring now to Figure 4A, there is shown therein a circuit arrangement including the device of Figure 1A which permits the reading and writing of that device when positive and negative signals which turn the device off and on, respectively, are applied to the gate electrode. Thus, in Figure 4A device 1 shows a -10 volt bias applied to gate electrode 6 and a -10 volt bias applied to substrate 5. Source 3 is shown grounded while drain 4 is connected to ground via a resistor 14 and a battery 15 which is utilized as a source of current flow between source 3 and drain 4 when device 1 is conductive. A read line 16 which senses the voltage drop across resistor 14 when device 1 is conductive is connected to drain 4. To change the state of device 1, positive and negative write cycle waveforms similar to that shown in Figure 4B may be applied to gate electrode 6 of device 1. As discussed hereinabove in connection with all the foregoing figures, if device 1 is nonconductive it can be rendered conductive by applying the negative going waveform 17 of Figure 4B to gate electrode 6 and, if device 1 is conductive, it can be rendered nonconductive by applying the positive going waveform 18 of Figure 4B to gate electrode 6. At this point, it should be obvious that if device 1 of Figure 4A is conducting, current will flow through it via source 3, buried channel 2 and drain 4. A potential drop in resistor 14 can then be sensed via read line 16. With device 1 nonconductive, of course no current will flow in device 1.

Referring now to Figure 5A, a schematic diagram of a circuit similar to that shown in Figure 4A is shown except that the write and read pulses utilized are applied to source 3 of device 1 rather than to gate electrode 6 of device 1. As is well known in the field effect transistor art, if pulses of opposite polarity to those applied to the gate of a field effect transistor are applied to the source of the same transistor, similar device operation can be expected. Thus, using the arrangement of Figure SA, a positive pulse 19 as shown in Figure 5B applied to source 3 of device 1 will render it conductive while a negative pulse 20 shown in Figure 5B will render device 1 nonconductive.

When device 1 is conductive, a positive read pulse 21 as shown in Figure 5B applied to source 3 will produce a momentary voltage drop in resistor 14 which can be sensed via read line 16. At this point, it should be appreciated that the nonconductive conditions of the circuits of Figure 4A, 5A are quasiequilibrium states and, that after a reasonably long period of time in the range of several minutes, this quasiequilibrium state will decay to the equilibrium, conductive state discussed hereinabove. Under the usual operating circumstances, however, it is expected that devices in the nonconducting or quasiequilibrium state will be rewritten with either new information or can be refreshed to preserve the information in a device for as long as required. In the usual case, refreshing can be carried out by reading out a device; sensing the condition of the device, and rewriting the device to the same condition.

Referring now to Figure 6, there is shown therein a schematic diagram of a circuit which shows the utilization of the device of Figure 1A in a memory cell environment. In addition to the device of Figure 1 A, the circuit includes an addressing FET, the gate and source of which are connected to the word and bit lines, respectively, of an associated memory array.

Memory cell 22 of Figure 6 includes a buried channel MOS transistor 1 similar to that des cribed in connection with Figure 1 A above.

MOS transistor 1 includes a buried channel 2, source 3, drain 4, gate electrode 6 and dielectric layer 7. Source 3 of transistor 1 is shown in Figure 6 as being common with the drain of an addressing transistor 23. Addressing transistor 23 includes a source diffusion 24 and a gate electrode 25 which is interposed between diffusions 3, 24 and spaced from an underlying channel region by a dielectric or oxide layer 26. Diffusion 24 is connected via interconnection 27 to a memory array bit line 28 while gate electrode 25 of device 23 is connected via an interconnection 29 to a memory array word line 30. Addressing FET 23 is operated so that it is ordinarily nonconducting until an appropriate potential from pulsed source 31 is applied to gate electrode 25 via word line 30. Once addressing FET 23 has been rendered conductive, potentials from pulsed source 32 may be applied via bit line 28 and interconnection 27 to diffusion 24. Because addressing device 23 is now conductive, current flows to common diffusion 3 and, using the potentials and writing scheme shown in Figures 5B and 5A, transistor 1 may be placed into either of its two possible states and that state may be read out. Utilizing the arrangement of Figure 6 or Figures 4A and 5A for that matter, it should be appreciated that read-out is nondestructive in character. It should also be appreciated that while only a single cell 22 has been shown in Figure 6, a plurality of similar cells may be connected in array form to other bit lines 28 and word lines 30 and addressed and written and read in the manner described.

Referring now to Figure 7, there is shown a layout of the memory cell of Figure 6 in a bit organised memory array wherein the extremities of the storage device channel region are isolated from the substrate by a recessed oxide. As should be obvious from what is shown in Figure 7, the layout does not incorporate the annular device of Figure 1 A but rather includes what may be characterized as an open-channel structure, the upper channel surfaces of which are isolated from the substrate by a recessed oxide.

The recessed oxide technique permits the use of open-channel devices by effectively terminating the channel regions of both the storage device 1 and the addressing FET 23 with a dielectric formed by silicon regrowth to form silicon dioxide in a manner well known to those skilled in the semiconductor art.

Referring now in more detail to Figure 7, the elements of Figure 7 will be related to the elements of Figure 6 by utilizing the same reference characters. Thus, bit line 28 which is shown connected to diffusion 24 via interconnection 27 in Figure 6 is shown in Figure 7 by diffusion 24 and is otherwise identified therein as bit line. In Figure 6 word line 30 is shown connected to gate electrode 25 via interconnection 29. Word line 30 is identified by both terminologies in Figure 7 and that portion of word line 30 which constitutes gate electrode 25 for device 23 is identified as such in Figure 7. Common diffusion 3 is shown disposed in substrate 5 adjacent gate electrode 25. Gate electrode 6 which in the embodiment of Figure 7 is preferably a silicon gate is disposed over ion-implanted regions 2 and is adjacent a diffusion 4 disposed in substrate 5 which forms the grounded drain diffusion of storage device 1.

The shaded regions shown in Figure 7 are intended to represent those areas of substrate 5 which have been regrown to form a recessed oxide (ROX). From this, it should be clear that

Claims (13)

**WARNING** start of CLMS field may overlap end of DESC **. the channel regions of both the storage device 1 and the addressing FET 23 with a dielectric formed by silicon regrowth to form silicon dioxide in a manner well known to those skilled in the semiconductor art. Referring now in more detail to Figure 7, the elements of Figure 7 will be related to the elements of Figure 6 by utilizing the same reference characters. Thus, bit line 28 which is shown connected to diffusion 24 via interconnection 27 in Figure 6 is shown in Figure 7 by diffusion 24 and is otherwise identified therein as bit line. In Figure 6 word line 30 is shown connected to gate electrode 25 via interconnection 29. Word line 30 is identified by both terminologies in Figure 7 and that portion of word line 30 which constitutes gate electrode 25 for device 23 is identified as such in Figure 7. Common diffusion 3 is shown disposed in substrate 5 adjacent gate electrode 25. Gate electrode 6 which in the embodiment of Figure 7 is preferably a silicon gate is disposed over ion-implanted regions 2 and is adjacent a diffusion 4 disposed in substrate 5 which forms the grounded drain diffusion of storage device 1. The shaded regions shown in Figure 7 are intended to represent those areas of substrate 5 which have been regrown to form a recessed oxide (ROX). From this, it should be clear that channel region 2 and the channel under gate electrode 25 are terminated at the ends thereof by recessed oxide thereby isolating the channel regions from substrate 5 so that leakage paths which would destroy the deep depletion operation of an unisolated device are eliminated. While not specifically shown in Figure 7, it should be appreciated that devices 1 and 23 can be repeated horizontally as well as vertically to form an array of meory cells in the usual manner. The activation of a typical device 1 utilizes approximately 5 volt positive and negative excursions for a period of approximately 2 microseconds. Read signals having an amplitude of approximately 2 volts have been found to be sufficient. These parameters are however not critical and wide variations may be achieved depending upon the design parameters and the semiconductor materials utilized. While only N channel devices have been utilized in connection with the above-described figures, it should be appreciated that P channel counterparts of the device and memory cell described hereinabove can be fabricated with opposite type semiconductor materials and that such devices and memory cells may be actuated with polarities opposite to those shown in Figures 4B and 5B. Finally, it should be appreciated that because of their long retention time in the nonconductive or quasistable state and the nature of the decay to the equilibrium or stable state, the devices described hereinabove can also be used as photon counters and light integrators. Incident light which impinges on a gate electrode which may be transparent and penetrates to the semiconductor surface depletion layer will produce electron-hole pairs for each impinging photon. The holes will be accumulated at the silicon surface and electrons settled in the channel and made available for conduction. The formation of photo-generated characters is cumulative. Thus, by sensing the conductivity of the channel, one can measure quantitatively the presence of the photon dosage. It should be appreciated that for such electronhole pair generation and separation the polarization potential accelerates the decay of the deep depletion of the channel regions. The maximum number of photons which can be counted is equal to the number of electrons depleted by the gate in the deep depletion state. There has been described a single memory device with nondestructive read-out. In addition, a device with a relatively long retention time requiring infrequent refreshing has also been provided. Also, because the read signal strength is determined by the width-to-length ratio rather than the area of the storage device, its size is only limited by the capabilities of the photolithography technique utilized. Also, very little stand-by power is required. WHAT WE CLAIM IS:

1. A method operating a semiconductor field effect device so that it functions as a dynamic data storage device, the field effect device comprising a semiconductor substrate of one conductivity type, a source region and a drain region of opposite conductivity type disposed in said substrate and having a channel region therebetween, an interconnecting region of said opposite conductivity type disposed in said channel region extending from the surface of said substrate and interconnecting said source and drain regions, the arrangement being such that the top of said interconnecting region is nowhere contiguous with said substrate, and a gate electrode disposed in insulated spaced relationship with said channel region, the method comprising (operation 1) applying such a bias potential to said gate electrode and said substrate with respect to said source and drain regions that an inverse layer is created at the surface of said interconnecting region, thus rendering the device conductive, when the device is in a first, equilibrium state and a depletion layer is created between said source and drain regions, thus rendering the device non-conductive, when the device is in a second, quasi-equilibrium state; and (operation 2) applying a potential pulse to either said gate electrode or said source region to switch the device from said equilibrium state to said quasiequilibrium state or vice versa.

2. A method as claimed in claim 1 for operating a device having source and drain regions of the N-conductivity type, in operation 2 of which a positive potential pulse is applied to said gate electrode to switch the device from said equilibrium state to said quasi-equilibrium

state and a negative potential pulse is applied to said gate electrode to switch the device from said quasi-equilibrium state to said equilibrium state.

3. A method as claimed in claim 1 for operating a device having source and drain regions of the N-conductivity type, in operation 2 of which a negative potential pulse is applied to the source region to switch the device from said equilibrium state to said quasi-equilibrium state and a positive potential pulse is applied to the source region to switch the device from said quasi-equilibrium state to said equilibrium state.

4. A method as claimed in any preceding claim when used for operating a device in which one of said source and drain regions surrounds the other of those regions forming an annular channel region and wherein said gate electrode is annular, said source and drain regions and said gate electrode forming an annular field effect transistor.

5. A method as claimed in any of claims 1 to 3, when used for operating a device in which there is means disposed at the extremities of said interconnecting region for isolating the top thereof from said substrate.

6. A method as claimed in claim 5, when used for operating a device in which said means for isolating includes a recessed oxide region disposed at the extremities of said interconnecting region.

7. A memory cell comprising a semiconductor substrate of one conductivity type; first, second and third regions of opposite conductivity type disposed in said substrate, each of said first and second regions and second and third regions having a channel region therebetween forming addressing and storage devices, respectively; an interconnecting region of said opposite conductivity type disposed in said channel region of said storage device extending from the surface of said substrate and interconnecting said second and third regions, the arrangement being such that the top of said interconnecting region is nowhere contiguous with said substrate; first and second gate electrodes disposed in insulated spaced relationship with the channel region of said addressing and storage devices respectively; means arranged to apply such a bias potential to said substrate and to the gate electrode of said storage device with respect to said second and third regions that an inversion layer is created at the surface of said interconnecting region, thus rendering the storage device conductive, when it is in a first, equilibrium state and a depletion region is created between said second and third regions, thus rendering the storage device nonconductive, when it is in a second quasiequilibrium state; and means arranged to apply a potential pulse to the gate electrode of said addressing device to render it conductive and means arranged to apply such a potential pulse to the first region that when the addressing device is conductive the storage device is switched from said equilibrium state to said quasi-equilibrium state or vice versa.

8. A memory cell as claimed in claim 7, in which there is means disposed at the extremities of said interconnecting region for isolating the top of said interconnecting region of said storage device from said substrate.

9. A memory cell as claimed in claim 8, in which said means for isolating includes a recessed oxide region disposed at the extremities of said interconnecting region of said storage device.

10. A memory including a word line, a bit line and a memory cell as claimed in any of claims 7 to 9, in which the gate electrode of said addressing device is connected to the word line and the gate electrode of said storage device is connected to said bit line.

11. A method as claimed in claim 1, substantially as described with reference to Figures 4A and 4B or Figures 5A and 5B of the accompanying drawings.

12. A memory cell circuit substantially as described with reference to Figure 6 of the accompanying drawings.

13. A semiconductor storage arrangement comprising an array of memory cells devices as claimed in claim 7, substantially as described with reference to Figure 7 of the accompanying drawings.