GB1589444A - Electrical communication system - Google Patents

Description

(54) ELECTRICAL COMMUNICATION SYSTEM (71) We, FORD MOTOR COMPANY LIMITED, of Eagle Way, Brentwood, Essex CM13 3BW, a British Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a electrical communication systems and is particularly, but not exclusively, intended for use in motor vehicles.

Conventional practice in motor vehicles has been to provide each powered device (light, horn, windscreen wiper motor, etc.) with its own power lead and associated driver's control switch, and to provide a number of warning and indicating instruments (fuel gauge, tachometer, oil pressure warning, etc.) each connected to an appropriate sensor by separate wiring. This gives rise to wiring looms of considerable complexity and cost, and which have a poor reliability. It is also necessary to fabricate and stock different wiring harnesses for each model of vehicle.

There have hitherto been a considerable number of proposals to overcome these problems by using a common channel interconnecting all electrically powered devices and monitoring devices with a central control station, information being passed along the channel by multiplexing techniques. None of these proposals has yet been put into practice in volume vehicle production, principally for reasons of cost, and/or complexity. The factors which can be identified as necessary for a commercially viable system are:-- (a) the system must be mechanically simple and robust.

(b) the number of different components required must be kept to a minimum.

(c) the system must be sufficiently fast to maintain information such as road and engine speed sufficiently up to date in real time for the purposes of the driver.

(d) it must be possible to control at least 50 functions and to receive information from a similar number of sensors.

(e) there must be signal security which prevents spurious signals caused by interference effecting erroneous operation of controlled devices.

Of the systems previously proposed, some have been too slow or have too small a channel capacity to be suitable for use in vehicles, while others have achieved the required speed and channel capacity by using long trains of pulses at high repetition rates which requires the use of high frequency components with attendant expense. Other systems are unsuitable because they require a number of signal-carrying conductors, which increases cost and the risk of incorrect connection.

The invention accordingly seeks to provide a communication system which overcomes or reduces the disadvantages of the prior art proposals.

According to the invention there is provided an electrical communication system comprising: - a signal bus; a master station arranged to transmit on the signal bus pulse signals divided into serial information frames; a plurality of peripheral stations each connected to the signal bus for actuation in response to a given information frame; and a corresponding plurality of connector means each electrically connecting a respective peripheral station to at least one sensor and/or controlled device and each including address setting means which sets a code determining the information frame to which that station responds.

An embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of an information handling system for use in a motor vehicle; Figure 2 is a detailed circuit diagram of one of the peripheral stations of Figure 1; Figure 3 shows a typical pulse train used in the apparatus of Figures 1 and 2; Figure 4 is a perspective view of a peri pheral station in position on a bus member of the system; Figures 5 to 7 and 9 are more detailed circuit diagrams of parts of the circuit of Figure 2; and Figure 4a is a plan view, partly in section of the bus and peripheral station of Figure 4 with a top cover of the peripheral station removed; Figure 8 illustrates wave forms in the circuit of Figure 7.

Referring to Figure 1, the system has a power bus 10 in circuit with a storage battery 12. The power bus 10 is formed by a single conductor, the return circuit being provided via vehicle earth. A signal bus 14 is associated with the power bus 10, and also compriscs a single conductor. The buses 10 and 14 are molded into a single insulating sheath 16 (Fig. 4) to form a unitary bus member which may rcadily be passed around a vehicle in a convenicnt route.

A master station 18 is connected to the buses 10 and 14, and to a vehicle control panel 20. Sixteen peripheral stations 22 are each connected to the buses 10 and 14.

Each peripheral unit is connected by external leads to up to four controlled devices and up to four sensors; by way of examplc, one of the stations 22 in Figure 1 is shown connected to a headlight HL, a direction indicator light DL, a temperature sensor TS and an oil pressure sensor PS. The connections of the other peripheral stations 22 are not shown, for clarity of the drawing.

The control panel 20 contains the usual control switches, warning lights and instru mcnts for use by the driver. The master station 18 scans the driver-actuated controls in a sequential manner and transmits an addrcssed signal which is acted upon by the appropriate peripheral station to activate or dc-activate the desired device. At the same time, the outputs of sensors for functions such as oil pressure, coolant temperature, road speed etc. are coupled to the cor rcsponding peripheral stations 22 and are thence repetitively called up by the master station 18, decoded, and displayed as appro private on warning lights and instruments on the control panel 20.

The manner in which information handling is accomplished in the peripheral stations will now be discussed with reference to Figures 2 and 3.

Figure 3 shows the voltage level of a typical signal on the signal bus 14. The voltage at any instant is controlled at one of four levels, labelled A, B, C and D. Level A is suitably tied to the vehicle earth (ground) voltage. The master station 18 includes a clock circuit which cyclically generates synchronising (sync) and clock pulses. Sync pulses are set at level D and occur once per complete scan (in this case 16 frames). Clock pulses are at level C and subdivide each frame into equal time slots, in this embodiment eight in number.

Information is conveyed by controlling the signals within the time slots at levels A and B.

Turning to Figure 2, the circuit of a single peripheral station 22 is shown. It should be noted that the stations 22 have identical circuitry. This simplifies stockholding and installation and assists in reducing costs. The circuit of Figure 2 has an input at 24 from the signal bus 14. The power bus 10 may be connected to powered devices via parallel bistable gates 26 controlled by the remainder of the circuit. The signal input at 24 passes to an amplitude discriminator 28 which has four outputs enabled respectively by signal levels C, D, (C or D) and (B or C). The receipt of a signal at level (C or D), i.e. a sync or clock pulse, causes an output pulse to be passed to an eight-way selector 30 which in turn passes every eighth pulse to a 4-bit counter 32. The bits of the counter 32 are connected in parallel to a decode circuit 34. The decode circuit 34 has an address set externally, as will be described below, over leads 36.

It will be seen that the counter 32 is incremented once for every eight clock (and sync) pulses, i.e. once per frame. When the count held by the counter 32 is that set via the leads 36, the decode circuit generates an output on line 38 for eight time slot periods, i.e. for one frame period. Line 38 is connected in parallel to gates G1-O8. These gates are also connected to sequential outputs of the eight-way selector 30, each output being enabled for one time slot period. Thus, when the particular station 22 receives an information frame corresponding to the address code set, the gates G1--G8 are sequentially enabled each for one time slot.

Reccived signals of level (B or C) are passed by the amplitude discriminator to a pulse width discriminator 40 whose function is to separate the clock pulses, which are of lesser duration, from time slot information.

Signals at level B are passed by output 42 to gates G1--G4 in parallel and are then used, via a command and verify circuit 44 to be described, to enable the gates 26.

Ignoring for the moment the command and verify circuit 44, the operation is thus that the controlled devices connected to terminals 1, 2, 3, 4 are turned on by B-level signals in time slots 1, 2, 3, 4 respectively and are turned of by A-level signals in these slots.

Similarly, inputs from sensors connected to terminals 5, 6, 7, 8 are sequentially gated by gates G5--G8. Such inputs may be either on/off or analog. The gated sensor signals pass to a pulse width modulator 46 which generates an output signal onto the signal bus 14 during time slots 5, 6, 7, 8. A typical set of output signals is shown in Fig. 3. Time slots 6 and 7 are occupied by tell-back signals monitoring the condition of devices controlled by the signals in time slots 2 and 3. Slot 6 represents an "off" tell-back signal and is wholly occupied by level A signal.. Scot 7 represents "on" and is wholly occupied by level B signal. Slots 5 and 8 are exemplarily shown as carrying analog coolant temperature and oil pressure signals.

These are pulse width modulated, the fraction of the time slot occupied at level B representing a fraction of a predetermined full scale deflection for that signal. The timing of the output of the pulse width modulator 46 is synchronised with the time slots 5-8 by C-level or clock pulses switched by the amplitude discriminator over line 48.

The purpose of the command and verify circuit 44 is to provide signal security. This circuit operates in conjunction with a sync detector 50 connected to receive sync pulses from the amplitude discriminator 28. The sync detector 50 is also connected to the 4-bit counter 32 by a line 52. On receipt of the sync pulse, the counter 32 should reset to zero, and the counter is so constructed that on resetting it transmits a pulse over line 52 to the sync detector 50. If both pulses arrive simultaneously, the sync detector emits a gating pulse on line 54 to the command and verifying circuit 44.

The command and verify circuit comprises four channels, each connected between one of the gates G1G4 and the respective output terminals 1--4. One such channel is shown in Fig. 5. The signal from gate G is applied over line 55 and is held in a resettable store 56, which may for instance be a bistable multivibrator. The stored signal is compared with the next signal gated to that channel by a comparaor 58. If the two values agree, an enable signal passes by line 60 to a gate 62. The gate 62 is also connected to receive the gating pulse on line 54 from the sync detector 50, and to receive signals over line 64 from the pulse width discriminator 40. The first of these is provided to block execution of commands where there is a failure of synchronism in the system, and the second to ensure that a command signal is passed only during a suitable time slot.

Thus a command signal will not be passed by the circuit 44 to the controlled device unless (1) the same signal is received twice in succession and (2) the address decode is operating correctly in synchronism with the master station. The first of these is principally a safeguard against a signal which is correctly timed but in which a positive pulse is dropped, while the second is of particular use in dealing with the case where an interference-induced spike appears on the signal bus and produces lack of synchronism. If either of these conditions is not met, the signal to the appropriate gate 26 is blocked and the controlled device continues in its pre-existing state.

The sync detector 50 is also connected to the 4-bit counter 32 to reset the latter on receipt of a sync pulse. (If the system is correctly in synchronism, the counter 32 will also be recycling to zero of its own accord at the same time).

It will be seen that this embodiment is capable of controlling 64 functions and of monitoring 64 sensors. Suitably, each information frame occupies 8 ms, giving a total cycle time of 128 ms. Since two consecutive identical signals are required to actuate controlled devices, the maximum delay in switching on or off is 256 ms. Readouts to the driver are updated every 128 ms.

These speeds are sufficiently fast to be practically instantaneous from the driver's point of view while not requiring high pulse repetition rates.

Turning to Figures 4 and 4a, one possible physical form of peripheral station is shown.

The circuitry is encapsulated in a housing 164 which is formed with a recess dimensioned to accommodate the sheath 16. A cover 65 is hinged at 66 to the housing 164 and may be locked shut by spring steel arms 67. Connecting blades 68 extend from the housing 164 to effect connection with the buses 10 and 14. In use, slots for the blades 68 are preformed at suitable locations on the sheath 16 and the bus memlber is positioned in the vehicle. At each station, a housing 164 is arranged in a position to receive the bus member with the connecting blades in contact with the buses 10 and 14.. The housing is then secured to a vehicle body panel (not shown) as by self-tapping screws 69 passed through a metal strap 70 secured to the housing 164 and supporting the arms 67. The strap 70 and screws 69 suitably act as an electrical ground connector and heat sink.

When the cover 65 is closed, the peripheral station also acts as a retainer for the bus member.

The connection to the associated devices and sensors is via a flexible printed circuit 71. This is located by means of pins 72 on the housing 164 passed through apertures 73 in the flexible printed circuit 71. Contact strips 74 on the housing 164 are provided for connection to the conductors of the circuit 71. The housing 164 is also provided with contacts 75 connected to the address decode circuit 34. A corresponding number of conductive strips 77 are formed on the circuit 71 and are interconnected at 79. The address for a given station is encoded on its circuit 71 by drilling or punching through selected strips 77 between the position of the respective contact 75 and the interconnection 79.

In the embodiment shown, five strips 77 are provided, enabling sixteen addresses to be encoded.

Figure 6 illustrates a preferred form of amplitude discriminator. A resistor chain 76, 78, 80, 82 connected across power supply lines 84, 86. Supply line 86 is grounded and is thus at voltage level A. The resistors 76 83 are selected to give voltage levels B, C and D at the resistor junctions, and these are fed as inputs to respective comparators 88, 90, 92. The input signal on line 24 is fed in parallel to the comparators 88-92. The presence of voltage levels B, C and D is thus detected and results in an output at the respective comparator, these outputs being gated by an exclusive-OR gate 94 and OR gates 96, 98 to give the required outputs of C, D, (C or D) and (B or C).

A preferred form of pulse width discriminator is shown in Figure 7. The discriminator is required only to differentiate between wide and narrow pulses, and the waveforms for each of these at various points in the circuit are shown in Fig. 8.

The input from the amplitude discriminator 28 is applied in parallel to a monostable multivibrator 100 and an invcrtcr 102. The monostable 100 is arranged to give an output pulse duration equal to that of the narrow "C" pulse. The outputs of these are coupled to a NAND gate 104. Thus the input pulses to the gate 104 are of the same duration for a received narrow pulse and no output is generated at the output of gate 104, whercas when a wide pulse is received, the low signal from the invcrtcr 102 is of shorter duration than the high signal from the monostable 100, and the gate 104 gives an output pulse for the time difference between the two.

Figure 9 shows a detailed circuit for the pulse width modulator 46. The clock pulses from the amplitude discriminator 28 are applied by line 48 to a NOR gate 106. The input signal from ehe appropriate gate U passes to the base of a MOS gate 108. This input signal is an analog representation of the parameter to be transmitted, and acts to vary the rcsistance to earth of the MOS gate 108 and a serially connected resistor 110, thus varying the time constant of an RC circuit constituted by these and a capacitor 112. The other input of the NOR gate 106 is connected by a feedback resistor 114 to the junction point of the resistor 110 and capacitor 112. This point is also connected by a resistor 116 to the output of the NOR gate 106, both being coupled to the input of an inverting amplifier 118. The action of the circuit is as follows. On receipt of a "C" pulse on line 48, the output of the NOR gate goes low and the circuit output from the inverting amplifier goes high. After a time delay set by the RC constant of the clemcnts 108, 110, 112 (and thus by the input signal at the base of the MOS gate 108), the output of the NOR gate switches to a high state and the circuit output goes low. Hence the value of the signal at the modulator input is represented in the signal bus waveform (Fig. 3) by the ratio of the high-level signal duration to the total slot time between the two appropriate clock pulses.

The master station 18 may readily be realised by those skilled in the art with well known techniques, and will therefore not be described in detail. It will be appreciated that it includes a suitable clock circuit generating "C" and "D" level pulses repetitively, and gating means for scanning control switches on a repetitive basis. Returning signals from remote analog sensors may suitably be demodulated to analog voltage signals and applied to voltmeter-type instruments; this is suitable for parameters such as road speed, engine speed and fuel contents.

It will be seen that the invention permits the use of identical peripheral stations whose addresses can be set by simple plug-in means, with consequent simplification of manufacture, stock holding and production control. The address setting means may take different forms from the printed circuit described above. For example, the peripheral station may be connected to its associated devices via individual leads and a multicontact plug and socket, the address being set by interconnections between conductors in the plug or socket.

Further features of the electrical communication system disclosed hernia are claimed in our copending British Patent Applications Nos. 42402/77 and 42404/77 (Serial Nos.

1,589,443 and 1,589,445).

WHAT WE CLAIM IS : - 1. An electrical communication system comprising: a signal bus; a master station arranged to transmit on the signal bus pulse signals divided into serial information frames; a plurality of peripheral stations each connected to the signal bus for actuation in response to a given information frame: a corresponding plurality of connector means each electrically connecting a respective peripheral station to at least one sensor and/or controlled device and each including address setting means which sets a code determining the information frame to which each respective station responds.

2. A system according to claim 1, in which all peripheral stations are substantially identical.

3. A system according to claim 1 or claim 2, in which the connector means comprises a flexible printed circuit, and the address setting means comprises a conductive pattern in said printed circuit.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (13)

**WARNING** start of CLMS field may overlap end of DESC **. provided, enabling sixteen addresses to be encoded. Figure 6 illustrates a preferred form of amplitude discriminator. A resistor chain 76, 78, 80, 82 connected across power supply lines 84, 86. Supply line 86 is grounded and is thus at voltage level A. The resistors 76 83 are selected to give voltage levels B, C and D at the resistor junctions, and these are fed as inputs to respective comparators 88, 90, 92. The input signal on line 24 is fed in parallel to the comparators 88-92. The presence of voltage levels B, C and D is thus detected and results in an output at the respective comparator, these outputs being gated by an exclusive-OR gate 94 and OR gates 96, 98 to give the required outputs of C, D, (C or D) and (B or C). A preferred form of pulse width discriminator is shown in Figure 7. The discriminator is required only to differentiate between wide and narrow pulses, and the waveforms for each of these at various points in the circuit are shown in Fig. 8. The input from the amplitude discriminator 28 is applied in parallel to a monostable multivibrator 100 and an invcrtcr 102. The monostable 100 is arranged to give an output pulse duration equal to that of the narrow "C" pulse. The outputs of these are coupled to a NAND gate 104. Thus the input pulses to the gate 104 are of the same duration for a received narrow pulse and no output is generated at the output of gate 104, whercas when a wide pulse is received, the low signal from the invcrtcr 102 is of shorter duration than the high signal from the monostable 100, and the gate 104 gives an output pulse for the time difference between the two. Figure 9 shows a detailed circuit for the pulse width modulator 46. The clock pulses from the amplitude discriminator 28 are applied by line 48 to a NOR gate 106. The input signal from ehe appropriate gate U passes to the base of a MOS gate 108. This input signal is an analog representation of the parameter to be transmitted, and acts to vary the rcsistance to earth of the MOS gate 108 and a serially connected resistor 110, thus varying the time constant of an RC circuit constituted by these and a capacitor 112. The other input of the NOR gate 106 is connected by a feedback resistor 114 to the junction point of the resistor 110 and capacitor 112. This point is also connected by a resistor 116 to the output of the NOR gate 106, both being coupled to the input of an inverting amplifier 118. The action of the circuit is as follows. On receipt of a "C" pulse on line 48, the output of the NOR gate goes low and the circuit output from the inverting amplifier goes high. After a time delay set by the RC constant of the clemcnts 108, 110, 112 (and thus by the input signal at the base of the MOS gate 108), the output of the NOR gate switches to a high state and the circuit output goes low. Hence the value of the signal at the modulator input is represented in the signal bus waveform (Fig. 3) by the ratio of the high-level signal duration to the total slot time between the two appropriate clock pulses. The master station 18 may readily be realised by those skilled in the art with well known techniques, and will therefore not be described in detail. It will be appreciated that it includes a suitable clock circuit generating "C" and "D" level pulses repetitively, and gating means for scanning control switches on a repetitive basis. Returning signals from remote analog sensors may suitably be demodulated to analog voltage signals and applied to voltmeter-type instruments; this is suitable for parameters such as road speed, engine speed and fuel contents. It will be seen that the invention permits the use of identical peripheral stations whose addresses can be set by simple plug-in means, with consequent simplification of manufacture, stock holding and production control. The address setting means may take different forms from the printed circuit described above. For example, the peripheral station may be connected to its associated devices via individual leads and a multicontact plug and socket, the address being set by interconnections between conductors in the plug or socket. Further features of the electrical communication system disclosed hernia are claimed in our copending British Patent Applications Nos. 42402/77 and 42404/77 (Serial Nos.

1,589,443 and 1,589,445).

WHAT WE CLAIM IS : - 1. An electrical communication system comprising: a signal bus; a master station arranged to transmit on the signal bus pulse signals divided into serial information frames; a plurality of peripheral stations each connected to the signal bus for actuation in response to a given information frame: a corresponding plurality of connector means each electrically connecting a respective peripheral station to at least one sensor and/or controlled device and each including address setting means which sets a code determining the information frame to which each respective station responds.

2. A system according to claim 1, in which all peripheral stations are substantially identical.

3. A system according to claim 1 or claim 2, in which the connector means comprises a flexible printed circuit, and the address setting means comprises a conductive pattern in said printed circuit.

4. A system according to claim 1 or

claim 2 in which the connector means includes a plug and socket, the address setting means comprising interconnections between conductors of the plug or socket.

5. A system according to any preceding claim, in which each peripheral station includes a counter arranged to be incremented by each information frame, and a decode circuit connected to said counter and to said address setting means to actuate the station on receipt of an information frame identified by the address setting means.

6. A system according to any preceding claim, in which each information frame is divided by serial clock pulses into a plurality of time slots, each peripheral station is connected to a plurality of sensors and/or controlled devices, and each peripheral station includes detecting means for detecting the clock pulses and gating means controlled by said detecting means to gate signals associated with each sensor and/ our controlled device to or from the signal bus during a respective time slot.

7. A system according to any preceding claim, including a power bus, each peripheral station being connected to the power bus and including switching means for selectively coupling controlled devices to the power bus.

8. A system according to claim 7, in which the power bus and the signal bus are housed in a common insulating sheath, and each peripheral station is contained in a housing having protruding pins for insertion through the sheath to contact the buses.

9. A system according to claim 8, in which each said housing is adapted to be secured to a support to clamp the sheath thereto.

10. A system according to claim 6, or to any of claims 7, 8 and 9 when dependent on claim 6, in which each peripheral station includes a modulator responsive to one or more sensors connected to the station to modulate the signal within respective time slots.

11. A system according to any preceding claim, in which the master station is connected to a control panel provided with manually operable controls and visual displays, the master station being responsive to operation of said controls to generate signals causing actuation of corresponding controlled devices and being responsive to operation of said controls to generate signals causing actuation of corresponding controlled devices and being responsive to signals from sensors to actuate the visual displays.

12. An information handling system according to claim 1 and substantially as hereinbefore described with reference to the accompanying drawings.

13. A motor vehicle including an information handling system in accordance with any preceding claim.