GB1578554A - Methods of and arrangements for inserting digital signals into a digital-multiplex-signal - Google Patents

Abstract

In transmission of digital time division multiplex signals, there is a requirement to mask out individual signals from the transmitted TDM signal (D1) in individual intermediate stations, and replace them by new signals which are at least almost synchronous, or else to assign free time slots of the TDM signal (D1). This new addition should be possible even if the transmitted TDM signals are badly distorted or not received at all. For this purpose, a second frame clock signal, which controls the addition of the digital signals arriving at the terminals (F22an), is generated in the transmission part (ST1) from the bit cycle signal (T1) (which is generated by the receiving part (ET1)) of the received TDM signal (D1). This second frame clock signal is controlled by the synchronisation pulses derived from the frame clock signal (TC) of the received TDM signal (D1) only in interference-free operation. <IMAGE>

Description

(54) IMPROVEMENTS IN OR RELATING TO METHODS OF AND ARRANGE MENTS FOR INSERTING DIGITAL SIGNALS INTO A DIGITAL-MULTIPLEX SIGNAL (71) We, SIEMENS AKTIENGESELLSCHAFT, a German Company, of Berlin and Munich, Federal Republic of Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:: This invention relates to methods of and arrangements for inserting in an insertion point of a t.d.m. transmission system synchronous or plesiochronous digital signals into a received digital-multiplex signal which possesses a periodic frame structure consisting of a plurality of multi-bit code words and a synchronising word including a frame code, wherein a bit timing signal and a first frame timing signal which consists of individual synchronising pulses, are derived from the received digital-multiplex signal.

In the transmission of a digital-multiplexsignal which contains a plurality of transmission channels via intermediate stations in a long transmission link it is frequently necessary, in individual intermediate stations, to gate individual signals out of the digitalmultiplex-signal, and to gate-in new signals, i.e. to allocate channels which are free.

Fig. 1 of the accompanying drawings schematically illustrates a digital-multiplexdevice which serves to gate-in individual channels into a digital-multiplex-signal. The digital-multiplex-device receives a digitalmultiplex-signal having a nominal bit rate of 2048 kbit/s at an input interface F2lan, and at other input interfaces F22an receives a plurality of digital signals which emanate from telephone channels and which each have a nominal bit rate of 64 kbit/s. The 64 kbit/ s signals are inserted in the transmission channels in the digital-multiplex-signal in such a way that a new digital signal is formed which likewise possesses a nominal bit rate of 2048 kbits/s; this signal is emitted at an output interface Flab.The digital-multiplexsignal possesses a periodic pulse frame structure each pulse frame of which comprises a plurality of multi-bit code words for the transmitted signals, a synchronising word corresponding to a plurality of transmission channels, and a synchronising channel. A pulse frame structure of this type is illustrated in Fig. 2.

Fig. 2 schematically illustrates one pulse frame of a 2048 kbit/s signal having a frame period duration of 125 CLS, as laid down in the CCITT recommendation G. 732. The pulse frame consists of 32 time slots each capable of accommodating one 8-bit code word. The corresponding time slots in successive pulse frames form respective ones of 32 channels 0 to 31, of which the 30 channels 1 to 15 and 17 to 31, referred to as source channels and which are for example telephone channels, are divided into two groups CF1-15 and CF17-31. In the first channel 0 a frame code word RKW and a message word MW are transmitted, alternately in the pulse frames as synchronising words.The frame code word RKW and the message word MW are as shown in Fig. 2; bits D and N serve to communicate alarms and bits reference X and Y are provided as service bits for national and international use. Exchange-orientated characteristic information is transmitted in the channel 16, which is reference KZU in Fig. 2.

The source channels may, instead of being telephone channels, be channels in which data signals are transmitted. In this case it is possible to transmit a 64 kbit/s digital signal in each of the individual channels. It is sufficient for the 64 kbit/s signals to be at least virtually synchronous, i.e. plesiochronous, to the digital-multiplex-signal. In the event of incomplete synchronism, the bit rates are matched by means of a stuffing process, in which respect reference is directed to our co-pending U.K. Patent Application No.

20412/77 (Serial No. 1578553) filed con currently herewith.

The digital-multiplex-signal emitted via the interface Flab, has a bit rate of 2048 kbit/s and differs from the digitalmultiplex-signal received at the interface F2lan only in respect of the newly allocated time slots, i.e. the newly allocated transmission channels.

When digital signals are inserted into a digital-multiplex-signal in the manner described above, the difficulty arises that in the even of a disturbance in the frame synchronism of the incoming digital-multiplexsignal, the emitted digital-multiplex-signal also exhibits a disturbed pulse frame. As a result, the frame disturbance is transferred from one section to subsequent sections of the transmission link, so that not only the transmission of the original digitalmultiplex-signal, but also that of the inserted digital signals, is obstructed. This is particularly serious in the case of long transmission links, in which a plurality of digitalmultiplex-devices for signal insertion and signal branching are connected in a chain.

This invention seeks to provide a method by which the transmission of the inserted digital signals is made independent of disturbances in the frame synchronism of the received digital-multiplex-signal, and which prevents a propagation of a frame synchronisation disturbance from a single point via the remainder of the transmission network.

According to this invention there is provided a method of inserting in an insertion point of a t.d.m. transmission system synchronous or plesiochronous digital signals into a received digital-multiplex-signal which possesses a periodic frame structure consisting of a plurality of multi-bit code words and a synchronising word including a frame code, wherein a bit timing signal and a first frame timing signal which consists of individual synchronising pulses are derived from the received digital-multiplex signal. a second frame timing signal is produced from the bit timing signal and is used to control the insertion of the digital signals into the digitalmultiplex signal. the received frame code is suppressed and independently the frame code is re-inscrted into the digital-multiplex signal which is to be emitted, and wherein during disturbancc-free operation the second frame timing signal is controlled by synchronising pulses of the first frame timing signal and in the event of a frame synchronisation disturbance in the received digitalmultiplex signal this control of the second frame timing signal is interrupted.

The main advantage of this method is that when the digital-multiplex-devicc. which carries out the insertion, functions in a faultfree fashion, the rc-inscrted frame code is likewise always fault-frec. and in this way the propagation of a frame synchronisation disturbance is prevented with a comparatively low outlay.

Expediently the control of the second frame timing signal by the first frame timing signal is interrupted as soon as at least three consecutive frame codes have been incorrectly received.

In order to safeguard and simplify the insertion of the digital signals, preferably the entire synchronising word of the received digital-multiplex-signal is suppressed and re-inserted into the digital-multiplex signal which is to be emitted.

When the sources for the digital signals are situated at a considerable distance from one another, it is often difficult to synchronise these sources from a central station. Thus the digital signals may be plesiochronous to the received digital-multiplex-signal, in which case preferably they are inserted using a positive-negative-stuffing process and stuffing information is transmitted in a code word in the frame which is not otherwise fully used for signal transmission. In order to balance the loading of the transmission channels represented by the code words of the frame, it can be expedient to use the code word provided for characteristic transmission for the transmission of the stuffing information.

The invention also extends to an arrangement for carrying out the method recited above comprising a receiving component which has a signal input for the received digital-multiplex signal, a pulse train derivation means, and outputs at which it emits the received digital-multiplex signal, the bit timing signal, and the first frame timing signal, and a subsequently connected transmitting component to respective inputs of which said signals are emitted, wherein the receiving component contains a pulse frame monitoring device which controls the output from the receiving component of the first frame timing signal. and wherein the transmitting component possesses separate inputs for the digital signals which are to be inserted, a multiplexing device, and a device which produces the second frame timing signal from the bit timing signal.

Advantageously in the link between the output of the receiving component and the input of the transmitting component for the first frame timing signal there is provided a gate which is controlled, via a delay element, by the pulse frame monitoring in the receiving component, and further links are provided between the receiving component and the transmitting component for conducting parts of the synchronising word of ths pulse frame of the received digital-multiplex signal.

The invention will be further understood from the following description by way of example of embodiments thereof with reference to the remaining figures of the accom panying drawings, in which: Fig. 3 schematically illustrates an arrangement in accordance with an embodiment of the invention for the insertion of digital signals into a digital-multiplex signal; Fig. 4 schematically illustrates an arrangement as shown in Fig. 3 but with insertion of the entire synchronising word; and Fig. 5 schematically illustrates an arrangement for the production of timing signals in the transmitting part of the arrangement shown in Fig. 3 and 4.

The arrangement illustrated in Fig. 3 consists of a receiving component ET 1 having an input interface F21an, a transmitting component ST1 having an output interface Flab, and links between these two components for conducting a digital- multiplex signal D1, a bit pulse train T1, and a frame timing signal TC. Digital signals which are to be inserted are supplied to the transmitting component at interfaces or terminals F22an.

In the receiving component ET1 in known manner, the bit pulse train T1 is obtained from the digital-multiplex-signal D1 received via the interface F2lan, and in addition a recognition circuit contained in the receiving component recognises and monitors the frame code in known manner.

The transmitting component ST1 possesses an individual pulse train frequency divider, which produces pulse trains required for the synchronisation of the multiplexer from the bit pulse train T1 received from the receiving component ET1. A pulse train frequency divider of this type is illustrated in Fig. 5. At its output Flab, the transmitting component ST1 emits a newly produced digital-multiplex-signal which has a newly inserted frame code and contains the inserted digital signals in the provided time slots or time channels, thus in the provided code words.

In the event of a disturbance in the frame synchronism of the received digitalmultiplex signal at the terminal F21an of the receiving component ET1, the frame timing signal TC produced by the receiving component ET1 is also disturbed. In this situation, under the control of the frame recognition circuit, the emission of the frame timing signal TC is suppressed. During the disturbance of the transmitting component, at its output Flab, the latter emits a digitalmultiplex signal which contains the reinserted, prescribed frame code and the digital signal supplied at the interfaces F22an in undistrubed form, and only the information contained in those time slots which have not been re-allocated are affected by the disturbance.

Fig. 4 shows an arrangement corresponding to Fig. 3 but additionally containing a gate circuit Tor which is inserted into the link between the receiving component ET2 and the transmitting component ST2 for the frame timing signal TC. The gate circuit Tor is controlled via a drop delay element by an output A of the receiving component ET2.

The output A is connected to a frame recognition circuit contained in the receiving component ET2, and in the event of a disturbance in the frame synchronism receives a control signal which, after a delay provided by a delay element T, closes the gate circuit Tor.

The received digital-multiplex signal has a bit rate of 2048 kbit/s, and this is also the bit rate of the digital- multiplex-signal which is to be emitted via the output interface Flab. The bit rate of the four digital signals which are to be inserted is 64 kbit/s, and in the present situation these are assumed to be synchronous to the digital-multiplex-signal. The receiving component ET2 is additionally supplied with a bit pulse train having a frequency of 2048 kHz and the transmitting component ST2 is additionally supplied with the bit pulse trains of the digital signals to be inserted with a frequency of 64 kHz. To simplify the circuit, the transmitting component re-inserts not only the frame code, but the complete code word "zero", into the digital-multiplex-signal.In accordance with Fig. 2, this code word is alternately constituted by the frame code word RKW and the message word MW, which contains the two message bits D and N. As these message bits D and N are signals which characterise the state of the individual parts of the transmission link, these message bits are conducted as shown in Fig. 4 from the receiving component ET2 to the transmitting component ST2 via separate lines, and in the transmitting component are re-inserted into the code word zero. To simplify the transmission of these bits, they are converted into continuous signals in the receiving component ET2.

Investigation of frame synchronisation disturbances has indicated that in the majority of cases a faulty synchronism state does not exceed a time of 0.5 ms. For this reason, a time of approximately 1 ms is selected for the drop delay, and this forms a delay after which the gate circuit is re-opened following the elimination of the frame synchronisation disturbance.

The arrangement illustrated in Fig. 4 is intended for use in a digital interface in which both the timing signals of the digitalmultiplex-signal and those of the digital signals which are to be inserted are transmitted.

For this reason it is possible to dispense with a pulse generating circuit in the receiving component.

The arrangement illustrated in Fig. 4 also facilitates the insertion of plesiochronous digital signals into the digital-multiplexsignal. For this purpose the digital signals must be matched to the bit rate of the digital-multiplex signal by means of a positive-negative-stuffing process, for examples as described in our co-pending U.K.

Patent Application No. 20412/77 (Serial No. 1578553). In this case it is necessary to transmit advantageously in the code word 16 which is used for the transmission of the exchange-orientated characteristics, an additional item of stuffing information which occurs with a very low bit rate. For this purpose, a stuffing frame is formed, as a superframe, from 64 frames of the 2048 kbit/s digital-multiplex-signal, and in each stuffing frame on 4-bit code word of the additional information is transmitted for each of the 30 transmission channels.The frame code of the stuffing frame is transmitted in channel 16 of the 1st, 17th, 33rd, and 49th frames of the 64-frame stuffing frame, and therefore the repetition frequency of the stuffing frame is 125Hz. The frame code of the stuffing frame is contained in the first to fifth and eighth bits of the code word 16, and the sixth and seventh bits of this code word are provided for alarm messages between the terminal stations of the transmissions link.

In comparison to the digital-mutliplexdevice illustrated in Fig. 4, a digitalmuliplex-device for the insertion of virtually synchronous, i.e. plesiochronous, digital signals also contains a monitoring circuit for the stuffing frame code, an additional frequency divider which emits a pulse train frequency of 125 Hz, an additional insertion device for the stuffing frame code in the transmitting component, and a timing element which serves to control the gate circuit Tor and which, in order to eliminate stuffing frame disturbances. possesses a drop delay of approximately 8 ms corresponding to the repetition frequency of the stuffing frame of 125 Hz.

Fig. 5 illustrates an arrangement for the production of the timing signals required in the transmitting components of the arrangements shown in Figs. 3 and 4. From the bit pulse train Tl exhibiting the frequency of 2048 khz. a ninc-stage pulse train frequency divider TT provides a plurality of frequency divisions each with the factor 2:1 to produce the individually required pulse trains. Thcse pulse trains are fundamental pulse trains which each possess a pulse duty factor of 1:2, and pulse trains which are additionally required for special circumstances and which possess different pulse duty factors can easily be derived from these fundamental pulse trains by menas of gate circuits in known manner.When plesiochronous digital signal are to be inserted. a timing signal having a frequency of 125 Hz is additionally required. For this reason, for the insertion of plesiochronous signals. there is provided an additional five-stage frequency divider, which is connected to the output of the nine-stage divider TT and is controlled by the 4 kHz timing signal of the latter. The nine-stage divider TT is set via an input TC which is supplied with a signal which is inverse to the frame timing signal TC; setting of the five-stage divider is similarly effected with a signal which is inverse to the timing signal of the stuffing frame.

WHAT WE CLAIM IS: 1. A method of inserting in an insertion point of a t.d.m. transmission system synchronous or plesiochronous digital signals into a received digital-multiplex signal which possesses a periodic frame structure consisting of a plurality of multi-bit code words and a synchronising word including a frame code, wherein a bit timing signal and a first frame timing signal which consists of individual synchronising pulses are derived from the received digital-multiplex signal, a second frame timing signal is produced from the bit timing signal and is used to control the insertion of the digital signals into the digitalmultiplex signal, the received frame code is suppressed and independently the frame code is re-inserted into the digital-muliplex signal which is to be emitted, and wherein during disturbance-free operation the second frame timing signal is controlled by synchronising pulses of the first frame timing signal and in the event of a frame synchronisation disturbance in ths received digitalmultiplex signal this control of the second frame timing signal is interrupted.

2. A method as claimed in Claim 1 wherein the control of the second frame timing signal by the first frame timing signal is interrupted as soon as at least three consecutive frame codes have been incorrectly received.

3. A method as claimed in Claim 1 or Claim 2 wherein the entire synchronising word of the received digital-multiplex isgnal is suppressed and re-inserted into the digital-multiplex signal which is to be emitted.

4. A method as claimed in any of claims 1 to 3 wherein the digital signals are plesiochronous to the received digital-multiplexsignal and are inserted using a positivenegative stuffing process, and wherein stuffing information is transmitted in a code word in the frame which is not otherwise fully used for signal transmission.

5. A method as claimed in Claim 4 wherein the code word provided for characteristic transmission is additionally employed for the transmission of the stuffing information.

6. A method of inserting digital signals into a digital-multiplex signal substantially as herein described with reference to Fig. 3 to 5 of the accompanying drawings.

7. An arrangement for carrying out the

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (9)

1. **WARNING** start of CLMS field may overlap end of DESC **.

   must be matched to the bit rate of the digital-multiplex signal by means of a positive-negative-stuffing process, for examples as described in our co-pending U.K.

   Patent Application No. 20412/77 (Serial No. 1578553). In this case it is necessary to transmit advantageously in the code word 16 which is used for the transmission of the exchange-orientated characteristics, an additional item of stuffing information which occurs with a very low bit rate. For this purpose, a stuffing frame is formed, as a superframe, from 64 frames of the 2048 kbit/s digital-multiplex-signal, and in each stuffing frame on 4-bit code word of the additional information is transmitted for each of the 30 transmission channels.The frame code of the stuffing frame is transmitted in channel 16 of the 1st, 17th, 33rd, and 49th frames of the 64-frame stuffing frame, and therefore the repetition frequency of the stuffing frame is 125Hz. The frame code of the stuffing frame is contained in the first to fifth and eighth bits of the code word 16, and the sixth and seventh bits of this code word are provided for alarm messages between the terminal stations of the transmissions link.

   In comparison to the digital-mutliplexdevice illustrated in Fig. 4, a digitalmuliplex-device for the insertion of virtually synchronous, i.e. plesiochronous, digital signals also contains a monitoring circuit for the stuffing frame code, an additional frequency divider which emits a pulse train frequency of 125 Hz, an additional insertion device for the stuffing frame code in the transmitting component, and a timing element which serves to control the gate circuit Tor and which, in order to eliminate stuffing frame disturbances. possesses a drop delay of approximately 8 ms corresponding to the repetition frequency of the stuffing frame of

   125 Hz.

   Fig. 5 illustrates an arrangement for the production of the timing signals required in the transmitting components of the arrangements shown in Figs. 3 and 4. From the bit pulse train Tl exhibiting the frequency of 2048 khz. a ninc-stage pulse train frequency divider TT provides a plurality of frequency divisions each with the factor 2:1 to produce the individually required pulse trains. Thcse pulse trains are fundamental pulse trains which each possess a pulse duty factor of 1:2, and pulse trains which are additionally required for special circumstances and which possess different pulse duty factors can easily be derived from these fundamental pulse trains by menas of gate circuits in known manner.When plesiochronous digital signal are to be inserted. a timing signal having a frequency of 125 Hz is additionally required. For this reason, for the insertion of plesiochronous signals. there is provided an additional five-stage frequency divider, which is connected to the output of the nine-stage divider TT and is controlled by the 4 kHz timing signal of the latter. The nine-stage divider TT is set via an input TC which is supplied with a signal which is inverse to the frame timing signal TC; setting of the five-stage divider is similarly effected with a signal which is inverse to the timing signal of the stuffing frame.

   WHAT WE CLAIM IS: 1. A method of inserting in an insertion point of a t.d.m. transmission system synchronous or plesiochronous digital signals into a received digital-multiplex signal which possesses a periodic frame structure consisting of a plurality of multi-bit code words and a synchronising word including a frame code, wherein a bit timing signal and a first frame timing signal which consists of individual synchronising pulses are derived from the received digital-multiplex signal, a second frame timing signal is produced from the bit timing signal and is used to control the insertion of the digital signals into the digitalmultiplex signal, the received frame code is suppressed and independently the frame code is re-inserted into the digital-muliplex signal which is to be emitted, and wherein during disturbance-free operation the second frame timing signal is controlled by synchronising pulses of the first frame timing signal and in the event of a frame synchronisation disturbance in ths received digitalmultiplex signal this control of the second frame timing signal is interrupted.
2. 2. A method as claimed in Claim 1 wherein the control of the second frame timing signal by the first frame timing signal is interrupted as soon as at least three consecutive frame codes have been incorrectly received.
3. 3. A method as claimed in Claim 1 or Claim 2 wherein the entire synchronising word of the received digital-multiplex isgnal is suppressed and re-inserted into the digital-multiplex signal which is to be emitted.
4. 4. A method as claimed in any of claims 1 to 3 wherein the digital signals are plesiochronous to the received digital-multiplexsignal and are inserted using a positivenegative stuffing process, and wherein stuffing information is transmitted in a code word in the frame which is not otherwise fully used for signal transmission.
5. 5. A method as claimed in Claim 4 wherein the code word provided for characteristic transmission is additionally employed for the transmission of the stuffing information.
6. 6. A method of inserting digital signals into a digital-multiplex signal substantially as herein described with reference to Fig. 3 to 5 of the accompanying drawings.
7. 7. An arrangement for carrying out the

   method of any of the preceding claims comprising a receiving component which has a signal input for the received digital-multiplex signal a pulse train derivation means, and outputs at which it emits the received digital-multiplex signal, the bit timing signal, and the first frame timing signal, and a subsequently connected transmitting component to respective inputs of which said signals are emitted, wherein the receiving component contains a pulse frame monitoring device which controls the output from the receiving component of the first frame timing signal, and wherein the transmitting component possesses separate inputs for the digital signals which are to be inserted, a multiplexing device, and a device which produces the second frame timing signal from the bit timing signal.
8. 8. An arrangement as claimed in Claim 6 wherein in the link between the output of the receiving component and the input of the transmitting component for the first frame timing signal there is provided a gate which is controlled, via a delay element, by the pulse frame monitoring in the receiving component, and wherein further links are provided between the receiving component and the transmitting component for conducting parts of the synchronising word of the pulse frame of the received digital-multiplex signal.
9. 9. Arrangements for carrying out the method of any of Claims 1 to 6 substantially as herein described with reference to Figs. 3 to 5 of the accompanying drawings.