GB1563860A - Electronic timepiece - Google Patents

Abstract

A time-measuring device having a quartz oscillator (4) as time standard contains, inter alia, two logic circuits (5, 6), one logic circuit (6) receiving signals independent from one another in parallel and relaying the information contained therein as a time-division multiplex signal. The invention is used, in particular, for quicker detection of very slight time deviations. <IMAGE>

Description

(54) ELECTRONIC TIMEPIECE (71) KABUSHIKI KAISHA SUWA SEIKOSHA, a Japanese Company of 3-4, 4-chome, Ginza, Chuo-ku, Tokyo, Japan, do hereby declare the invention for which we pray that a patent may be granted to us and the method by which it is to be performed to be particularly described in and by the following statement : This invention relates to electronic timepieces.

According to the present invention, there is provided an electronic timepiece comprising : at least one piezo-electric oscillator means for producing a standard time signal ; logic circuit means for frequency dividing the time standard signal; feed means for feeding the standard time signal and an output signal from the logic circuit means to the exterior of the timepiece so that the dividing ratio of the logic circuit may be determined ; and display means.

Said feed means preferably comprises means for producing electromagnetic waves, light or sound waves.

The electronic timepiece may include an externally operable member for causing the time division signal to be fed to the exterior of the timepiece.

The timepiece may include antenna means for feeding the time division signal to the exterior of the timepiece. The antenna means may be constituted by a portion of the display means.

The invention is illustrated, merely by way of example, in the accompanying drawings, in which :- Figure 1 is a block diagram of a conventional electronic timepiece; Figures 2 and 3 are block diagrams of embodiments of electronic timepieces according to the present invention; Figure 4 is a circuit diagram of one embodiment of an electronic timepiece according to the present invention; Figure 5 is a block diagram illustrating the operation of the electronic timepiece of Figure 4; and Figure 6 is a block diagram of another embodiment of an electronic timepiece according to the present invention.

Figure 1 illustrates a conventional electronic timepiece having a piezo-electric oscillator 1, a logic circuit 2 comprising a frequency divider circuit and a display driving device, and a display device 3 comprising, for example, hands driven by an electro-magnetic motor, a liquid crystal display device driven by an electric field, or a light emitting diode display. The display device may indicate not only a time indication, but also, for example, the result of a calculation if a calculator is incorporated in the timepiece.

The conventional electronic timepiece has the following defects.

During assembly of a timepiece, the frequency of the piezo-electric oscillator is made to cbincide with a standard frequency electronically by means of a logic memory circuit. If the electronic timepiece subsequently fails to keep good time because the frequency of the piezo-electric oscillator changes, it is not possible to measure the running rate of the timepiece reliably using conventional measuring apparatus.

The electronic timepiece is thus very difficult to repair.

Figures 2 and 3 illustrates electronic timepieces embodying the present invention. The electronic timepiece of Figure 2 has an oscillator 4, a logic circuit 5, an additional circuit 6 which converts the signal from the oscillator into a time division signal by means of a series of frequency dividers whose state has been set to divide the signal from the oscillator by a desired amount, a display driving circuit 7 and a display device 8. The time division signal is the signal which is outputted by the frequency divider to drive the display driving circuit 7.

The electronic timepiece of Figure 3 has an oscillator 9, a logic circuit 10, a switch 11, a converting circuit 12 which converts a logic state of the logic circuit 10 into a time division signal, the switch 11 control Iing the converting circuit 12, a display driving circuit 13, and a display device 14.

The display device 14 not only displays the time indication but also can be used to display the time division signal and a standard time signal having a known relation to the fundamental frequency of the oscillator 9.

Figure 4 shows one embodiment of an electronic timepiece according to the present invention. A quartz crystal oscillator circuit includes a piezo-electric oscillator 15, an inverter 16 functioning as a driving amplifier, a phase control resistor 17, a bias resistor 18 and capacitors 19 for frequency control. The electronic timepiece has frequency divider circuits 20 to 24, and electric switching devices 25 to 27 interlock with either externally operable members or state setting circuits for setting the dividing state of the frequency divider circuits 20 to 24, the setting circuits being capable of being set by an external magnetic field, sound, an electric field, an electro-magnetic wave, or light. When the state of the divider circuits 22 to 24 coincides with the state of the switching devices 25 to 27, the output signals from exclusive NOR circuits 28 to 30 is at a high level and the output of an AND circuit 31 resets the divider circuits 22 to 24. After the divider circuits 22 to 24 have been reset, the dividing ratio of the divider circuits is decided by the switching devices 25 to 27. The output of a frequency divider circuit 33 is fed via an OR circuit 46, and a driving circuit 48, to a display device 49 to cause it to display a time of day indication.

The following is an explanation of addtional circuitry to cause the setting state of the divider circuits to be displayed. When the output signal from the AND circuit 31 changes from high level to low level, a delay circuit 34, an inverter 35 and an AND circuit 36 connected to the output of an inverter 32 resets frequency divider circuits 37 to 39. The divider circuits 37 to 39 correspond to the divider circuits 22 to 24. When the divider circuits 37 to 39 are reset, outputs of exclusive NOR circuits 40 to 42 are passed bv an AND circuit 43. The output of an inverter 44 becomes higll level so far as all the switching devices 25 to 27 are not reset to a low level.

The input signal of the frequency divider circuit 21 is a comparatively fast clock Du ! se signa ! and is fed to the divider circuit 37 via an AND circuit 45. When the count state of the divider circuits 37 to 39 coincides with the setting state of the switching devices 25 to 27, the output of the AND circuit 43 is determined by the NOR circuits 40 to 42 and becomes high level.

The divider circuits 37 to 39 are clamped until the output of the AND circuit 45 passes the inverter 44 and becomes low level, and the divider circuits 37 to 39 are reset again by the output of the AND circuit 31. Until the divider circuits 37 to 39 are reset and clamped, the output of the AND circuit 45 is fed to the OR circuit 46. An impedance control circuit 46 is provided to impedance-match the outputs of the driving circuit 48 and the AND circuit 43. Until the divider circuits 37 to 39 are reset and clamped, the clock pulse at the output of the AND circuit 45, which represents the time division signal, is displayed by the display device 49. A circuit 47 controls the display device 49 so that, when the time division signal is to be fed to the exterior of the timepiece as, for example, an electro-magnetic signal, the display device 49 is inoperative whilst the time division signal is being so fed.

Figure 5 is a block diagram illustratin the operation of the electronic timepiece of Figure 4. An output signal 50 from the divider circuit 20 in Figure 4 is fed to a programmable frequency divider circuit 51 and to one gate of an OR circuit 52, the other input of which receives the output of the divider circuit 51. The output of the OR circuit 52 is fed to a display driving circuit 53 whose output is applied to the input of an impedance control circuit 54 which also receives, as a control signal, the output of the divider circuit 51. The output of the control circuit 54 is fed to a displav device 55. Alternatively, antenna means, which may comprise the coil of a pulse motor or electrodes of a liquid crystal, may operate as an antenna for feeding the output signal from the frequency divider circuit 51 to the exterior of the timepiece.

Thus both a standard time signal which has a known relation to the frequency of the oscillator circuit and which is inputted to the frequencv divider circuit 51 at the point 50, and the output signal from the frequency divider circuit 51 are transmitted to the display device 55 and either signal may be selectively displayed thereby.

Hence the dividing ratio of the frequency divider circuit 51 may be determined, and hence the running rate of the timepiece may readily be altered by re-programming the frequency divider circuit 51 so that a desired dividing ratio is obtained.

Figure 6 shov-s a block diagram of another embodiment of an electronic timepiece according to the present invention.

The electronic timepiece has two oscillator circuits 56,57 each of which includes a piezo-electric oscillator and is temperature compensated. The electronic timepiece includes a frequency divider cicuit 59, a beat frequency generator circuit 58 whose output is a beat signal whose frequency corresponds to the difference between the frequencies of the oscillator circuits 56 and 57 and produces a temperature compensation signal which is fed to a circuit 67. The circuit 67 may be either a display driving circuit or a circuit which converts signals supplied thereto into, for example, electro-magnetic signals. A circuit 61 feeds the setting state of a pulse adder circuit 60 and corresponds to the circuits 37 to 45 in Figure 4. The circuit 61 is controlled by an electric switching device 63 and the output of AND circuit 66. The circuit 61 is controlled by a divider circuit 62 which also controls AND circuits 64,65 and the beat frequency generator circuit 58 and the appropriate clock pulse 68, and leads out in the same way as in Figure 4. After this, the circuit 62 controls the AND circuits 64,65 and the frequency of the outputs of the oscillator circuits 56,57 are led out in order after passed an OR circuit 69. The beat frequency generator circuit 58 is controlled by a signal 70 from the circuit 62.

The display device is driven by a signal produced by frequency dividing the outputs of the oscillator circuits 56,57, or a signal generated by an electric field, a magnetic field, an acoustic wave or light. It will be appreciated that it is possible to indicate the setting state of the divider circuits on a display provided specially for the purpose.

It will be appreciated that with the electronic timepieces described above it is possible to lead out from the timepiece a standard time signal directly related to the frequency of the oscillator and the setting state of a frequency divider circuit which divides the standard time signal. The setting state of the frequency divider can be led outside the timepiece without opening the case of the timepiece. The described embodiments use either one or two quartz crystal oscillators and a C-MOS divider circuit ; however, any number of oscillators may be employed. Thus non-professionals can measure the running rate of a timepiece according to the present invention relatively easily.

It will thus be appreciated that, by use of the present invention, the repair of electronic timepieces becomes extremely easy because of the improvement in the apparatus used for measuring the running rate of the timepiece, thus reducing costs.

Claims (6)

WHAT WE CLAIM IS :-

1. An electronic timepiece comprising : at least one piezo-electric oscillator means for producing a standard time signal : logic circuit means for frequency dividing the time standard signal ; feed means for feeding the standard time signal and an output signal from the logic circuit means to the exterior of the timepiece so that the dividing ratio of the logic circuit may be determined; and display means.

2. An electronic timepiece as claimed in claim t in which said feed means comprises means for producing electromagnetic waves, light or sound waves.

3. An electronic timepiece as claimed in claim 1 or 2 including an externally operable member for causing the said output signal to be fed to the exterior of the timepiece.

4. An electronic timepiece as claimed in any preceding claim including antenna means for feeding the said output signal to the exterior of the timepiece.

5. An electronic timepiece as claimed in claim 4 in which the antenna means is constituted by a portion of the display means.

6. An electronic timepiece substantially as herein described with reference to and as shown in Figures 2 to 6 of the accompanying drawings.