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GB1540450A - Self-aligning double polycrystalline silicon etching process - Google Patents

Self-aligning double polycrystalline silicon etching process

Info

Publication number
GB1540450A
GB1540450A GB35950/76A GB3595076A GB1540450A GB 1540450 A GB1540450 A GB 1540450A GB 35950/76 A GB35950/76 A GB 35950/76A GB 3595076 A GB3595076 A GB 3595076A GB 1540450 A GB1540450 A GB 1540450A
Authority
GB
United Kingdom
Prior art keywords
self
etching process
polycrystalline silicon
silicon etching
aligning double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB35950/76A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB1540450A publication Critical patent/GB1540450A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H10P50/263—
GB35950/76A 1975-10-29 1976-08-31 Self-aligning double polycrystalline silicon etching process Expired GB1540450A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US62685975A 1975-10-29 1975-10-29

Publications (1)

Publication Number Publication Date
GB1540450A true GB1540450A (en) 1979-02-14

Family

ID=24512170

Family Applications (1)

Application Number Title Priority Date Filing Date
GB35950/76A Expired GB1540450A (en) 1975-10-29 1976-08-31 Self-aligning double polycrystalline silicon etching process

Country Status (4)

Country Link
JP (1) JPS6020908B2 (en)
DE (1) DE2645014C3 (en)
FR (1) FR2330146A1 (en)
GB (1) GB1540450A (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1089299B (en) 1977-01-26 1985-06-18 Mostek Corp PROCEDURE FOR MANUFACTURING A SEMICONDUCTIVE DEVICE
JPS5419372A (en) * 1977-07-14 1979-02-14 Nec Corp Production of semiconductor memory
JPS54109785A (en) * 1978-02-16 1979-08-28 Nec Corp Semiconductor device
US4288256A (en) * 1977-12-23 1981-09-08 International Business Machines Corporation Method of making FET containing stacked gates
JPS5550667A (en) * 1978-10-09 1980-04-12 Fujitsu Ltd Method of fabricating double gate mos-type integrated circuit
JPS55105373A (en) * 1978-12-04 1980-08-12 Mostek Corp Metal oxide semiconductor transistor and method of fabricating same
US4240196A (en) * 1978-12-29 1980-12-23 Bell Telephone Laboratories, Incorporated Fabrication of two-level polysilicon devices
DE3037744A1 (en) * 1980-10-06 1982-05-19 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING A MONOLITHICALLY INTEGRATED TWO-TRANSISTOR MEMORY CELL IN MOS TECHNOLOGY
FR2468185A1 (en) * 1980-10-17 1981-04-30 Intel Corp METHOD FOR MANUFACTURING A HIGH DENSITY ELECTRICALLY PROGRAMMABLE MEMORY ARRAY
JPS5787176A (en) * 1980-11-20 1982-05-31 Seiko Epson Corp Fabrication of semiconductor device
JPS57106171A (en) * 1980-12-24 1982-07-01 Fujitsu Ltd Manufacture of semiconductor device
US4490900A (en) * 1982-01-29 1985-01-01 Seeq Technology, Inc. Method of fabricating an MOS memory array having electrically-programmable and electrically-erasable storage devices incorporated therein
IT1218344B (en) * 1983-03-31 1990-04-12 Ates Componenti Elettron PROCESS FOR THE SELF-ALIGNMENT OF A DOUBLE LAYER OF POLYCRYSTALLINE SILICON, IN AN INTEGRATED CIRCUIT DEVICE, BY MEANS OF AN OXIDATION OPERATION
JPS60187852A (en) * 1984-03-07 1985-09-25 Shimadzu Corp Electrostatic magnetic field generator for nmr ct apparatus

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3719866A (en) * 1970-12-03 1973-03-06 Ncr Semiconductor memory device
DE2139631C3 (en) * 1971-08-07 1979-05-10 Deutsche Itt Industries Gmbh, 7800 Freiburg Method for producing a semiconductor component, in which the edge of a diffusion zone is aligned with the edge of a polycrystalline silicon electrode
GB1360770A (en) * 1972-05-30 1974-07-24 Westinghouse Electric Corp N-channel mos transistor
JPS5024084A (en) * 1973-07-05 1975-03-14

Also Published As

Publication number Publication date
DE2645014A1 (en) 1977-05-12
JPS5259585A (en) 1977-05-17
FR2330146B1 (en) 1982-08-27
DE2645014B2 (en) 1979-06-07
DE2645014C3 (en) 1980-02-28
JPS6020908B2 (en) 1985-05-24
FR2330146A1 (en) 1977-05-27

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee