GB1404748A - Electronic push button combination lock - Google Patents

Abstract

1404748 Electronic locks INTEGRATED CONVERSION TECHNOLOGY Inc 4 April 1974 [6 April 1973] 14943/74 Heading E2A An electronic push-button combination lock comprises push buttons corresponding to different digits 0-9, and connected to a decimal to binary converter 11 which provides an output binary signal in response to depression of a selected button which signal defines the first input signal of a comparator circuit 12 which receives a further, coded binary signal input from coded circuits 14-17, and which is connected to a ring counter 18 having a number of stages one greater than the number of coded circuits, the comparator generating an advance signal to the counter to advance it to a next successive stage whenever the output binary signal corresponds to the coded binary signal whereby the lock 20 is opened when the last stage is reached to provide an unlocking signal thereto. The lock will not open unless the correct sequence of push buttons are depressed to provide successive output binary signals which correspond to the successive coded binary signals. If a button is wrongly depressed comparator 12 generates a reset signal 22 to restore the ring counter 18 to its start position. A timer 23 is energised upon the counter reaching its final stage which automatically resets the counter to its first stage after a given period. In the embodiment shown a single lock is applied to a door. In a modification several door locks may be provided and the coded binary signals for each door may be altered from a remote location. Each lock includes an address multiple bit shift register Fig. 3 (not shown) for effecting a serial to parallel conversion of successive bits of address information the output of which forms one input of an address comparator, the second input of which is an address code identifying the particular lock. The address code is represented by a series of address pulses from an address signal line means connected to the serial input of the address multiple bit shift register. A gate connected between a data signal line means providing a series of coded pulses representing new codes to be inserted into the lock and a code insert multiple bit shift register is controlled by an open gate signal from the address comparator to open and permit a new code to be inserted. This open gate signal is only generated when the address code supplied by the address signal line means corresponds with the address code identifying the particular lock.